جست‌وجوی استاد و پژوهشگر

Michael Norrishمشاهده پروفایل

دانشیار

• Formal Methods
• Interactive Theorem Proving
• Formal Semantics
• +۳ مورد دیگر

Dr. Michael Norrish is an Associate Professor at The Australian National University , affiliated with the School of Computing and the Mathematical Sciences Institute . He specializes in formal methods, interactive theorem proving (particularly with the HOL4 system), and formal semantics for complex systems. His work emphasizes rigorous software verification and foundational computer science research. Dr. Norrish holds a PhD in Computer Science from the University of Cambridge (1999) , along with a BA and BSc(Hons) from Victoria University of Wellington. His research has led to significant contributions in verified compilers (e.g., CakeML), formalized algorithms (e.g., AKS primality test), and reproducibility challenges in scientific software. Research Interests include: - Formal verification of theorem provers - Verified systems programming - Machine learning integration in automated reasoning - Reproducibility in computational research His recent articles focus on advancing theorem proving tools (e.g., HOL4), reproducibility debt in scientific software, and verified compiler frameworks like PureCake and Pancake. He co-organized the 15th International Conference on Interactive Theorem Proving (ITP 2024) and leads projects on AI trustworthiness in Health, Safety & Environment (Tech4HSE). Current projects include: - Tech4HSE: AI Trust & Trustworthiness (ANU, 2024–2029) - Formalization of mathematical algorithms in HOL4

• Digital Circuit Design
• Embedded Systems
• Microelectronics
• +۳ مورد دیگر

Manuel Jesús Bellido Díaz is a Full Professor at the University of Seville's Department of Electronic Technology. His research focuses on digital circuit design, embedded systems, microelectronics, and FPGA implementations. He leads the 'Investigación y Desarrollo Digital' (Digital Research and Development) group and has been involved in numerous projects, including the SEPIC project on embedded systems for critical infrastructure and the USECHIP microelectronics chair. He has advised doctoral students such as Germán Cano (2022), David Guerrero (2012), and Alejandro Millán (2008). Education: Doctorate in Electronic Engineering (University of Seville). His research interests span power optimization, timing models, and hardware/software co-design. Recent projects include secure IoT boot mechanisms (IRIS), FPGA-based time synchronization cores, and energy-efficient CMOS gate implementations. He has authored over 100 publications, including books and journal articles on topics like trigonometric computation algorithms and embedded file systems. Grants and projects include funding from TSI-020100-2008, SOL2024-31823, and OTRI/08-FCIE13. His work also involves patents for trigonometric function calculators and FPGA-oriented file systems. Labs/Teams: Active in the Digital Technology Research Group, collaborating on hardware-oriented solutions for IoT and embedded systems.

• Microelectronics
• Embedded Systems
• IoT (Internet of Things)
• +۴ مورد دیگر

Enrique Ostúa Arangüena is an Associate Professor in the Department of Electronic Technology at the University of Seville. He is part of the Digital Research and Development group and has been involved in numerous research projects focused on microelectronics, embedded systems, and FPGA-based solutions. His work includes contributions to IoT security, real-time systems, and hardware-oriented file systems. He has led or participated in projects such as USECHIP (Microelectronics Chair), Advanced Initiation Systems for IoT, and Hardware Vorbis CODEC development. His research spans digital circuit design, low-power electronics, and FPGA implementation, with emphasis on applications like time synchronization (SNTP), cryptographic hardware (E-LUKS), and embedded system optimization. He has authored chapters in books such as Grid Computing and Program of Teaching Teams for the Training of Novice Teachers , and has presented at conferences like the IBERCHIP Workshop and IEEE Symposium on Industrial Embedded Systems. Key contributions include patents on trigonometric function calculators and hardware security modules. He has collaborated extensively with researchers like David Guerrero Martos and Julián Viejo Cortés, focusing on methodologies for teaching digital electronics and FPGA-based SOC design. His work emphasizes open-source technologies, hardware-software co-design, and practical applications in industrial control systems.

PAOLO CRIPPAمشاهده پروفایل

دانشیار

• Biomedical Signal Processing
• Embedded Systems
• Neural Networks
• +۵ مورد دیگر

Prof. Paolo Crippa is an Associate Professor at the Department of Information Engineering (DII) of the University of Ancona (Università Politecnica delle Marche), Italy. His research focuses on biomedical signal processing, embedded systems, and wearable technology for healthcare applications. He specializes in neural networks, sensor design, and nanoelectronics, with notable contributions to graphene-based biosensors and real-time gesture recognition systems. His work bridges electronics, machine learning, and healthcare, addressing challenges in disease diagnosis, activity monitoring, and assistive living technologies. Prof. Crippa’s publications emphasize the development of low-power, high-accuracy systems for applications such as EEG-based disease classification, wearable sensors for activity recognition, and SARS-CoV-2 detection using advanced materials. His recent work includes optimizing LSTM neural networks for embedded platforms and integrating multimodal sensors (PPG, IMU, sEMG) for health monitoring. His research trends reveal a strong emphasis on applying machine learning to biomedical signals, improving sensor synchronization, and leveraging nanotechnology for diagnostic tools. He also explores open-source hardware/software co-design frameworks for system-on-chip (SoC) development. Prof. Crippa’s contributions extend to international collaborations and interdisciplinary projects, reflecting his role in advancing both theoretical and applied aspects of information engineering.

Kakarountas Athanasiosمشاهده پروفایل

دانشیار

• Computer Architecture
• Embedded Systems
• VLSI Circuits & Systems Design
• +۷ مورد دیگر

Dr. Athanasios Kakarountas is an Associate Professor at the University of Thessaly, specializing in Embedded Computing Systems. He leads the Intelligent Systems Laboratory (iSL) and manages ParICT, Central Greece's parallel computing node. His roles include Head of the Department of Computer Science and Biomedical Informatics, Deputy Chairman of GRNET (2019–2023), and Chair of the Central Greece Research & Innovation Committee (2018–2022). He holds an MBA from Cyprus Open University and has extensive industry experience in tech policy, innovation, and entrepreneurship. Education: BSc & PhD in Electrical & Computer Engineering (University of Patras, 1998/2004), MBA (Cyprus Open University, 2015). Research focuses on Computer Architecture, VLSI Design, TinyML, IoT Security, and Healthcare Technologies . Key projects include seizure detection systems, blockchain in supply chains, neuromorphic circuits, and cybersecurity solutions for smart cities. He has published 150+ articles, 2 e-books, and 7 book chapters, with 1,600+ citations. Awards include IEEE's Outstanding Branch Counselor Award (2013). Leadership: IEEE Greece Section Secretary (4 years), Vice-Chair (6 years), and co-Chair of the IEEE eGOV Special Committee. Editor-in-Chief of IEEE Potentials magazine, and active in organizing IEEE conferences and hackathons. Founder of A2rTEST creative team and mentor for robotics/tech competitions. Grants & Projects: Over 30 EU/Greek-funded projects. Labs/Teams: iSL, ParICT, and partnerships with Patras Science Park. Future work emphasizes TinyML for healthcare, IoT security, and smart city infrastructure.

Ataberk Olgunمشاهده پروفایل

مدرس

• Computer Architecture
• Memory Systems
• DRAM Reliability
• +۵ مورد دیگر

Ataberk Olgun is a Lecturer at the Department of Information Technology and Electrical Engineering at ETH Zürich, where he conducts research in the SAFARI Research Group under Professor Onur Mutlu. His work focuses on computer architecture with particular emphasis on memory systems, DRAM reliability, and security vulnerabilities such as RowHammer. His educational background includes BSc and MSc degrees from TOBB ETÜ (Ankara University of Economics and Technology) under Professor Oğuz Ergin's supervision. Prior to his doctoral work at ETH Zürich, he worked at Kasirgalabs until 2021, leading the design of a RISC-V system-on-chip manufactured using SKY130 technology, and previously developed authentication methods based on behavioral biometrics with Professor Kemal Bicakci. Olgun's research interests center on designing reliable and energy-efficient memory systems. He has developed FPGA-based testing platforms for DDR3/4 and HBM2 DRAM chips, created end-to-end systems for processing-in-memory techniques, and made significant contributions to understanding and mitigating the RowHammer problem. His work often combines hardware design with system-level considerations to address fundamental challenges in modern memory technology. His publication record shows consistent output in top-tier venues including ACM TACO, USENIX Security, ISCA, MICRO, and HPCA, with a clear trend toward increasingly sophisticated investigations of DRAM vulnerabilities and innovative mitigation strategies. Recent work focuses on fine-grained DRAM architectures, scalable RowHammer mitigation techniques, and experimental characterization of emerging memory technologies. As part of the SAFARI Research Group at ETH Zürich, Olgun collaborates extensively with Professor Onur Mutlu and other researchers on memory systems research. His technical expertise spans FPGA-based prototyping, DRAM characterization, hardware security, and memory controller design. Olgun maintains an active research presence with numerous ongoing projects investigating next-generation memory technologies, security vulnerabilities in modern DRAM, and energy-efficient memory system designs. His work bridges theoretical understanding with practical implementation through FPGA-based experimental platforms.

Filip De Turckمشاهده پروفایل

استاد

• Resilient Networks
• Anomaly Detection
• Large-Scale Data Processing
• +۳ مورد دیگر

Filip De Turck is a Professor at Ghent University's Department of Information Technology , leading the network and service management team. With a PhD in Engineering (2002) and a visiting postdoc at Columbia University (2003), his research focuses on resilient softwarized networks , anomaly detection , and adaptive large-scale data processing . He has supervised 38 PhD students and currently mentors 8, with an h-index of 40 and over 8952 citations. Research Interests : Resilient networks, anomaly detection, edge computing, Kubernetes orchestration, SDN, and adaptive data processing. Education : Master in Electrical Engineering (1997), PhD in Engineering (2002) from Ghent University. Leadership : Co-authored 180 Web of Science journal papers and 500+ peer-reviewed works, leading the IDLab network and service management team. Publications : Recent studies span reinforcement learning for container orchestration, haptic-enabled VR systems, and knowledge graphs for network security. Impact : Innovations in cloud-native edge computing, volumetric video delivery, and federated learning for intrusion detection.

Behrooz Parhamiمشاهده پروفایل

استاد

• Computer Arithmetic
• Parallel Processing
• Fault Tolerance
• +۴ مورد دیگر

Behrooz Parhami is a Distinguished Professor in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara, where he has been a faculty member since 1988. He previously served as Associate Dean for Academic Personnel in the College of Engineering from 2009-2012 and as Vice Chairman of the ECE Department from 1990-1992. Before joining UCSB, he was a professor at Sharif University of Technology in Tehran, Iran from 1974-1988. He received his PhD in Computer Science from UCLA in 1973. Professor Parhami's research focuses on computer arithmetic, parallel processing, and fault-tolerant computing. In computer arithmetic, he pioneered generalized signed-digit number systems as a unified framework for redundant representations. His work in parallel processing includes contributions to database processors, interconnection networks, and scalable architectures. In fault tolerance, he developed systematic data-driven methodologies for reliable hardware and software systems. He has also made significant contributions to adapting computer technology for Persian language computing. His scholarly output demonstrates consistent focus on fundamental computing principles. Recent publications show continued exploration of unconventional number systems, reliability analysis, and specialized computing architectures. His work bridges traditional computer architecture with emerging technologies including atomic-scale computing, neuromorphic systems, and novel memory technologies. His research maintains relevance through connections to both theoretical foundations and practical implementations. IEEE Life Fellow Fellow of Institution of Engineering and Technology Chartered Fellow of British Computer Society IEEE Centennial Medal (1984) Top-cited article award from Journal of Parallel and Distributed Computing (2010) IET Circuits, Devices & Systems Premium Achievement Award (2009) Sharif University Technology Association's Dr. Amin Lifetime Achievement Award (2024) Professor Parhami has graduated four PhD and numerous MS students. His teaching spans both undergraduate and graduate levels, with recent courses including ECE 1B (Puzzling Problems in Computer Engineering), ECE 252B (Computer Arithmetic), ECE 254B (Parallel Processing), and ECE 257A (Fault Tolerant Computing). He has authored six textbooks that have been widely adopted internationally, including works on parallel processing, computer arithmetic, and computer architecture. His consulting activities focus on high-performance digital system design and intellectual property issues. He is actively involved in promoting gender equity through UCSB's Men Advocating for Gender Equity (MAGE) group, which he currently chairs.

Snorre Aunetمشاهده پروفایل

استاد

• Ultra-low-voltage circuits
• Low-power CMOS design
• Subthreshold electronics
• +۹ مورد دیگر

Snorre Aunet is a Professor II in the Department of Informatics at the University of Oslo, affiliated with the Faculty of Mathematics and Natural Sciences. He is a key member of the Nanoelectronics Systems Research Group and contributes to the 4DSpace project. His academic background includes a Dr. ing. from NTNU (2002) and a cand. scient. from the University of Oslo (1993). His research focuses on ultra-low-voltage and low-power mixed-signal circuits , particularly in subthreshold operation, with applications in IoT, space systems, and energy harvesting. He specializes in radiation-hardened (radhard) and defect-tolerant architectures, leveraging advanced semiconductor technologies like 22nm and 28nm FDSOI. His work integrates circuit design, microarchitecture, and reliability under extreme conditions such as radiation exposure and process variation. The recent trend in his publications shows a strong emphasis on energy-efficient VLSI design , including SRAM cells, adders, level shifters, and flip-flops operating in subthreshold regimes. He has also expanded into MEMS-based energy harvesting and hardware security, demonstrating a broad and evolving research portfolio. His collaborations span institutions and involve both theoretical modeling and practical implementation. Scientific Awards: No specific awards mentioned in the provided text. Advising and Grants: Snorre Aunet has supervised multiple students, including Somayeh Hossein Zadeh, Even Låte, and Ali Asghar Vatanjou, whose names appear as co-authors on several publications. He is involved in the 4DSpace research project, indicating active grant funding and leadership in space-related electronics research. His advising style appears collaborative, with students contributing to high-impact journals and conferences. Labs and Teams: He is a core member of the Nanoelectronics (NANO) research group at the Department of Informatics, which focuses on next-generation electronic systems. This group is engaged in cutting-edge research in nanoscale circuits, low-power design, and robust computing architectures.

Andersen Angمشاهده پروفایل

مدرس

• Mathematical programming/optimisation
• Nonnegative Matrix Factorisation/Tensor factorisation
• Machine learning
• +۳ مورد دیگر

Dr Andersen Ang is a Lecturer at the University of Southampton, specializing in mathematical optimization, nonnegative matrix/tensor factorization, and machine learning applications. His research focuses on developing advanced algorithms for signal processing, convex optimization, and data analysis. He is actively supervising two PhD students in Computer Science and has published extensively in top-tier journals/conferences like IEEE Transactions on Signal Processing and SIAM Journal on Optimization. Dr Ang's work spans theoretical algorithm development (e.g., MGProx multigrid optimization, sparse NMF) and practical applications in source separation, biomedical interfaces, and educational technology. His recent publications emphasize graph signal processing, convex relaxation techniques, and scalable optimization methods for high-dimensional data. He maintains an active Google Scholar profile and a personal research website at https://angms.science/. While no specific awards were listed, his prolific publication record (over 25 articles since 2014) and focus on impactful optimization techniques demonstrate significant contributions to computational mathematics and machine learning communities. Current research includes inhomogeneous graph trend filtering and Riemannian optimization approaches for constrained problems.

Luke Theogarajanمشاهده پروفایل

استاد

• Neurotechnology
• CMOS Circuits
• Biosensors
• +۵ مورد دیگر

Luke Theogarajan is a Professor of Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB). His research focuses on integrating nanoscale sensors with conventional CMOS circuits, developing smart biosensors, and advancing neurotechnology through novel neural activity reporters and CMOS image sensors. He leads the Biomimetic Circuits & Nanosystems Group, exploring interdisciplinary applications in quantum computing, probabilistic hardware, and silicon photonics. Key research areas include: Probabilistic computing architectures and p-bit devices Quantum advantage in combinatorial optimization Photonic interconnects and silicon photonics for data centers Nanofabrication techniques for biosensors and neural interfaces MEMS-based retinal prostheses and neural recording systems His recent publications emphasize CMOS-compatible Ising/Potts annealing systems, high-density silicon photonic interconnects, and microneedle-based glucose sensors. Over 20 years of work includes foundational contributions to CMOS biosensors, optoelectronic oscillators, and wafer-scale integration of memristive memory. Labs/Teams: Biomimetic Circuits & Nanosystems Group (UCSB ECE Department).

• High-performance computing
• Parallel programming
• Computer architecture
• +۷ مورد دیگر

Enrique Morancho Llena is a Professor in the Department of Computer Architecture at the Barcelona School of Informatics (FIB), Polytechnic University of Catalonia (UPC). He is an active member of the UPC PM - Programming Models research group and has been affiliated with the CAP - Grup de Computació d'Altes Prestacions (High-Performance Computing Group), one of UPC's most productive research teams with over 120 publications. His academic career spans more than 30 years, with continuous research output from 1994 to the present. Dr. Morancho Llena's research spans multiple areas in computer systems, with particular expertise in high-performance computing, parallel programming models, computer architecture, operating systems, and compiler optimization. His work has evolved from early research in instruction scheduling and memory access optimization to current work on heterogeneous computing, RISC-V architecture, hardware security, and malware detection. He has made significant contributions to OpenMP programming models, GPU acceleration, and virtualization technologies, with publications in top-tier venues including IEEE Transactions on Parallel and Distributed Systems and the Journal of Parallel and Distributed Computing. His recent publications (2021-2024) show a clear trend toward heterogeneous computing architectures, security aspects of computer systems, and RISC-V based technologies. He has published extensively on OpenMP extensions for heterogeneous systems, hypervisor implementations for RISC-V, and security applications including malware detection using opcode analysis. His work bridges theoretical computer architecture concepts with practical implementations for scientific computing and security applications. Dr. Morancho Llena has supervised PhD students, with R. Gran's thesis on "Non-speculative enhancements for the scheduling logic" being one documented example. He has participated in numerous competitive research projects funded by Spanish and Catalan governments, including multiple iterations of the "Computació d'Altes Prestacions" (High-Performance Computing) projects and RISC-V related initiatives under the RIS3CAT program. His collaborations extend across UPC departments and include partnerships with the Barcelona Supercomputing Center. He is an active member of the CAP research group and the PM - Programming Models group, focusing on advanced programming techniques for high-performance systems. His work on the UPC-Computación de Altas Prestaciones series demonstrates long-term leadership in establishing UPC as a center of excellence in high-performance computing research. Current projects include work on RISC-V based accelerators, security in the computing continuum, and trustworthy development environments for cloud services.

• WebAssembly
• Formal Verification
• Memory Models
• +۳ مورد دیگر

Jean Pichon-Pharabod is a Tenure Track Assistant Professor in the Department of Computer Science at Aarhus University, Denmark, with an office at Åbogade 34 in Aarhus N. His research spans formal verification, programming languages, and computer architecture, focusing on foundational work for secure and reliable systems. His primary research interests include the formal verification of WebAssembly, relaxed memory models for architectures like Arm, and security invariants for virtualized environments. He develops mechanized proofs using frameworks like Iris and Coq to establish robust safety properties for compilers, hypervisors, and low-level systems. His work bridges hardware semantics with programming language theory to address concurrency challenges in modern architectures. Analysis of his 2021-2025 publications reveals a consistent focus on verified compilation (CertiCoq-Wasm), axiomatic semantics for relaxed architectures (AxSL logic), and memory-safe WebAssembly verification (Iris-MSWasm). His research demonstrates strong international collaboration, particularly with Lars Birkedal at Aarhus University, and targets high-impact venues like PACMPL and CPP. Key trends include mechanized separation logics for virtual machines (VMSL) and formal elucidation of hardware-software interfaces for security-critical systems.

Hernán Ponce de Leónمشاهده پروفایل

پژوهشگر

• Software Verification
• Programming Languages
• Security
• +۴ مورد دیگر

Hernán Ponce de León is a Principal Software Systems Research Engineer at Huawei Dresden Research Center (DRC) with an affiliation at Bundeswehr University Munich. His work focuses on the intersection of programming languages, security, and formal methods, particularly in developing automatic tools to verify low-level code correctness, security, and performance on emerging architectures. His research interests span Software Verification , Programming Languages , and Memory Models , with particular emphasis on weak memory consistency verification. He has made significant contributions to the field through the development of the Dat3M verification framework, which supports multiple memory models including C11, LKMM, Power, ARM, and others. Dr. Ponce de León has served on program committees for major conferences including PLDI, POPL, ECOOP, and OOPSLA, demonstrating his active engagement in the academic community. His work has been recognized with multiple SVCOMP medals and a Distinguished Paper award at OOPSLA 2022. Gold and Silver Medal @ SVCOMP 2025 Gold Medal (x2) @ SVCOMP 2024 Gold Medal @ SVCOMP 2023 Distinguished Paper @ OOPSLA 2022 As maintainer of the Dat3M verification tool, he leads a team of developers working on advancing state-of-the-art techniques for memory model verification. His recent publications focus on static analysis of memory models, SMT encodings, and consistency theories, demonstrating his continued leadership in this specialized research area.

• Computer Systems
• Operating Systems
• Distributed Systems
• +۲ مورد دیگر

Russ Ross is a Professor of Computer Science in the Department of Computing at Utah Tech University, teaching core systems courses including Computer Organization, Operating Systems, and Distributed Systems. His academic background includes: Graduation as valedictorian and National Merit Scholar from Pine View High School (1995) Bachelor of Science in Computer Science magna cum laude from Harvard University (2001) PhD in Computer Science from the University of Cambridge (2007) Research focuses on computer systems infrastructure, with teaching directly reflecting expertise in operating systems, distributed architectures, and low-level programming. Current courses demonstrate consistent engagement with hardware-software interfaces and system design principles across multiple semesters. Active mentoring occurs through CS 4800r (Undergraduate Research), where students pursue independent projects under his supervision. Office hours are maintained Monday-Thursday 3:00-4:00 PM in North Burns 226.