جست‌وجوی استاد و پژوهشگر

Ozcan Ozturkمشاهده پروفایل

استاد

• Heterogeneous Computing
• Hardware Accelerators
• GPU Computing
• +۷ مورد دیگر

Ozcan Ozturk is a Professor in the Computer Science and Engineering and Electronics Engineering programs at Sabancı University's Faculty of Engineering and Natural Sciences. Previously, he held professorships at Bilkent University and adjunct roles at North Carolina State University. His expertise spans heterogeneous computing, parallel systems, processor architecture, and compiler optimization. He earned his Ph.D. from Penn State University, with prior academic roles at the University of Florida and internships at Intel and Marvell. Education: Ph.D. in Computer Science and Engineering (2007), Pennsylvania State University M.S. in Computer Engineering (2002), University of Florida B.Sc. in Computer Engineering (2000), Bogazici University Research interests include accelerator technologies, GPU-based systems, multicore processors, and compiler optimizations. His work focuses on improving parallelization efficiency, energy optimization, and reliability in heterogeneous architectures. He leads funded projects like 'Machine Learning for Compiler Flags' and 'Graph Accelerator Design'. Notable awards include the Bilkent Teaching Award (2019), BAGEP (2018), and HiPEAC Paper Award (2016). He serves on editorial boards of IEEE and ACM journals and chairs major conferences like ASPLOS and ICS. Grants and collaborations include partnerships with Huawei, Intel, NVIDIA, and TÜBİTAK. He advises over 20 students and has supervised projects in safety-critical systems, FPGA accelerators, and compiler-directed optimizations. His lab develops domain-specific architectures, including RISC-V extensions for graph processing.

• Compilers
• Computer Architecture
• High-level Synthesis
• +۵ مورد دیگر

Scott Mahlke is a Professor and Associate Chair in the Electrical Engineering and Computer Science Department at the University of Michigan. He is affiliated with the Advanced Computer Architecture Laboratory and the Software Systems Laboratory, where he leads the Compilers Creating Custom Processors (CCCP) research group. His research focuses on compilers, computer architecture, and high-level synthesis, with particular emphasis on designing next-generation computer systems that overcome challenges in performance, power consumption, and reliability. His work bridges the gap between hardware and software through innovative compiler technology that enables customized processors and accelerators. Mahlke's publications demonstrate a strong focus on compiler techniques for exploiting instruction-level parallelism, memory system optimization, and application-specific processor design. His research spans from fundamental compiler algorithms to practical implementations in both general-purpose and embedded systems. National Science Foundation CAREER Award (2003) Morris Wellman Faculty Development Assistant Professor (2004) 2006 ISCA Most Influential Paper Award Multiple best paper awards at major architecture conferences As an advisor, Mahlke has chaired numerous Ph.D. dissertations and actively mentors graduate students in the CCCP group. His research is generously funded by the National Science Foundation, Gigascale Systems Research Center, ARM Ltd., Samsung Advanced Institute of Technology, and other major organizations. The CCCP group maintains strong industry partnerships that facilitate the transfer of research innovations to practical applications.

Mark Oskinمشاهده پروفایل

استاد مدعو

• Computer Architecture
• Parallel Computing
• Graph Processing
• +۱۲ مورد دیگر

Mark Oskin is an Adjunct Professor at the School of Computer Science and Engineering , University of Washington , focusing on Software & Hardware Systems . He leads the Sampa Group and collaborates on projects like HammerBlade and BlackParrot. University: University of Washington School: School of Computer Science and Engineering Department: Department of Electrical & Computer Engineering His research spans Computer Architecture , Parallel Computing , and Graph Processing , with additional expertise in Quantum Computing , Open Source Hardware , and Distributed Shared Memory . Ongoing work includes custom manycore devices for graph execution and open-source RISC-V designs. Past projects like Grappa and WaveScalar advanced distributed memory and dataflow execution. Recent publications include BlackParrot: An Agile Open Source RISC-V Multicore for Accelerator SoCs (IEEE Micro 2020) and Perceptual Compression of Video Storage and Processing Systems (SoCC 2019), reflecting trends in hardware-software co-design, quantum systems, and energy-efficient video processing. Best Paper Award , USENIX ATC 2015 IEEE Micro Top Picks , 2009 Mark has advised numerous students, including Amrita Mazumdar (IoT video compression startup), Brandon Lucia (CMU), and Steve Swanson (UC San Diego). He co-founded Corensic, a startup exploring deterministic multithreaded execution.

Alberto Rosمشاهده پروفایل

استاد

• Computer Architecture
• Parallel Processing
• Multicore Processors
• +۵ مورد دیگر

Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.

Gurindar S. Sohiمشاهده پروفایل

استاد

• Computer Architecture
• Parallel Computing
• Memory Systems
• +۳ مورد دیگر

Gurindar S. Sohi is a Vilas Research Professor , John P. Morgridge Professor , and E. David Cronon Professor of Computer Sciences at the University of Wisconsin-Madison , affiliated with both the College of Engineering (Department of Electrical and Computer Engineering) and the Department of Computer Sciences . He served as Department Chair of Computer Sciences from 2004 to 2008 and has been a faculty member since 1985. Education: Ph.D. in Electrical and Computer Engineering from the University of Illinois (1985) Sohi's research focuses on high-performance computer architecture , particularly instruction-level parallelism (ILP) , multiscalar processing , and speculative execution techniques . His work has influenced commercial microprocessor design through innovations like non-blocking caches , memory dependence prediction , and trace caches . Key publications represent 15+ years of research in dynamic scheduling , parallel computing paradigms , and processor simulation tools (e.g., Simplescalar). Industry collaborations span major manufacturers like Intel , IBM , and HP . Scientific recognition includes: ACM SIGARCH Maurice Wilkes Award (1999) Vilas Associate (1997) WARF Kellett Mid-Career Award (2000) WARF Named Professor (2007) ACM and IEEE Fellow National Academy of Engineering member Teaching contributions include advanced courses on computer architecture (CS/ECE 752, 757) and foundational computer organization classes (CS/ECE 354, 552). He has graduated 18 Ph.D. students , including six NSF CAREER awardees and a Sloan Research Fellow.

• Computer Architecture
• Vector Processors
• GPU Microarchitecture
• +۹ مورد دیگر

Roger Espasa Sans is a senior academic and researcher at the Universitat Politècnica de Catalunya (UPC), affiliated with the Faculty of Informatics of Barcelona (FIB) and the Department of Computer Architecture. He has made significant contributions to computer architecture, particularly in vector processing, GPU design, and performance optimization. Universitat Politècnica de Catalunya (UPC) Faculty of Informatics of Barcelona (FIB) Department of Computer Architecture His research focuses on advanced computer architecture, including vector and superscalar processors, memory systems, instruction-level and data-level parallelism, GPU microarchitecture, and performance modeling. His work bridges theoretical design and practical implementation, especially in high-performance and embedded systems. The recent articles highlight a strong trend in GPU and shader optimization, memory redundancy elimination, and performance modeling. His publications span prestigious venues such as IEEE Microarchitecture Symposium, IEEE HPCA, and The Visual Computer, indicating sustained impact in the field of computer systems and architecture. Premiada (Awarded activity) Roger Espasa Sans has advised several doctoral students, including Manel Fernandez Gomez and Francisca Quintana Domínguez, contributing to the next generation of computer architects. His collaborative network is extensive, involving key figures like Mateo Valero and international institutions. While specific grants are not listed, his prolific output suggests sustained funding. He has contributed to major research groups such as CAP (High Performance Computing Group). He is a core member of the CAP - Grup de Computació d'Altes Prestacions (High Performance Computing Group), and has also been associated with PM - Programming Models and ARCO - Microarchitecture and Compilers. His work often involves simulation frameworks like JINKS and Asim, indicating a strong focus on performance evaluation and modeling.

John Paul Shenمشاهده پروفایل

استاد

• Modern Processor Design
• Instruction-Level Parallelism
• Dependable Computing
• +۳ مورد دیگر

John Paul Shen is a Distinguished Service Professor of Electrical and Computer Engineering at Carnegie Mellon University (CMU), based at the Silicon Valley campus. With over three decades of experience in academia and industry, he has held prominent roles including founding director of Nokia Research Center-North America Lab (2007–2012) and director of Intel’s Microarchitecture Research Lab (2000–2006). His academic career includes a tenured professorship at CMU’s ECE Department from 1990–2000 and a return to CMU in 2015 as a tenured professor. Education: Ph.D. in Electrical Engineering, University of Southern California M.S. in Electrical Engineering, University of Southern California B.S. in Electrical Engineering, University of Michigan Research Focus: Modern Processor Design: Specializes in superscalar processors, instruction-level parallelism (ILP), and microarchitecture validation tools like VMW (Visualization-Based Microarchitecture Workbench). Neuromorphic Computing: Develops energy-efficient temporal neural networks (TNNs) and CMOS implementations for sensory processing. Edge AI: Focuses on low-precision accelerators, sparsity exploitation, and real-time data analytics for edge devices. Dependable Computing: Leverages idle processor resources for error-checking and fault tolerance. Awards & Impact: Recipient of multiple teaching awards during his CMU tenure. Supervised 17 Ph.D. students and dozens of M.S. students, with notable contributions to compiler design and parallel computing. Authored two influential textbooks, including Modern Processor Design: Fundamentals of Superscalar Processors , used at Stanford. Generated over 100 patents and 200+ papers at Nokia and Intel, with a focus on mobile computing and hardware architecture innovations. Labs & Collaborations: Founded and led the Nokia Research Center-NAL, advancing mobile Internet and computing. Directed Intel’s Microarchitecture Research Lab, advancing IA32/IA64 processor designs. Current research at CMU Silicon Valley focuses on neuromorphic systems, wearable computing, and real-time data analytics.

Utpal Boraمشاهده پروفایل

پژوهشگر

• Computer Architecture
• Programming Languages
• Semantics
• +۳ مورد دیگر

Utpal Bora is a Researcher at the University of Cambridge's Department of Computer Science and Technology. His research focuses on Programming Languages, Semantics, Verification, and Computer Architecture with an emphasis on static analysis of parallel programs, compiler optimization techniques, and performance analysis. He has contributed to projects such as LLOR (automated OpenMP program repair) and Llov (static data-race detection for OpenMP). His work bridges compiler design, parallel computing, and formal methods to improve software reliability and hardware efficiency. Research Interests: Static Analysis of Parallel Programs Compiler Optimization (LLVM) Data-Race Detection in OpenMP Instruction-Level Parallelism (ILP) Performance Modeling (CPI Analysis) Formal Verification of Concurrent Systems Recent work trends show a focus on enhancing parallel programming correctness through automated repair and static analysis tools, alongside optimizing code execution via compiler-level transformations and hardware architecture improvements. His contributions address critical challenges in parallel computing scalability and compiler-driven performance enhancement.

Manoj Franklinمشاهده پروفایل

دانشیار

• Computer Architecture
• Instruction-Level Parallel (ILP) Processing
• Compiling for ILP Machines
• +۳ مورد دیگر

Manoj Franklin is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Maryland, affiliated with Maryland Applied Graduate Engineering. He is based in A.V. Williams 1333 and can be reached at manoj@umd.edu. His research focuses on computer architecture, specifically instruction-level parallel (ILP) processing, compiling for ILP machines, memory systems, fault-tolerant computing, and digital logic testing. Franklin has received notable recognition, including the NSF CAREER Award (1997) and Clemson University's Board of Trustees Faculty Excellence Award (1997). His work has also been supported by the NSF Research Initiation Award (1994-1997). He has contributed to mentoring students, with alumni such as Mohamed Zahran (recognized with the IEEE Computer Society Award) and Neehar Peri (Undergraduate Researcher of the Year, now pursuing a PhD at Carnegie Mellon University). Franklin has also been honored for service to the ECE Department at the ECE Welcome Back Reception.