David H. Albonesi is a Professor in the Computer Systems Laboratory at Cornell University's School of Electrical and Computer Engineering. His research focuses on power-efficient computer architectures, including reconfigurable systems, accelerator design for deep learning, smart buildings, and silicon nanophotonics interconnects. He has held leadership roles in major conferences like ISCA and MICRO, and serves on editorial boards for IEEE Computer and IEEE Micro. Research interests span adaptive architectures for dynamic power management, sparse matrix/tensor accelerators, and energy-efficient smart building systems. His work bridges hardware-software co-design, emphasizing phase-aware resource allocation and energy minimization. Awards include the IEEE Fellow distinction, NSF CAREER Award, and multiple teaching accolades from Cornell. Over 30 years of industry-academic collaboration has led to innovations in GALS microarchitectures, clustered multi-threaded processors, and thermal-aware scheduling. Key contributions include the CuttleSys reconfigurable multicore framework, MatRaptor sparse matrix accelerator, and foundational work in silicon photonics for on-chip interconnects. Patents cover dynamic core power management and adaptive microprocessor designs.
Professor Jon Kerridge is a distinguished academic at the School of Computing, Edinburgh Napier University, where he has made significant contributions to parallel programming, software systems, and database applications. With a career spanning several decades, he has published extensively in the field of computer science and has supervised numerous PhD students. BSc, MSc, PhD Fellow of the British Computer Society (FBCS) Chartered IT Professional (CITP) Fellow of the Higher Education Academy (FHEA) Chartered Engineer (CEng) Professor Kerridge's research primarily focuses on parallel programming models, particularly through his work on the Groovy Parallel Patterns Library and Communicating Sequential Processes (CSP). His research spans multiple domains including software engineering, database systems, and interdisciplinary work in neuroscience related to dyslexia. He has also made significant contributions to pedestrian movement modeling and evolutionary algorithms. His publications demonstrate a consistent focus on practical software engineering solutions for parallel and distributed systems. The research trajectory shows progression from foundational work in computer architecture education in the 1980s through database systems in the 1990s-2000s to modern parallel programming frameworks. His interdisciplinary work connecting computer science with visual processing in dyslexia represents an innovative application of computational approaches to neuroscience problems. Fellow of the British Computer Society (FBCS) Chartered IT Professional (CITP) Fellow of the Higher Education Academy (FHEA) Chartered Engineer (CEng) Professor Kerridge has supervised several PhD students to completion, including Kevin Chalmers (Investigating communicating sequential processes for Java to support ubiquitous computing) and Robert Kukla (A software framework for the microscopic modelling of pedestrian movement). His research has been supported by Edinburgh Napier University funding, with applications ranging from healthcare systems to pedestrian flow optimization. He is a key member of the Centre for Algorithms, Visualisation and Evolving Systems at Edinburgh Napier University, where his work continues to influence both theoretical and applied aspects of computing.
Dr. Robert K. Chun is a Professor in the Department of Computer Science at San José State University (SJSU), part of the College of Engineering. He holds a BSEE (1979), MSCS (1981), and Ph.D. (1989) from UCLA. With 20+ years in industry, he joined SJSU as a full-time faculty in 2001. His research focuses on Cloud Computing, parallel processing, high-performance architectures, and AI. He received NASA Faculty Fellowships (2002-2003) and holds a U.S. patent for real-time expert systems integration. Education: Bachelor of Science, Electrical Engineering, UCLA (1979) Master of Science, Computer Science, UCLA (1981) Doctor of Philosophy, Computer Science, UCLA (1989) Research Interests: Cloud Computing architectures and scalability High-performance computing and parallel algorithms Software engineering for distributed systems CAD tools for VLSI design verification Artificial intelligence and neural networks Publications highlight advancements in parallel processing, distributed systems, and compiler optimization. Notable works include adaptive transactional memory algorithms, wireless cluster computing frameworks, and EJB performance measurement tools. His NASA-funded research at Ames Supercomputing Center explored parallel computing applications. Advising and Grants: Advised 16 Master’s theses, including topics like dynamic clusters and intelligent debuggers Contributed to industry-university partnerships through NASA collaborations Labs/Teams: Active in SJSU’s parallel processing and computer architecture research groups, contributing to course development in advanced parallel processing and operating systems.
Dr. Richard W Sharp is a Research Fellow at the University of Cambridge , with expertise in virtualization, computer security, and hardware synthesis. His work bridges foundational research in programming languages and practical applications in cloud computing and secure systems. BA, Computer Science (1999, Robinson College, University of Cambridge) PhD, Computer Science (2003, University of Cambridge) MBA (2012, Judge Business School) Dr. Sharp's research spans virtualization environments , operating systems , and security policy enforcement . He has pioneered techniques for network policy implementation , storage optimization , and VM migration , with a focus on heterogeneous systems and resource allocation. His publications highlight trends in functional programming applications, secure mobile computing, and hardware/software co-design. Dr. Sharp also contributes to functional programming in industrial contexts and security frameworks for web applications. Despite no formal awards listed, his work in virtualization and security synthesis remains influential.
Stephen Crago is an Associate Director at the USC Information Sciences Institute (ISI) and serves as Director of the Computational Systems and Technology (CS&T) division and the ISI Arlington site since 1997. He holds a joint appointment as a Research Associate Professor in the Ming Hsieh Department of Electrical and Computer Engineering at the University of Southern California. Education : Ph.D. in Electrical Engineering from USC, M.S. and B.S. in Computer and Electrical Engineering from Purdue University His research interests focus on heterogeneous computing, high-performance and embedded cloud computing, introspective systems, and parallel software development. He explores methods to optimize performance, power efficiency, and productivity in highly parallel, heterogeneous systems, driven by challenges in scaling multi-core processors. Dr. Crago’s work has been funded by DARPA, NASA, and the Office of Naval Research (ONR), spanning projects from small-scale research to large interdisciplinary collaborations. He leads the CS&T division, contributing to advancements in computational systems and technology.
Luigi Pomante is a tenured Assistant Professor at the University of L'Aquila, Italy, where he is affiliated with the Department of Engineering and Information Science and Mathematics (DISIM) and the DEWS Center of Excellence. His academic career focuses on research and teaching in embedded systems and hardware-software co-design methodologies. Dr. Pomante's primary research interest is Electronic System-Level Hardware-Software Co-Design of heterogeneous parallel dedicated systems. He is the principal developer of the HEPSYCODE framework, which provides comprehensive methodologies and tools for system-level design space exploration. His work addresses critical challenges in embedded systems development, including handling functional and non-functional requirements, heterogeneous architectures, and mixed-criticality constraints. He has published extensively in journals like IEEE Transactions on Computers and IET Computers & Digital Techniques, as well as at major international conferences. Analysis of Dr. Pomante's publication record reveals a consistent research trajectory focused on hardware-software co-design methodologies, with increasing attention to real-time constraints and mixed-criticality systems in more recent work. His publications demonstrate expertise in design space exploration techniques, system modeling using CSP-like approaches, and the development of metrics for evaluating hardware-software partitioning solutions. The HEPSYCODE framework represents his most significant contribution to the field. Dr. Pomante actively supervises student projects and theses related to electronic design automation and embedded systems. He has contributed to European research projects including EMC2 (Embedded Multi-Core systems for Mixed Criticality applications), where he was responsible for deliverables related to design methodologies, implementation approaches, and validation frameworks. His work has practical applications in aerospace and other safety-critical domains through collaborations with industry partners. He leads the HEPSYCODE research group at DEWS, which focuses on developing methodologies and tools for hardware-software co-design of heterogeneous parallel dedicated systems. The group's current work includes extensions for real-time and mixed-criticality systems, frameworks for embedded system monitoring, and techniques for handling approximate computing and energy/power constraints within the design space exploration process.
Javier Verdu Mula is a Professor at the Departament d'Arquitectura de Computadors (Universitat Politècnica de Catalunya - UPC) and a key researcher at the CRAAX - Centre de Recerca d'Arquitectures Avançades de Xarxes . His work focuses on computer architecture, parallel processing, and networking systems. Fields of Research include RISC-V virtualization, multithreaded processor optimization, and performance analysis of stateful networking applications. Scientific Awards include the BDigital Global Congress (2015) and Wayra Barcelona (2012) recognitions. Collaborations span institutions like Barcelona Supercomputing Center and researchers such as Manuel Alejandro Pajuelo, Mateo Valero Cortes, and Mario Nemirovsky. His recent publications address RISC-V hypervisor extensions, deep packet processing in parallel architectures, and statistical thread assignment models. He also holds patents in hardware virtualization and resource control systems.
Professor Martin Schoeberl is affiliated with the Department of Applied Mathematics and Computer Science at the Technical University of Denmark (DTU). His research focuses on real-time systems, worst-case execution time analysis, and embedded systems engineering. He is actively involved in projects such as Rigoletto, aiming to develop high-performance automotive processors using RISC-V architecture. Research Interests: Schoeberl's work spans time-predictable processors, network-on-chip architectures, and hardware-software co-design for cyber-physical systems. He explores methodologies to ensure deterministic behavior in multicore environments and develops tools for WCET analysis. His contributions include advancements in compiler optimizations for neural networks and temporal semantics in embedded systems. Advising & Grants: Schoeberl supervises PhD students such as E. Khodadad (on rigorous design of time-predictable systems) and A. Cerioli (on compiler optimizations for neural networks). He leads or participates in funded projects including Rigoletto (2025-2028) and Multi-Core Architecture for L1 Deterministic Processing (2022-2025). These projects aim to enhance real-time capabilities in embedded systems and automotive computing platforms. Labs & Teams: As part of the Embedded Systems Engineering group at DTU, Schoeberl collaborates on hardware generators using Chisel and designs reactor-oriented architectures for cyber-physical systems. His work integrates reconfigurable logic and synchronous models to create efficient, time-predictable solutions.
Benedict Herzog is a Researcher at the Bochum Operating Systems and System Software (BOSS) group at Ruhr-Universität Bochum (RUB). Previously, he was part of the Department of Computer Science 4 (Distributed Systems and Operating Systems) at Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU). His work focuses on energy-efficient systems, operating systems optimization, and embedded computing. Herzog holds a Master's degree in Computer Science from FAU, where his thesis explored energy demand estimation using artificial neural networks, and a Bachelor's degree in Energy-aware error correction in wireless sensor networks. His research interests span energy-aware computing, system software design, and machine learning applications for optimizing edge and embedded systems. He actively participates in academic activities, serving as a reviewer for conferences like TECS, SBESC, and EMSOFT. Herzog has taught courses such as 'Systemnahe Programmierung in C' and 'Energy-Aware Computing Systems' at FAU, and advised multiple students on topics ranging from interrupt handling overhead to Meltdown/Spectre mitigation impacts. Key technical contributions include frameworks for energy measurement integration (EnergyBudgets), system-call aggregation (AnyCall), and automated OS configuration optimization. His work bridges hardware-software co-design challenges in energy efficiency, with applications in edge computing and real-time systems.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and the founder and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research and Technology – Hellas (FORTH) in Heraklion, Crete, Greece. He has held academic positions since 1986 and played a pivotal role in establishing the Computer Science Department at the University of Crete. His research spans computer architecture, interconnection networks, VLSI systems, and high-performance computing, with a strong focus on scalable, low-power, manycore systems and RISC-V. He has led numerous European R&D initiatives, including serving as Coordinator of the ExaNeSt project. PhD in Computer Science, University of California, Berkeley (1983) MSc in Electrical Engineering and Computer Science, University of California, Berkeley (1980) Diploma of Electrical Engineering, National Technical University of Athens (1978) Manolis Katevenis's research focuses on advancing scalable system architectures for high-performance and big data computing. His work in computer architecture includes RISC-V, exascale computing, and manycore systems. He has made foundational contributions to interprocessor communication, particularly through remote-write, remote-DMA, and remote-enqueue mechanisms, and has pioneered innovations in interconnection networks and low-latency network interfaces. His research integrates hardware and software co-design to optimize performance, energy efficiency, and scalability in large-scale computing systems. The recent publications highlight a strong trend in exascale computing, interconnection networks, and FPGA-based prototyping of manycore systems. His work emphasizes scalable, low-power architectures, with recurring themes in congestion management, fair scheduling, crossbar design, and hardware-software integration for HPC. The articles span high-impact journals such as IEEE/ACM Transactions on Networking, IEEE Micro, and Computer Networks, reflecting sustained contributions to computer architecture and networking. ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981–1983) Greek State Fellowship (1973–1978) Stelios Pichoridis Award for Outstanding University Teaching (2015) Member of Academia Europaea (elected 2012) Award by the Secretary General of the Region of Crete (2003) IEEE Milestone recognition for the RISC Project (2015) Manolis Katevenis has supervised over 50 graduate theses and mentored many prominent Greek computer architects, including recipients of the ACM Maurice Wilkes Award. He has served as Principal Investigator or co-PI in over 30 R&D projects with a total budget exceeding 18 million euros, including major European initiatives such as ExaNeSt (which he coordinated), EuroEXA, EcoScale, SARC, ENCORE, and multiple HiPEAC Network of Excellence projects. His leadership extends to project coordination, architectural design, FPGA prototyping, and systems software development. Katevenis founded and leads the CARV Laboratory at FORTH-ICS, a major research team with 80–100 members focused on computer architecture and VLSI systems. The lab has spun off the Distributed Computing Systems (DCS) Laboratory and is central to European exascale computing efforts, including participation in the European Processor Initiative. CARV has developed large-scale prototypes such as the 768-core ExaNeSt system and the Formic FPGA platform for manycore research.
Joachim Falk is a researcher at the Department of Hardware-Software Co-Design (Computer Science 12) at Friedrich Alexander University Erlangen-Nuremberg. With over 20 years of experience since joining the department in 2004, he specializes in electronic system level design, dataflow programming, and hardware-software co-design, contributing significantly to the field through publications, teaching, and research leadership. His educational background includes: Doctorate degree (Dr.-Ing.) in Computer Science from FAU (2014) Diploma degree in electrical engineering (data processing) from Georg-Simon-Ohm University of Applied Science Nuremberg (2002) Falk's research focuses on Electronic System Level Design, Hardware/Software Code Generation for Data-Flow Graphs, Compiler Optimizations, and Parallel Architectures. His work bridges theoretical computer science with practical embedded systems implementation, particularly through the SystemC framework and his contributions to the SysteMoC language. He actively explores energy-efficient computing approaches for dataflow networks and embedded systems, with recent work emphasizing self-powering networks, clock and power gating techniques, and multi-reader buffer implementations for heterogeneous architectures. His recent publication trends reveal a consistent focus on optimizing dataflow networks for energy efficiency and performance. Key themes include self-powering dataflow networks, innovative clock and power management techniques, buffer management strategies for heterogeneous many-core systems, and invasive computing approaches. His research demonstrates a strong connection between theoretical models and practical implementation challenges in embedded systems design. Dr. Falk teaches courses including 'Entwicklung interaktiver eingebetteter Systeme' (Development of Interactive Embedded Systems) for Winter Semester 2024/2025 and 'SystemC' for Summer Semester 2024, supervising multiple theses on security modeling at the electronic system level and sleep/wake-up strategies for hardware implementations of dataflow networks. His research is conducted within the framework of projects like SysteMoC (representation of computational models in SystemC) and SystemCoDesigner (design space exploration for embedded systems).
Alexander Wold is an Associate Professor at the University of Oslo, affiliated with the Research Group for Robotics and Intelligent Systems within the Faculty of Mathematics and Natural Sciences. His work focuses on reconfigurable computing, embedded systems, and robotics, with notable contributions to FPGA design, real-time systems, and educational technology. He holds a position at the Institute of Informatics (IFI) and can be contacted at alexawo@ifi.uio.no . Research interests include optimizing hardware-software co-design, thermal management in 3D-IC systems, and developing open-source tools like EasyPR for pattern recognition. His publications span topics such as remote cloud labs for reconfigurable logic education, network traffic management in industrial Ethernet, and constraint programming for module placement in FPGAs. Dr. Wold’s articles reflect a strong emphasis on practical applications of robotics and intelligent systems, with a focus on safety-critical industrial systems and autonomic computing. He has contributed to multi-core system design, thermal-aware FPGA architectures, and self-aware systems.
Sarma Vrudhula is a Professor at the School of Computing and Augmented Intelligence, Arizona State University (ASU). He holds a Ph.D. in Electrical Engineering from the University of Southern California (1985). Previously, he was a professor at the University of Arizona and served as the founding director of the NSF UA/ASU Center for Low Power Electronics. He is an IEEE Fellow recognized for contributions to low-power and energy-efficient digital circuit design. Educations: Ph.D. Electrical Engineering, University of Southern California (1985) M.S. Electrical Engineering, University of Southern California (1980) Bachelor's in Mathematics (Computer Science and Mathematical Statistics), University of Waterloo, Canada (1976) Research Interests: His work focuses on design automation, energy management in digital systems, statistical analysis of process variations, threshold logic circuits, and emerging technologies. He has pioneered methodologies for low-power VLSI design, thermal management of multi-core processors, and hardware implementations of threshold logic using spintronic devices. Publications: His recent research includes scalable energy-efficient architectures for AI, in-memory computing, and reconfigurable threshold logic gates. Key topics span energy efficiency in edge computing, neuromorphic systems, and sustainable VLSI design. Awards: IEEE Fellow (2005) Best Paper Award (2008) for macro cell characterization methodology Service & Grants: He led the NSF IUCRC Consortium for Embedded Systems and served on editorial boards. His grants include projects on threshold logic synthesis, energy-aware embedded systems, and hardware acceleration for neural networks. Courses Taught: Algorithmic Foundations of CAD for Digital Systems Computer Architecture Discrete Mathematics for Engineers
Dr. Park Ki-ho is an Associate Professor at the Department of Computer Engineering, Sejong University. His research focuses on computer architecture, embedded systems, IoT systems, and low-power design methodologies. Academic Background: PhD in Computer Science from Yonsei University Professional Experience: Senior Engineer at Samsung Electronics, Post-Doctoral Research Associate at University of Utah Research Interests: Develops innovative solutions for sensor hub design , memory systems , and machine learning hardware acceleration . Key areas include: Non-Volatile Memory (NVM) management 3D Integrated Circuit memory bandwidth optimization Intelligent Edge Device architectures Hybrid Cache Architectures Model Compression Techniques On-Device AI Processing Recent Publications demonstrate expertise in in-memory acceleration , sparse matrix representation , and large language model inference . His work bridges theoretical advancements with practical implementations for IoT and AI applications.
Prof. A.D. Pimentel holds a full professorship at the Informatics Institute of the University of Amsterdam, leading the Parallel Computing Systems (PCS) group within the Systems and Networking Lab. His research focuses on multi-core and multi-processor systems, emphasizing performance, energy efficiency, dependability, and productivity in system design and runtime management. He earned his PhD and MSc in Computer Science from the University of Amsterdam in 1998 and 1993, respectively. Current roles: Chair of PCS group, Board member of Advanced School for Computing and Imaging (ASCI), and ICT Research Platform Nederland (IPN) Teaching: Courses on Multi-core Processor Systems, Embedded Software, and Architecture Research interests span edge AI, sustainable computing, and system-level modeling. Recent work includes innovations in energy-efficient scheduling, thermal management in 3D-stacked systems, and adaptive CNN inference at the edge. Over 25 years of contributions to embedded systems design space exploration and hardware/software co-design have been recognized through awards like the IEEE CEDA Outstanding Service Award (2025). Awards: IEEE DATE Fellow (2025), NWO Knowledge & Innovation Covenant grant lead Active in conference organization, serving as General Chair for Embedded Systems Week (2026) and Design Automation and Test in Europe (DATE 2024). Engages in cross-disciplinary projects like improved secure semiconductor evaluation (ISSE) and energy labeling for digital services.
