Dr. Mahesh Tripunitara is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo, serving as Associate Chair for Undergraduate Studies. He holds a PhD (2005) and Master's (1995) in Computer Science from Purdue University, along with a BSc (1993) in Computer Science from Dalhousie University. His research focuses on information security, authorization mechanisms, cryptographic key management, and hardware security, with industry experience at Motorola's R&D labs and Silicon Valley. His work spans theoretical advancements like access control policy analysis and practical applications such as secure payments systems and IoT device reliability. Notable awards include the Best Student Paper at Usenix Security 2013 and Best Paper at ACM SACMAT 2013. He actively serves on program committees for major security conferences including CCS, CODASPY, and SACMAT. Recent publications highlight innovations in cellular security (SUCI-Catchers defense), role-mining optimization, and blockchain smart contract auditing. Teaching includes advanced algorithm design courses (ECE 406/606) and digital computation (BME 121). His research emphasizes balancing security rigor with usability in authorization systems and hardware protection mechanisms.
Timothy Rogers is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University, located in West Lafayette. His research focuses on GPU architecture, parallel processing, and simulation frameworks, with particular emphasis on optimizing hardware acceleration, memory systems, and concurrency management. He holds an office at BHEE 326A and can be reached at timrogers@purdue.edu. His work spans GPU performance modeling, SIMT architecture analysis, and energy-efficient computing. Recent contributions include frameworks like ThreadFuser for MIMD program analysis, CRISP for concurrent rendering, and Simr for data center microservices. He has also contributed to hardware ray tracing units and RISC-V core integration studies. Rogers has been active in conference leadership, serving as General Chair for ISPASS 2024 and securing NSF travel grants for student participation. His research bridges theoretical architecture design with practical implementation, addressing challenges in modern massively parallel systems.
Rachee Singh is an Assistant Professor of Computer Science at Cornell University, leading the sysphotonics research group. She concurrently serves as an Amazon Scholar within the SageMaker Hyperpod teams, specializing in large-scale machine learning infrastructure development for cloud environments. Her research focuses on photonic interconnect systems for server-scale, rack-scale, and long-haul communication networks, targeting performance optimization for distributed machine learning and planet-scale cloud workloads. Key specialties include optical network design, fault-tolerant WAN architectures, and energy-efficient datacenter interconnects, with strong emphasis on practical deployment in real-world systems. Her group bridges theoretical networking principles with applied AI infrastructure challenges. Recent publications demonstrate concentrated innovation in photonic network optimization for ML workloads, particularly in wavelength management, collective communication algorithms, and chip-to-chip photonic fabrics. This work spans optical physics, distributed systems, and machine learning, revealing a trajectory toward sustainable, high-performance AI infrastructure. Scientific recognition includes: Amazon Research Award (2023) Cisco Research Award Dr. Singh actively mentors graduate researchers including Jonathan Aimuyo, Byungsoo Oh, and Arjun Devraj, whose co-authored publications form the core of her group's output. Research funding is secured through competitive grants from the NSF (including a $1M award for chip-to-chip photonic fabrics), SRC/DARPA JUMP 2.0 program, Cisco, and Cornell's Atkinson Center for Sustainability. The sysphotonics group operates as Cornell's hub for photonic network systems research, developing programmable integrated photonics solutions and collaborating with Amazon on SageMaker Hyperpod for next-generation ML infrastructure.
Ludovic Räss is a computational geoscientist at the University of Lausanne and lecturer at ETH Zurich's Glaciology Lab. His research intersects high-performance computing (HPC), geophysics, and applied mathematics, with specialization in GPU-accelerated scientific computing and supercomputing applications. He leads the GPU4GEO initiative developing multi-physics solvers and pioneers differentiable modeling techniques for geophysical simulations using Julia. Research focuses include: Portable HPC software development Ice dynamics and porous media deformation GPU-optimized computational methods Scalable simulation architectures Differentiable programming for geophysics He designed and teaches Solving partial differential equations in parallel on GPUs at ETH Zurich, providing hands-on training in GPU programming and Julia-based scientific computing. Contributes significantly to Julia's open-source ecosystem through JuliaGPU and JuliaParallel projects.
Rabi N. Mahapatra is a Professor in the Department of Computer Science & Engineering at Texas A&M University, within the College of Engineering. His research focuses on embedded systems, reconfigurable architectures, real-time systems, and semantic networks. He holds a Ph.D. in Computer Engineering from the Indian Institute of Technology (1992), an M.S. in Electrical Engineering (Sambalpur University, 1984), and a B.S. in Electronics & Communication (Sambalpur University, 1979). His research interests include Network-on-Chip (NoC), data analytic co-design, IoT protocols, and temperature-aware energy management. His work emphasizes hardware-software co-design for complex systems, with applications in many-core processors, semantic search engines, and real-time embedded systems. Key publications highlight contributions to collaborative filtering on many-core architectures, low-jitter clock distribution circuits, and energy-efficient scheduling. He has been recognized as an IEEE Computer Society Distinguished Visitor (2005–2007) and received the BOYS-CAST Indo-US Young Scientist Award. He leads the Codesign Embedded Systems group at Texas A&M, exploring cutting-edge topics such as photonics NoC, reservoir computing, and IoT security. His research bridges theory and practice, addressing challenges in scalable systems and embedded applications.
Xiaoming Li is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Delaware , focusing on compiler optimization, GPU computing, and hardware-software interaction. His work bridges machine learning with code generation to enhance program efficiency. B.S. and M.E. from Nanjing University (1998, 2001) Ph.D. in Computer Science from University of Illinois at Urbana-Champaign (2006) Research interests include: Compiler optimizations for static and dynamic code transformation Machine learning-driven code generation techniques FFT algorithms for sparse and hybrid systems Non-traditional compilers for SAT solvers and virtual machines GPU acceleration for large-scale computational problems His publications span 15 years , emphasizing: FFT optimization across GPU/CPU architectures Compiler techniques for heterogeneous systems Adaptive scheduling and error resilience Integration of empirical and model-driven approaches Notable awards: NSF CAREER Award (2008) Best Paper Award at ADAPT Workshop (2013) Advising highlights: Current students: Ryan Taylor, Sha Li, Shuo Chen, Yuanfang Chen, Chao Yang, Chaoyu Chen Graduates: Liang Gu (FFT Libraries), Jakob Siegel (GPGPU Frameworks), Murat Bolat (Context-Aware Compilation)
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
Timothy Harris is an Affiliated Lecturer at the University of Cambridge's Department of Computer Science and Technology, where he jointly teaches courses on multicore semantics and programming. Currently, he works at OpenAI, focusing on performance optimization for GPU inference of large language models, including the Azure OpenAI Service. Previously, he held roles at Microsoft, AWS, Oracle Labs, and was a faculty member at the University of Cambridge (2000–2004). His research spans distributed systems, runtime systems, operating systems, and high-performance computing, with an emphasis on scalability and performance. He contributed to projects like the Xen hypervisor and the Barrelfish research OS. Key research interests include distributed training of PyTorch models in the ONNX runtime, large-scale storage performance with Amazon S3, and runtime systems for in-memory graph analytics. His work often bridges 'big data' and high-performance computing techniques. Notable contributions include the book Transactional Memory (2010) and the Barrelfish OS, alongside numerous publications in top-tier conferences like SOSP, ASPLOS, and EuroSys. He has served as PC chair for ISMM 2025, VEE 2017, and EuroSys 2015, reflecting his leadership in the systems research community. His awards include a Best Paper Award at PACT 2010. Beyond academia, Harris is an avid hiker, aiming to complete the UK coastline, and maintains a photography portfolio at tlhphotography.uk .
Mark Batty is a Professor in the School of Computing at the University of Kent, specializing in formal methods for concurrent systems. His work bridges hardware-software interfaces, focusing on memory models for C/C++, OpenCL, and architectures including x86, ARM, POWER, and GPUs. As a member of the Programming Languages and Systems Research Group, he develops mathematical specifications and verification tools for real-world concurrency challenges. His research centers on empirical testing of hardware/compiler behavior, formal modeling of system components, and verification of fine-grained concurrent algorithms. Key contributions address relaxed memory semantics, transactional memory, and compositional reasoning for concurrent data structures. His work combines theoretical rigor with practical tool development to ensure correctness in complex concurrent environments. Analysis of his 2015-2025 publications reveals consistent focus on memory consistency models, formal verification of weak memory concurrency, and compiler optimizations. Dominant themes include C/C++11 standards, GPU concurrency semantics, and mechanized verification techniques. His research demonstrates strong industry relevance through collaborations with hardware vendors and contributions to language standards. Mark Batty has received significant recognition: John C. Reynolds Doctoral Dissertation Award (2015) from ACM SIGPLAN CPHC and BCS Distinguished Dissertation Award (2015) Lloyds Register Foundation and Royal Academy of Engineering Research Fellowship (2016) He actively leads major research initiatives and mentors next-generation researchers: Current Funding: EPSRC Standard Grant 'Verifiably Correct transactional memory' (2018), VeTTS Grant 'Specification and verification of C++ data structure libraries' (2018), EPSRC First Grant 'Compositional, dependency-aware C++ concurrency' (2018) PhD Recruitment: Actively seeking candidates for UKRI-funded studentship in Verified Trustworthy Software Systems Batty drives community engagement through Kent Concurrency Workshop (2016) and South of England Programming Language Seminars, fostering national collaboration in programming languages research. His leadership in organizing Royal Society discussions underscores his influence in trustworthy systems verification.
Trevor Brown is an Associate Professor in the Computer Science department at the University of Waterloo, affiliated with the Cheriton School of Computer Science. He leads the Multicore Lab and specializes in concurrent data structures, non-blocking algorithms, and memory management. His research bridges theory and systems, focusing on practical implementations of lock-free trees, transactional memory, and techniques for non-uniform memory architectures. Education includes a PhD in Computer Science from the University of Toronto and a B.Sc. in Computer Science and Mathematics from York University. Research interests center on concurrent systems, with recent work exploring hardware-accelerated indexing, memory reclamation techniques, and performance anomalies in microbenchmarks. His publications demonstrate consistent innovation in parallel computing, with articles frequently appearing at top conferences like PPoPP, SPAA, and DISC. Sustainable energy research includes optimizing hybrid power systems and battery storage solutions. Awards include multiple best paper/artifact recognitions at SPAA and PPoPP, teaching excellence honors, and nominations for the Governor General’s Gold Medal. Extensive advising includes 13+ graduate students and PDFs, with research grants exceeding $965K from NSERC, Huawei, and CFI. He directs the Multicore Lab, developing open-source tools like SetBench for rigorous performance benchmarking.
Bo Wu is an Associate Professor in the Department of Computer Science at Colorado School of Mines. His research focuses on compilers and programming systems, particularly program optimizations for heterogeneous computing and emerging architectures, with applications in machine learning and graph processing. He joined Mines in 2014 after earning a Ph.D. from The College of William and Mary and earlier degrees from Central South University in China. Education : B.S. in Computational Science and Technology (Central South University, 2005) M.S. in Computer Science (Central South University, 2008) Ph.D. in Computer Science (The College of William and Mary, 2014) Research Interests : Wu's work emphasizes enhancing data locality in heterogeneous systems, GPU scheduling, and optimizing applications for emerging architectures. His contributions include frameworks like GraphZero for efficient graph mining and FLEP for GPU preemption. Awards & Grants : NSF SPX Award (2018) NSF CAREER Award (2018) Supercomputing Best Paper Award (2015) Multiple NSF grants for GPU-related research Advising & Grants : Wu has led several NSF-funded projects and actively participates in conference program committees (e.g., PPoPP, SC, ICS). His research spans compiler optimizations, parallel computing, and high-performance systems. Labs & Teams : While specific labs aren’t named, his work involves collaborations on GPU-based systems, graph processing frameworks, and compiler toolchains.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Daniel J. Sorin is a Professor of Electrical and Computer Engineering at Duke University's Pratt School of Engineering, where he also serves as Associate Chair of Education. He holds joint appointments in both the Electrical and Computer Engineering department and Computer Science department, and is recognized as a Bass Fellow for his contributions to education and research. His research focuses on computer architecture with specific expertise in memory systems, cache coherence protocols, fault tolerance, and verification-aware design. Dr. Sorin's work bridges theoretical computer architecture with practical implementations, often incorporating coding theory to solve architectural challenges. His research group has made significant contributions to automated protocol generation, hardware acceleration, and robot motion planning systems. Dr. Sorin's publications reveal a consistent focus on memory consistency models, cache coherence protocols, and verification techniques. His recent work has expanded into robot motion planning acceleration, FPGA resource management, and novel error correction techniques for emerging memory technologies. The trend shows increasing interdisciplinary work connecting computer architecture with robotics and machine learning applications. Program Chair of HiPEAC 2017 Co-chair of IEEE Micro's Top Picks selection committee (2016) Lois and John L. Imhoff Distinguished Teaching Award (2011) NSF CAREER Award recipient IEEE Micro Top Pick awards (2011, 2015) ACM Senior Member As an advisor, Dr. Sorin has mentored numerous PhD students who have gone on to successful careers at leading technology companies including Google, Microsoft, Oracle, and Nvidia. His research group maintains strong industry connections and has produced influential work in cache coherence protocols, memory systems, and fault-tolerant architectures. He has also authored the widely-used textbook 'A Primer on Memory Consistency and Cache Coherence' (2nd edition). Dr. Sorin leads an active research laboratory focused on next-generation computer architecture challenges, with ongoing projects in hardware acceleration, memory systems, and robot motion planning. His group collaborates with researchers across multiple disciplines including robotics, coding theory, and semiconductor design.
Dr. Yiting Xia is a tenure-track faculty member at the Max Planck Institute for Informatics (MPI-INF), leading the Network and Cloud Systems research group. She previously worked as a research scientist at Facebook and holds a PhD in Computer Science from Rice University (2018) and a B.S. in Telecommunications Engineering from Beijing University of Posts and Telecommunications and Queen Mary University of London (2011). Her research focuses on high-performance and energy-efficient networking for cloud computing, including reconfigurable data center networks, optical communications, and network protocols. Notable contributions include innovations in transport protocols, time synchronization for optical networks, and failure-resilient network design. Education: PhD in Computer Science, Rice University, 2018 M.S. in Computer Science, Rice University, 2014 B.S. in Telecommunications Engineering, BUPT & QMUL, 2011 Research Interests: Data center networking, optical communications, cloud systems, network protocols, distributed systems, and network security. Her work bridges theoretical contributions with practical implementations, addressing challenges in latency-sensitive flows, traffic engineering, and system reliability. Awards include the Ken Kennedy-Cray Fellowship and the N2Women Rising Star Award (2021). She has co-lectured courses on distributed systems and data networks at Saarland University and previously contributed to teaching at Rice University. Key projects include Aurora (for MoE inference optimization), Lighthouse (an open research framework for optical networks), and Occam (a reliable network management system). Grants & Projects: Focus on deployable optical network architectures and resilient backbone management during pandemic-driven traffic shifts. Labs/Teams: Leads the Network and Cloud Systems group at MPI-INF, collaborating with academia and industry on cutting-edge networking solutions.
Dr. Feng Yan is an Associate Professor at the University of Houston's Computer Science Department, leading the Intelligent Data and Systems Lab (IDS Lab). He previously held an Associate Professor position at the University of Nevada, Reno. His research focuses on bridging Big Data, Machine Learning, and Systems, with interdisciplinary applications in wildfire science, materials engineering, and civil infrastructure. He has received prestigious awards such as the NSF CAREER Award and the Regents' Rising Researcher Award. Education: Ph.D. (2016) and M.S. (2011) in Computer Science from College of William and Mary; B.S. (2008) in Computer Science from Northeastern University. Research experience includes roles at Microsoft Research and HP Labs. Research Interests: Large Language Models (LLM), Distributed Deep Learning, AutoML, Serverless Computing, Federated Learning, and AI-driven domain sciences. His work emphasizes real-world impact through collaborations with industry and national labs. Publications: Over 60+ papers in top-tier venues like NeurIPS, ICLR, KDD, AAAI, SOSP, SC, and VLDB. Key contributions include ZeRO++ (collective communication optimization), Gradient Compression techniques, and Federated Learning frameworks like TiFL and HDFL. Awards: NSF EPSCoR Award ($20M), NSF CAREER Award, FAA BAKFAA Grant, and multiple best paper awards (IEEE CLOUD 2018, CLOUD 2019). Active in program committees for HPDC, ICAC, ICPE, and AAAI. Advising: Supervised over 30+ graduate/undergraduate students, with placements at Microsoft Research, IBM, Oak Ridge National Lab, Facebook, and MathWorks. Runs a vibrant lab with a focus on interdisciplinary AI/Systems research.