Daniel J. Sorin

Daniel J. Sorin is a Professor of Electrical and Computer Engineering at Duke University's Pratt School of Engineering, where he also serves as Associate Chair of Education. He holds joint appointments in both the Electrical and Computer Engineering department and Computer Science department, and is recognized as a Bass Fellow for his contributions to education and research.

His research focuses on computer architecture with specific expertise in memory systems, cache coherence protocols, fault tolerance, and verification-aware design. Dr. Sorin's work bridges theoretical computer architecture with practical implementations, often incorporating coding theory to solve architectural challenges. His research group has made significant contributions to automated protocol generation, hardware acceleration, and robot motion planning systems.

Dr. Sorin's publications reveal a consistent focus on memory consistency models, cache coherence protocols, and verification techniques. His recent work has expanded into robot motion planning acceleration, FPGA resource management, and novel error correction techniques for emerging memory technologies. The trend shows increasing interdisciplinary work connecting computer architecture with robotics and machine learning applications.

• Program Chair of HiPEAC 2017
• Co-chair of IEEE Micro's Top Picks selection committee (2016)
• Lois and John L. Imhoff Distinguished Teaching Award (2011)
• NSF CAREER Award recipient
• IEEE Micro Top Pick awards (2011, 2015)
• ACM Senior Member

As an advisor, Dr. Sorin has mentored numerous PhD students who have gone on to successful careers at leading technology companies including Google, Microsoft, Oracle, and Nvidia. His research group maintains strong industry connections and has produced influential work in cache coherence protocols, memory systems, and fault-tolerant architectures. He has also authored the widely-used textbook 'A Primer on Memory Consistency and Cache Coherence' (2nd edition).

Dr. Sorin leads an active research laboratory focused on next-generation computer architecture challenges, with ongoing projects in hardware acceleration, memory systems, and robot motion planning. His group collaborates with researchers across multiple disciplines including robotics, coding theory, and semiconductor design.