جستجوی استاد راهنمای دانشگاهی

Rakesh Kumarمشاهده پروفایل

استاد

• Computer Architecture
• System-Level Design Automation
• Low Power Computing
• +۳ مورد دیگر

Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.

• Computer Vision
• Computer Graphics
• Machine Learning
• +۴ مورد دیگر

Prof. Matthias Nießner is a Professor at the Technical University of Munich , where he leads the Visual Computing Lab . Prior to this, he held a Visiting Assistant Professor position at Stanford University . His work bridges computer vision , graphics , and machine learning , focusing on 3D reconstruction , semantic scene understanding , and AI-driven video synthesis . Prof. Nießner has published over 150 works in top venues like SIGGRAPH , CVPR , and ECCV , with several receiving best paper awards (SIGCHI’14, HPG’15, SPG’18, SIGGRAPH’16 Emerging Tech). His research has garnered international media attention, including features in the New York Times , Wall Street Journal , and MIT Technological Review , as well as TV demonstrations (e.g., Jimmy Kimmel Live for Face2Face technology). Awards : TUM-IAS Rudolph Moessbauer Fellowship (2017–ongoing) Google Faculty Award (2017) Nvidia Professor Partnership Award (2018) ERC Starting Grant (2018, €1.5M) Eurographics Young Researcher Award (2019) Research Trends : 3D Gaussian Splatting for real-time rendering Neural Radiance Fields (NeRF) with mesh supervision Audio-driven facial animation via diffusion models Latent space diffusion for 3D scenes Self-supervised and zero-shot methods for 3D and image analysis As a co-founder and director of Synthesia Inc. , he drives democratization of synthetic media. His YouTube channel has over 5 million views, reflecting his impact beyond academia.

Jian Huangمشاهده پروفایل

دانشیار

• Computer Architecture
• Memory and Storage Systems
• AI Infrastructure
• +۵ مورد دیگر

Jian Huang is an Associate Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC), holding a 100% appointment since August 2024. He is also an affiliated Associate Professor in Computer Science and serves as the Y. T. Lo Faculty Fellow in ECE. Huang leads the Systems Platform Research Group and received his Ph.D. in Computer Science from Georgia Institute of Technology in August 2017, where his dissertation earned the College of Computing Dissertation Award. His research focuses on Computer Architecture, Memory and Storage Systems, AI Infrastructure, Distributed Systems, and Systems Security . Huang has pioneered work in sustainable AI infrastructures, modular data centers, neural processing unit virtualization, and ransomware-aware storage systems. His research has been featured in top-tier conferences including ISCA, MICRO, ASPLOS, OSDI, SOSP, and USENIX ATC, with over 50 publications and multiple patents issued worldwide. Huang's research has significant industry impact, with some work transferred into products and featured in popular media outlets including ACM CACM, TechXplore, and Science Daily. His work on non-volatile memory and storage systems has received extensive coverage, with some projects generating over 50 media reports. Among his notable achievements are the ACM SIGMICRO Early Career Award, NSF CAREER Award, IEEE Micro Top Picks (three times), USENIX Best Paper Award, and the MICRO Best Paper Runner Up in 2024. He has secured over $4.01M in grants ($11.12M with collaborators) from NSF, DARPA, Army Research Office, and industry partners. ACM SIGMICRO Early Career Award NSF CAREER Award IEEE Micro Top Picks (three times) USENIX Best Paper Award MICRO Best Paper Runner Up (2024) Google Faculty Research Award NetApp Faculty Fellowship Award Huang actively contributes to the academic community as program co-chair of NVMW'23 and organizer of HotInfra'23. He currently advises 12 Ph.D. students, 1 master student, and multiple undergraduates. His teaching innovations include developing ECE522: Emerging Memory/Storage System and revising ECE511: Computer Architecture with cutting-edge content.

Gustavo Alonsoمشاهده پروفایل

استاد

• Databases
• Distributed Systems
• Cloud Computing Architecture
• +۴ مورد دیگر

Gustavo Alonso is Full Professor at the Department of Computer Science (D-INFK) of ETH Zurich and Head of the Institute for Computing Platforms . He has been at ETH since 1995, first as a post-doc, then as Assistant Professor from April 1998, and promoted to Full Professor in October 2001. Within the Systems Group he leads the Information and Communication Systems Research Group . Education: 1989 – Telecommunications Engineering (undergraduate), Madrid Technical University (UPM-ETSIT), Spain 1992 – M.S. Computer Science, University of California, Santa Barbara (UCSB) 1994 – Ph.D. Computer Science, University of California, Santa Barbara (UCSB) Research Interests: His work spans databases, distributed systems, cloud-computing architecture, FPGAs, hardware acceleration for data science, parallel and reconfigurable computing . The group investigates how modern heterogeneous hardware—from GPUs to SmartNICs—can be integrated into data-processing systems to achieve orders-of-magnitude performance gains, energy savings, and new functionality such as in-network computation and serverless acceleration. Scientific Awards & Honors: Fellow of the ACM (Association for Computing Machinery) Fellow of the IEEE (Institute of Electrical and Electronics Engineers) Distinguished Alumnus, Department of Computer Science, UC Santa Barbara Four Test-of-Time / Most Influential Paper Awards across databases, programming languages, cloud computing, and software engineering Labs & Projects: He directs the Information and Communication Systems Research Group within the Systems Group ( systems.ethz.ch ). The lab develops open-source platforms such as Coyote v2 for FPGA abstractions, Shuhai for HBM benchmarking, and MicroRec for micro-second recommendation serving, while collaborating with industry on SmartNICs, serverless analytics, and cloud-scale data analytics.

Jakob Foersterمشاهده پروفایل

دانشیار

• Multi-Agent Learning
• Deep Reinforcement Learning
• Human-AI Coordination
• +۵ مورد دیگر

Jakob Foerster is an Associate Professor at the University of Oxford's Department of Engineering Science and a Supernumerary Fellow at St Anne's College. He leads the FLAIR lab, focusing on multi-agent reinforcement learning (MARL), human-AI coordination, and AI foundational research. Previously, he was a Research Scientist at Facebook AI Research (FAIR) and holds a DPhil from Oxford. His work has been cited over 5,000 times and includes seminal contributions like QMIX and the Hanabi Challenge. Research interests span compute-efficient scaling of AI, MARL applications in finance and bio, and ethical AI. He actively collaborates across academia and industry, co-organizing workshops like NeurIPS' Emergent Communication. His lab emphasizes open-ended RL, environment design, and scalable algorithms. Notable awards include the CIFAR AI Chair (2019) and NeurIPS Best Paper Runner-Up (2018). Current efforts include FLAIR's research on zero-shot coordination and the JaxMARL framework. He advises students in Oxford's Engineering DPhil and AIMS CDT programs.

• Computer Engineering
• Circuit Design
• Fault Tolerance
• +۶ مورد دیگر

Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.

• Computer Architecture
• Datacenter Systems
• Cloud-Native Server Architecture
• +۷ مورد دیگر

Babak Falsafi is a Full Professor at the School of Computer and Communication Sciences (IC) at EPFL, leading the Parallel Systems Architecture Laboratory (PARSA). He is a renowned expert in computer architecture, datacenter systems, and cloud-native server design. His research focuses on post-Moore era computing, emphasizing heterogeneous architectures, energy efficiency, and scalable IT infrastructure. Falsafi is the founder of EcoCloud, an EC-sponsored industrial-academic consortium investigating sustainable information technology. He holds ACM and IEEE fellowships, a Sloan Research Fellowship, and has contributed to major projects like Optimus Prime (data transformation acceleration), AstriFlash (flash-based online service systems), and Midgard (virtual memory re-design). His work spans hardware-software co-design, memory systems, and security. Falsafi advises numerous PhD students and collaborates with industry partners such as Google and Cavium. Key achievements include pioneering scalable multiprocessor architectures, snoop filters in IBM BlueGene, and spatial memory streaming in ARM cores. His lab develops open-source tools like QFlex for server simulation. He frequently presents at top conferences (HPCA, ISCA, MICRO) and chairs workshops on post-Moore infrastructure. Teaching roles include leading courses in computer architecture and parallel systems across multiple EPFL departments (SIN, EDIC, SSC, SMA). His work addresses datacenter challenges like the 'data tax' and mitigating latency through specialized accelerators.

Bernhard J. Bergerمشاهده پروفایل

مدرس

• Software Security
• Static Code Analysis
• Machine Learning
• +۴ مورد دیگر

Bernhard J. Berger is a Lecturer in the Department of Computer Engineering at the Institute of Embedded Systems, Hamburg University of Technology (TUHH). His research focuses on software security, static code analysis, machine learning, optimization, and research data management. He has held significant roles such as Program Committee member for ICPC 2025 and MSR 2025, and has received awards including the Best Reviewer Award (ICPC 2023) and Best Engineering Paper Award (SCAM 2019). His work spans interdisciplinary applications including maritime systems security, GPU-accelerated AI, and evolutionary algorithms. Recent studies emphasize AI-driven security tools (e.g., ML-SAST) and domain-specific language approaches to optimization (EvoAl). He has contributed to over 30 peer-reviewed publications, with notable work in IEEE Transactions on Software Engineering and Science of Computer Programming. Berger collaborates closely with industry through DAAD review committees and serves on artifact evaluation boards for ISSTA and ARES conferences. Education: Doctoral Thesis (2022), Diploma in Computer Science (2007) Key Projects: ArchSec tool suite, Threat Modeling Frameworks, Bauhaus static analysis methodology Lab Affiliation: Embedded Systems Design Group His advisory roles include Deputy of TUHH's Election Verification Committee and Session Chair at IEEE Congress on Evolutionary Computation 2023. Current research trends integrate machine learning with static analysis for automated vulnerability detection, while also exploring explainable AI techniques for neural network optimization.

• Computer Networks
• Network Security
• Machine Learning in Networking
• +۳ مورد دیگر

Mariano Scazzariello is a Lecturer at KTH Royal Institute of Technology, Sweden, affiliated with the School of Electrical Engineering and Computer Science and the Department of Network and Systems Engineering. He teaches the course 'Network Systems with Edge or Cloud Datacenters (IK2227)'. His research focuses on advanced networking topics including machine learning in networks, high-speed packet processing, network emulation, and software-defined networking innovations. His work spans contributions to network emulation tools like Kathará and Megalos, stateful packet processing at terabit scales, and leveraging large language models (LLMs) for network configuration and vulnerability detection. Recent research emphasizes low-latency protocols (e.g., SRv6/DetNet integration) and GPU-centric networking on commodity hardware. Mariano’s publications (2020–2025) highlight expertise in network function virtualization, ASIC-based switching, and optimizing network configurations through AI-driven approaches. He has pioneered frameworks for evaluating routing protocols and virtualizing large network scenarios at scale.

Yang Zhouمشاهده پروفایل

دانشیار

• Big Data Algorithms
• Data Mining
• Machine Learning
• +۵ مورد دیگر

Yang Zhou is an Associate Professor in the Department of Computer Science and Software Engineering at Auburn University, part of the Samuel Ginn College of Engineering. His research focuses on big data algorithms, machine learning, data mining, and distributed computing. He has contributed to advancements in federated learning frameworks, graph mining tools, and spatial machine learning for environmental applications like flood mapping. Education includes a Ph.D. in Computer Science from Georgia Tech (2021), M.E. in Computer Application Technology from Chongqing University (2016), and B.E. in Engineering from Jiangnan University (2014). His work emphasizes scalable algorithms for large-scale systems, with tools like DirDense for dense subgraph mining and FedASMU for federated learning optimization. Recent publications explore adversarial robustness, blockchain strategies in IoT, and curriculum-based learning for large language models. He advises on interdisciplinary projects at the intersection of AI and environmental science.

Geng Yuanمشاهده پروفایل

استادیار

• Artificial Intelligence Systems
• Energy-Efficient Deep Learning
• Model Compression
• +۵ مورد دیگر

Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.

James C. Hoeمشاهده پروفایل

استاد

• Computer Architecture
• Reconfigurable Computing
• High-Level Hardware Design and Synthesis
• +۴ مورد دیگر

James C. Hoe is Professor of Electrical and Computer Engineering at Carnegie Mellon University (College of Engineering). He is on sabbatical at MangoBoost and directs research in computer architecture, reconfigurable computing, and high-level hardware design. Education Ph.D., Electrical Engineering and Computer Science, MIT (2000) M.S., Electrical Engineering and Computer Science, MIT (1994) B.S., Electrical Engineering and Computer Science, UC Berkeley (1992) Research Interests Professor Hoe’s work spans computer architecture , reconfigurable computing , FPGA architectures , and high-level hardware synthesis . His group created the CoRAM abstraction for virtualized FPGA computing and leads efforts in power-efficient accelerators, in-network computing, and security-oriented FPGA systems. Scientific Awards IEEE Fellow (2013) Intel Outstanding Researcher Award (2021) Research Funding & Projects Intel / VMware Crossroads 3D-FPGA Academic Research Center – co-leading exploration of FPGA roles in future datacenters. DARPA BRASS program ($2.7 M, 4 years) – ensuring long-lived software systems remain robust to resource changes. Pigasus open-source IDS – world’s fastest FPGA-accelerated intrusion-detection system (100 Gb/s on one server). Labs & Teams He heads activities within the Computer Architecture Lab at Carnegie Mellon (CALCM) , supervising graduate researchers on CoRAM++, SPIRAL autotuning, and FPGA overlays for stream processing.

Scott Hauckمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Architecture
• Quantum Computing Control
• +۵ مورد دیگر

Affiliation & Education Scott Hauck is a Professor at the University of Washington's Department of Electrical & Computer Engineering and an Adjunct Professor in Computer Science & Engineering. He leads the Adaptive Computing Machines and Emulators (ACME) Lab . He earned his BS in EECS from UC Berkeley (1990), and MS/PhD in CSE from the University of Washington (1992/1995). Research Focus Dr. Hauck specializes in FPGA-based reconfigurable computing with applications in: Quantum Computing: FPGA controllers for trapped-ion quantum systems enabling precise laser control and quantum state readout. Medical Imaging: Portable radiation sensors for personalized cancer therapy and PET scanner enhancements. High-Energy Physics: FPGA readout systems for ATLAS pixel detectors at CERN's Large Hadron Collider. AI Acceleration: Real-time machine learning inference for scientific applications via projects like hls4ml. His work bridges hardware innovation with computational physics, emphasizing real-time processing and low-latency systems. Publication Trends Recent research focuses on FPGA-accelerated machine learning for particle physics (e.g., transformer networks for LHC trigger systems) and quantum computing instrumentation. Earlier work established foundations in reconfigurable computing architectures and medical imaging electronics. Awards & Recognition Distinguished Teaching Award, University of Washington (2010) Advising & Funding Leads the ACME Lab with extensive funding from NSF, DARPA, NIH, DOE, and industry partners including Intel, Xilinx, and Microsoft. Mentored over 30 MS/PhD students in VLSI, reconfigurable systems, and scientific computing. Collaborations & Labs Directs the ACME Lab (EE1-307), collaborating with UW Radiology (Prof. Robert Miyaoka), UW Physics (Prof. Shih-Chieh Hsu), and Drexel University (Prof. Josh Agar). Projects include quantum control systems, LHC readout electronics, and medical sensor networks.

Joy Arulrajمشاهده پروفایل

دانشیار

• Data Systems
• Machine Learning
• Database Systems
• +۲ مورد دیگر

Joy Arulraj is an Associate Professor in the School of Computer Science within the College of Computing at Georgia Institute of Technology. His research focuses on data systems, machine learning, and database systems, with a particular emphasis on video analytics and adaptive query processing. He leads the Data Systems and Analytics Group and is developing the EVA AI-Relational Data System. Dr. Arulraj's research interests span data systems, machine learning, database systems, video analytics, and adaptive query processing. His work centers on developing systems that efficiently process complex queries, particularly for video analytics and machine learning workloads. He has made significant contributions to GPU database systems, non-volatile memory database management, and adaptive query processing techniques. His research often bridges the gap between theoretical database principles and practical implementations for modern hardware architectures. His recent publications show a strong trend toward video analytics systems, adaptive query processing for machine learning workloads, and GPU-accelerated database systems. The EVA system represents a major focus of his recent work, providing end-to-end exploratory video analytics capabilities. His research also addresses fundamental database concepts like buffer management, query optimization, and storage management, adapting these principles for modern hardware and application requirements. Dr. Arulraj has advised numerous graduate students including Pramod Chunduri, Gaurav Tarkok Kakkar, Jiashen Cao, and Sayan Sinha. His graduated students have gone on to work at companies like ServiceNow, Meta Research, and the Korean Army. He actively teaches database system courses at Georgia Tech, including Database System Implementation (CS 4420/6422) and Advanced Database System Implementation (CS 4423/6423), where students build database systems from scratch using C++ and the BuzzDB framework. He maintains an active research program with consistent publication output across top database and systems conferences. His work spans from theoretical database principles to practical system implementations, with a recent emphasis on video analytics, machine learning integration with database systems, and leveraging modern hardware like GPUs and non-volatile memory for database applications.

Zhonghai Luمشاهده پروفایل

استاد

• Computer Architecture
• Embedded Systems
• Network-on-Chip (NoC)
• +۷ مورد دیگر

Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence