Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.
Jeffrey Krolik is a Professor of Electrical and Computer Engineering at Duke University's Pratt School of Engineering. He holds a Ph.D. in Electrical Engineering from the University of Toronto (1987) and previously served as an Assistant Professor at Concordia University and Assistant Research Scientist at Scripps Institution of Oceanography. Ph.D. University of Toronto (1987) M.A. University of Toronto (1983) B.A. University of Toronto (1980) His research focuses on physics-based and statistical signal processing with applications in radar, sonar, microwave remote sensing, and medical imaging. Key projects include adaptive beamforming for ocean acoustic waveguides, aircraft height finding via HF radar, and motion-robust fMRI algorithms. Recent publications cover multipath mitigation in sonar arrays, vibrational radar backscatter communication, and CNN implementations for radar signal processing. His work spans underwater acoustics, urban radar tracking, and distributed sensor networks. He teaches advanced courses in sensor array signal processing, digital audio systems, and radar applications. His research has been supported through collaborations with institutions like Scripps and consulting roles with ONR, DARPA, and Air Force Rome Laboratories. Key contributions include waveguide invariant processing, matched-field beamforming, and novel approaches to radar clutter suppression in urban and maritime environments. His work integrates statistical signal processing with physical propagation models across diverse domains.
Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.
Russell Tessier is a Professor and Department Head of Electrical and Computer Engineering at the University of Massachusetts Amherst, affiliated with the Manning College of Information and Computer Sciences. His research focuses on reconfigurable computing, FPGA architectures, and hardware security, with notable contributions in CAD algorithms for FPGAs, embedded systems, and multi-tenant FPGA vulnerability analysis. Education: B.S.C.S.E., Rensselaer Polytechnic Institute (1989) M.S. and Ph.D., Massachusetts Institute of Technology (1992 and 1999) Research Interests: Dr. Tessier's work spans FPGA security (e.g., side-channel attacks, power distribution vulnerabilities), reconfigurable cloud computing, and hardware acceleration for applications like SAR imaging and machine learning. His lab, the Reconfigurable Computing Group, develops open-source FPGA cores (e.g., FlexGrip GPGPU, DE4 NetFPGA) and explores cutting-edge security countermeasures. Awards and Honors: Chancellor's Leadership Fellow (2015-2016) NSF Information Technology Research Grant Lilly Teaching Fellow (2002-2003) Multiple College of Engineering Excellence Awards Grants and Projects: Active funding includes NSF SaTC grants on reconfigurable cloud security and NASA support for snowpack measurement systems. His research also addresses FPGA-based solutions for cybersecurity, such as intrusion detection and power-side channel mitigation. Labs and Teams: Leads the UMass Reconfigurable Computing Group, which collaborates on open-source FPGA tools, security frameworks, and embedded system designs. The group maintains platforms like the DE4 NetFPGA and FlexGrip architecture.
Brendan Dolan-Gavitt is an Associate Professor in the Computer Science and Engineering Department at NYU Tandon School of Engineering and part of the NYU Center for Cybersecurity (CCS). He holds a Ph.D. in Computer Science from Georgia Tech (2014) and a BA in Math and Computer Science from Wesleyan University (2006). His research spans cybersecurity, program analysis, virtualization security, memory forensics, and embedded/cyber-physical systems, focusing on automating the understanding of large software systems to develop novel defenses. Research interests include developing techniques for static and dynamic analyses of real-world software to reveal hidden design assumptions. His work has been presented at top security conferences like USENIX Security, ACM CCS, and IEEE Security & Privacy. He led the development of the open-source PANDA platform for dynamic analysis. His publications primarily focus on AI-driven security solutions, vulnerability discovery, and automated testing tools. Recent work explores LLMs in offensive security, fuzzing enhancements, and secure code generation, emphasizing practical applications in cybersecurity. Scientific Awards: NSF CAREER Award for improving software vulnerability testing and education He leads the OSIRIS Lab, a student-run cybersecurity group, and collaborates on interdisciplinary projects addressing emerging security challenges through grants and industry partnerships.
Dr. Gushu Li is an Assistant Professor at the University of Pennsylvania's School of Engineering and Applied Science, affiliated with the Computer and Information Science Department (primary) and Electrical and Systems Engineering Department (secondary). He leads the Penn Quantum System Lab, focusing on quantum computing software-hardware co-design. University: University of Pennsylvania School: School of Engineering and Applied Science Department: Computer and Information Science Academic Rank: Assistant Professor His research spans quantum compilers, programming languages, algorithm optimization, computer architecture, and electronic design automation. He develops techniques for quantum error correction verification, qubit mapping, and hybrid quantum-classical systems, with work integrated into IBM's Qiskit and Quantinuum's TKET frameworks. The 15 most recent publications highlight advancements in quantum simulation , bosonic quantum computing , fermion-to-qubit mapping , and NISQ-era architectures . Key methodologies include symbolic Hamiltonian compilation, adaptive tree structures, and runtime assertions for quantum program testing. 2024: NSF CAREER Award, NVIDIA Academic Grant Program Award, Intel Rising Star Faculty Award 2021-2022: QISE-NET Triplet Fellow, ACM SIGPLAN Distinguished Paper Award, multiple travel grants 2015-2017: Fellowships from UCSB, UChicago, and DAC Dr. Li advises four PhD students and actively recruits candidates with FPGA/digital design skills for 2025. His lab emphasizes interdisciplinary backgrounds to tackle quantum system challenges.
Nicola Nicolici is a Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on methods and algorithms for the design of digital integrated circuits and systems, with significant contributions in manufacturing test, post-silicon validation and debug. His work has expanded to include embedded systems, low-energy computing, and custom hardware-accelerated computing systems. Professor Nicolici's research interests span multiple areas of digital system design and validation. His early work focused on manufacturing test methodologies and power-aware testing strategies for integrated circuits. More recently, he has made significant contributions to post-silicon validation techniques, including constrained-random stimuli generation, trace signal selection, and bit-flip detection. His research has evolved to address emerging challenges in embedded computing systems, low-energy design, and specialized hardware acceleration for various applications including deep neural networks and signal processing. His recent publications reveal a strong trend toward hardware acceleration for specialized computing tasks. The research spans matrix multiplication algorithms (Strassen and Karatsuba), memory system optimization (DDR5 calibration), FPGA-based radar processing, and neural network acceleration. His work consistently bridges theoretical algorithm development with practical hardware implementation considerations, particularly focusing on precision analysis, fault tolerance, and energy efficiency. The research demonstrates a clear progression from traditional digital circuit testing to more complex system-level validation and acceleration techniques. Professor Nicolici has been actively involved in teaching courses related to system-on-chip design and test, digital systems, and embedded systems. His teaching portfolio includes advanced courses such as System-on-Chip (SOC) Design and Test and Digital Systems Design , reflecting his expertise in the field. While specific grant information isn't detailed in the provided text, his extensive publication record suggests ongoing research funding support. His research has contributed significantly to the fields of digital circuit testing, post-silicon validation, and hardware acceleration. The work has practical applications in semiconductor manufacturing, embedded systems design, and specialized computing architectures. His recent focus on neural network acceleration and memory system optimization reflects the evolving landscape of computer architecture research.
David Wentzlaff is a Professor of Electrical and Computer Engineering at Princeton University, with associated faculty roles in Computer Science and the High Meadows Environmental Institute (HMEI). He leads research in computing architecture, green computing, and sustainable system design. As Director of Undergraduate Studies, he shapes educational programs in his field. Education: Ph.D., Electrical Engineering, MIT (2012) M.S., Electrical Engineering and Computer Science, MIT (2002) B.S., Electrical Engineering, University of Illinois at Urbana-Champaign (2000) Research Focus: Future Computing Systems: Designing manycore architectures, cloud computing infrastructure, and chiplet-based systems for exascale computing. Sustainability: Developing energy-efficient hardware, recyclable computing systems, and eco-friendly decommissioning strategies. Hardware-Software Co-Design: Exploring FPGA integration, in-memory computing, and parallel processing frameworks. Advising & Grants: Advises 8 current graduate students, focusing on topics like chiplet design, neural acceleration, and sustainable computing. Recipient of NSF grants for projects like OpenPiton (open-source manycore research platform) and CAREER awards for energy-efficient architectures. Labs & Collaborations: Leads the Wentzlaff Research Group at Princeton. Develops open-source frameworks like PRGA (FPGA prototyping) and OpenPiton (manycore processor).
John Wawrzynek is a Professor of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He is affiliated with the Department of Electrical Engineering and Computer Sciences in the College of Engineering and serves as Co-Director of the Berkeley Wireless Research Center and Co-PI of the CONIX Research Center, one of the six centers in the Joint University Microelectronics Program sponsored by DARPA. Dr. Wawrzynek received his B.S. in Electrical Engineering from SUNY, Buffalo (1977), M.S. in EE from the University of Illinois, Urbana/Champaign (1979), and Ph.D. in Computer Science from Caltech (1987). Before joining the Berkeley faculty in 1988, he worked as a consultant at Schlumberger Palo Alto Research. His research focuses on Computer Architecture, Reconfigurable Computing, Wireless Systems, and Integrated Circuit and System Design . His work spans both theoretical foundations and practical implementations, with particular emphasis on FPGA-based computing systems, reconfigurable architectures, and wireless communication systems. His research group has made significant contributions to the field of reconfigurable computing, including the development of the Garp architecture and various tools for reconfigurable computing systems. Analysis of his recent publications (2022-2025) reveals continued focus on reconfigurable computing, FPGA design, wireless networking, and formal methods for hardware verification. His work shows an evolution from traditional computer architecture towards specialized hardware acceleration, machine learning for EDA, and wireless systems research, with particular emphasis on SAT sampling, differentiable computing, and efficient FPGA implementation of neural networks. DAC's Most Influential Paper Award (2025) NSF Presidential Young Investigator (PYI) (1989) Charles Lee Powell Fellowship (1985) NASA Certificate of Recognition (1983) Rensselaer Engineering and Science Medal (1975) Professor Wawrzynek has advised numerous graduate students throughout his career, many of whom have gone on to prominent positions in both industry and academia including Google, Xilinx, and MIT Lincoln Laboratory. His research has been supported by various grants from NSF, DARPA, and industry partners. He leads the Berkeley Wireless Research Center, which focuses on next-generation wireless communication systems and technologies, and is actively involved in the CONIX Research Center which explores connected intelligence at the network's edge.
Itsuro Morita is Professor in the School of Fundamental Science and Engineering, Faculty of Science and Engineering, Waseda University, Tokyo. Before joining Waseda in 2022 he spent 23 years at KDDI R&D Laboratories, advancing from researcher to executive research fellow, and has been a visiting researcher at Stanford University. He is an IEEE Fellow and IEICE Fellow recognized for pioneering large-capacity, long-haul optical transmission systems. Education: 2004 – 2005 Tokyo Institute of Technology, Graduate School of Science & Engineering, Department of Electrical and Electronic Engineering (Doctoral coursework) 1990 – 1992 Tokyo Institute of Technology, Graduate School of Science & Engineering, Department of Physical Electronics (M.E.) 1986 – 1990 Tokyo Institute of Technology, School of Engineering (B.E.) Research Interests: Morita’s work sits at the intersection of optical fiber communication and software-defined networking. He explores ultra-high-capacity transmission via space-division multiplexing (multi-core/few-mode fibers), real-time MIMO digital signal processing for modal crosstalk mitigation, and SDN/NFV orchestration of disaggregated optical networks. Additional interests include quality-of-transmission estimation using machine learning, telemetry-enabled control planes (gRPC/gNMI), and metro-embedded edge/cloud architectures for IoT services. Publication Trends: Recent articles emphasize two converging themes: (i) petabit-per-second SDM/WDM experiments using novel fiber geometries and real-time DSP, and (ii) cloud-native SDN control frameworks that integrate machine-learning-based QoT prediction, YANG/NETCONF modeling, and open APIs (TAPI/OpenConfig) for multi-domain, partially disaggregated networks. These works collectively push both the physical capacity frontier and the agility of next-generation optical infrastructure. Scientific Awards: C&C Prize 2024 (NEC C&C Foundation) – contributions to WDM optical submarine cable systems IEICE Achievement Award 2021 – pioneering research on 10-Pbit/s ultra-large-capacity SDM transmission Telecom System Technology Award 2021 – 10.16-Pbit/s dense SDM/WDM transmission record IEEE Fellow (2021) – contributions to large-capacity high-speed transmission systems IEICE Fellow (2020) – research on trans-oceanic high-speed optical signal transmission Ichimura Industrial Award – Contribution Prize 2018 – development of terabit-class submarine cable systems Maejima Hisoka Award 2012 – proposal and demonstration of distributed-control soliton communication Minister of Economy, Trade and Industry Award for Advanced Technology 2006 – 160 Gbit/s ultra-high-speed optical transmission technology Advising & Grants: At Waseda University Morita advises graduate students on experimental photonic networking and leads externally funded projects on petabit SDM transmission and SDN orchestration. While specific grant numbers are not disclosed, his continuous industry-university collaborative testbeds (with KDDI, CTTC, and others) indicate substantial competitive funding. Labs & Teams: He heads the Optical Space-Division-Multiplexing Laboratory at Waseda, maintaining joint experimental facilities with KDDI Research and international partners (e.g., CTTC, Spain). The group operates real-time coherent MIMO testbeds, multi-domain SDN controllers, and fiber-level SDM prototypes capable of petabit-per-second demonstrations.
Chester Rebeiro is an Associate Professor at the Department of Computer Science and Engineering within the Indian Institute of Technology Madras . His work spans hardware and software security with a focus on cryptographic implementations and microarchitectural vulnerabilities. Research interests include hardware security, applied cryptography, side channel analysis, and operating system security. He develops frameworks for automatic vulnerability detection and mitigation in cryptographic systems. Editorial Board: Associate Editor at Journal of Hardware and Systems Security (Springer, 2021-2024) Conference Leadership: General Co-Chair for SPACE 2024, Program Co-Chair for ATS 2024, and Program Co-Chair for INDOCRYPT 2023 Professional Activities: Organizer of e-CTF Embedded Capture The Flag and contributor to cybersecurity workshops across India and abroad Scientific contributions highlight two major awards: a Distinguished Paper Award at USENIX Security 2024 and a Best Paper Award at IEEE HOST 2020. His research focuses on practical security solutions for processors and cryptographic systems. Advising includes mentoring 11 PhD students and 7 MS by Research candidates, with notable co-guided projects in fault attack detection and side-channel mitigation. He actively contributes to educational initiatives through courses on Secure Processor Microarchitecture and Operating Systems.
Prashanth Krishnamurthy is a Research Scientist in the Department of Electrical and Computer Engineering at New York University Tandon School of Engineering. His research focuses on robotics, control systems, and cybersecurity, particularly in cyber-physical systems such as power grids and embedded devices. He holds a Ph.D. in Electrical Engineering from NYU. Key research areas include hardware security (e.g., detecting Trojans in chips), anomaly detection in critical infrastructure, and resilient control strategies for robotic systems. He has led or contributed to projects funded by the U.S. Department of Energy (DOE), Office of Naval Research (ONR), and others, including the Tracking Real-time Anomalies in Power Systems (TRAPS) initiative and hardware Trojan detection using short-term aging phenomena. Education: Ph.D., Electrical Engineering, NYU His work bridges theoretical advancements and practical implementations, such as developing FPGA-based testbeds for hardware security validation and creating AI-driven cybersecurity tools like the CRAKEN LLM agent. Collaborators include institutions like SRI International, Karlsruhe Institute of Technology, and the NYU Center for Cybersecurity. Grants include a $1.94M DOE grant for TRAPS and a $359K DURIP grant for hardware Trojan detection. His technical contributions span control systems, anomaly detection algorithms, and cybersecurity frameworks for embedded systems. He is actively involved in advancing secure cyber-physical systems through innovations in real-time monitoring, robust control mechanisms, and AI-augmented security solutions.
Lisa Wills serves as Assistant Professor of Computer Science at Duke University's Trinity College of Arts & Sciences and holds a joint appointment in Electrical and Computer Engineering at the Pratt School of Engineering since 2019. Her research bridges computer architecture and domain-specific applications, with a focus on hardware acceleration for computationally intensive fields. Dr. Wills earned her Ph.D. from Columbia University in 2014. Her academic journey reflects a deep commitment to advancing hardware-software co-design methodologies for real-world computational challenges. Her research centers on developing efficient hardware accelerators for big data analytics, particularly in genomics, graph processing, and database systems. She pioneers frameworks that simplify accelerator deployment while tackling critical bottlenecks in genomic data analysis, protein structure prediction, and privacy-preserving computing. Current work focuses on hardware-aware machine learning systems and energy-efficient architectures for emerging AI applications. Analysis of her publication record reveals a clear trajectory: from foundational work in database processing units (2014-2016) to specialized genomic accelerators (2019-2021), then evolving toward ML-enhanced design automation (2022-2023) and cutting-edge architectural abstractions (2024-2025). Her research consistently targets the intersection of hardware efficiency and domain-specific computational demands, with increasing emphasis on AI/ML workloads. Google ML and Systems Junior Faculty Award (2025) Dr. Wills actively mentors doctoral students including Chris Kjellqvist (lead architect of Beethoven accelerator framework), Mason Ma (PyTFHE FHE framework), and Mansi Choudhary (COCOSSim accelerator simulator). Her research is supported by significant grants including the NSF AI Institute: Athena ($20M, 2021-2027), Meta-funded ProSE accelerator project (2023-2026), and NSF CAREER award (2021-2026), totaling over $25M in active funding. She directs the APEX Lab (Application-driven Programmable Efficient Accelerated Systems), which develops open-source frameworks like Beethoven for FPGA/ASIC accelerator deployment and focuses on lowering barriers for non-hardware researchers to leverage custom acceleration in genomics, AI, and big data applications.
David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.
Lisa Wu Wills is an Assistant Professor in the Department of Computer Science and Electrical and Computer Engineering at Duke University, leading the APEX Lab (Application-driven Programmable Efficient Accelerated Systems Lab). Her research focuses on hardware acceleration for big data analytics in genomics, graphs, and databases to advance healthcare and natural sciences. Education: Ph.D. in Computer Science, Columbia University, 2014 Research Interests: Dr. Wills pioneers computer architecture and hardware-software co-design to create efficient accelerators for emerging applications. Her work targets genomics , graph analytics , and database systems , emphasizing simplified hardware deployment and energy efficiency for scientific breakthroughs in healthcare and AI. Publication Trends: Her 2022-2025 publications reveal a strong focus on open-source frameworks (Beethoven, PyTFHE) for accelerator development, hardware acceleration in privacy-preserving computing, and optimization for large language models. Key themes include transfer learning for EDA, domain-specific architectures for genomics, and energy-efficient image processing. Scientific Awards: Google ML and Systems Junior Faculty Award (2025) Advising and Grants: Dr. Wills mentors three PhD students: Chris Kjellqvist (Beethoven framework architect), Mason Ma (PyTFHE lead for FHE applications), and Mansi Choudhary (COCOSSim simulator creator). Her 2025 Google award funds research on accelerating vector databases and retrieval-augmented generation for LLMs. Labs and Teams: She directs the APEX Lab at Duke, developing tools like Beethoven (open-source accelerator composer) and PyTFHE for hardware-software integration, enabling domain scientists to leverage custom acceleration with minimal hardware expertise.
