جست‌وجوی استاد و پژوهشگر

Sergei Savitskyمشاهده پروفایل

استاد

• Reconfigurable Computing
• Digital Signal Processing
• Hardware Architectures
• +۳ مورد دیگر

Sergei Savitsky is a Professor at Wedel University of Applied Sciences, where he serves as Head of the Bachelor of Computer Science program and Senate Chairman. He has been a university lecturer at the institution since October 2008, following professional experience at NXP Semiconductors (2006-2008) and Philips Research Europe (2001-2006). His educational background includes: Doctorate in Engineering (Dr.-Ing.) from Technical University of Dresden (2002) with distinction "summa cum laude" Habilitation (Dr.-Ing. habil.) from Technical University of Dresden (2024) with teaching authorization in "Technical Computer Science" Diplom-Informatiker (equivalent to MSc) in Computer Science from Technical University of Dresden (1998) Savitsky's research focuses on reconfigurable computing systems , with particular expertise in FPGA design, hardware acceleration, and error correction coding. His work bridges theoretical computer science with practical hardware implementation, resulting in numerous patents and publications in top venues. He has made significant contributions to the development of adaptive hardware architectures for forward error correction, which are critical for modern communication and storage systems. His recent publications demonstrate a strong trajectory in optimizing hardware design processes, with particular focus on applying machine learning techniques like self-organizing maps and gradient descent algorithms to improve FPGA placement efficiency. His research spans both theoretical foundations and practical applications, with patents filed in collaboration with industry partners like NXP Semiconductors and ST-Ericsson. Among his recognitions is the Best Paper Award at CENICS 2019 for his work on accelerating FPGA placement algorithms. As an educator, Savitsky teaches courses related to digital system design, including "Computer-aided design of digital systems," where he emphasizes algorithmic aspects of Electronic Design Automation beyond basic digital technology concepts.

Chang Y Chooمشاهده پروفایل

استاد

• Computer Vision
• Digital Signal Processing
• FPGA Design
• +۷ مورد دیگر

Dr. Chang Y Choo is a Professor of Electrical Engineering at San José State University, where he also serves as Director of the AI/ML FPGA/DSP Systems Laboratory. His academic career spans over three decades, with previous positions at Worcester Polytechnic Institute and industry experience at Altera Corp. (now Intel). Dr. Choo maintains an active research program focusing on hardware acceleration for AI and signal processing applications, with particular emphasis on FPGA-based implementations for real-world systems. Dr. Choo's educational background includes: Ph.D. in Computer and Systems Engineering, Rensselaer Polytechnic Institute (1986) M.S. in Operations Research and Statistics, Rensselaer Polytechnic Institute (1982) B.S./M.S. in Engineering, Seoul National University, Korea Dr. Choo's research interests center on the intersection of hardware design and artificial intelligence. His work focuses on implementing computer vision, deep learning, and digital signal processing algorithms on specialized hardware platforms including FPGAs, GPUs, and custom ASICs. Current projects include developing real-time illumination/view-independent object recognition systems for autonomous vehicles, wideband acoustic echo cancellation for wearable technology, and FPGA-based accelerators for medical imaging applications. His research bridges theoretical algorithm development with practical hardware implementation constraints. Analysis of Dr. Choo's recent publications reveals a clear trajectory toward increasingly sophisticated hardware-accelerated AI systems. His work has evolved from foundational research in digital signal processing and image compression to cutting-edge applications of deep learning on specialized hardware. Recent publications demonstrate expertise in implementing CNN architectures on FPGAs, developing metabolic syndrome prediction models, and creating food object detection systems using transformer models. This progression reflects the broader field's shift toward hardware-aware AI development. Dr. Choo's significant scientific contributions include multiple patents that have advanced the state of the art in several domains: U.S. Patent No. 9,025,763 (2015): 'Apparatus and Method for cancelling wideband acoustic echo' U.S. Patent Nos. 7,058,675 (2006) and 7,124,161 (2006): 'Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices' U.S. Patent Nos. 5,943,096 (1999) and 6,621,864 (2003): 'Motion vector based frame insertion process' U.S. Patent Nos. 5,832,131 (1998) and 5,991,455 (1999): 'Hashing-based vector quantization' U.S. Patent No. 5,587,710 (1997): 'Syntax based arithmetic coder and decoder' Throughout his career, Dr. Choo has been actively involved in both academic and industry collaborations. He has served as a technical consultant for numerous Silicon Valley companies including National Semiconductor (now Texas Instruments), Philips Semiconductor, Skybox Imaging (acquired by Google), Novariant (now AgJunction), and Ricoh Innovations. His industry experience informs his teaching approach, which emphasizes practical implementation considerations alongside theoretical foundations. Dr. Choo has also served as an expert witness in intellectual property court cases involving audio and video compression algorithms and FPGA hardware. Dr. Choo directs the FPGA/DSP AI/DL Laboratory at San José State University, which focuses on developing hardware-accelerated solutions for real-time AI applications. The lab maintains strong connections with Silicon Valley technology companies and provides students with hands-on experience in cutting-edge hardware design methodologies. Current research directions include autonomous vehicle navigation systems, medical imaging applications, and edge AI deployment strategies.

Ying Xuمشاهده پروفایل

پژوهشگر

• Neuromorphic Engineering
• Neuromorphic Auditory Systems and Applications
• Mixed-signal VLSI Design
• +۲ مورد دیگر

Dr. Ying Xu serves as a Researcher at the International Centre for Neuromorphic Systems (ICNS) within Western Sydney University, specializing in neuromorphic computing and hardware implementations. Her academic qualifications include: PhD from Western Sydney University (2019) M.Sc. in Microelectronics from Waseda University, Japan (2008) Bachelor of Electrical Engineering from Xidian University (2006) Her research focuses on biologically inspired computing systems with expertise in neuromorphic auditory processing , analog-digital circuit design , and hardware-accelerated machine learning . She bridges theoretical neuromorphic principles with practical VLSI implementations for next-generation computing architectures. Based at Western Sydney University's Penrith (Werrington South) campus in Room BA.2.01, she contributes to the ICNS research ecosystem advancing neuromorphic technologies through mixed-signal hardware solutions.

Orlando Hernandezمشاهده پروفایل

دانشیار

• VLSI Architectures
• Computer Vision
• Image Processing
• +۴ مورد دیگر

Orlando Hernandez is an Associate Professor in the Department of Electrical and Computer Engineering at The College of New Jersey. He holds a Ph.D. in Electrical Engineering from Southern Methodist University (2002), an M.S.E.E. (1993) and B.S.E.E. (1991) from the University of South Florida. Prior to his academic career, he held industry positions at Texas Instruments and Maxim Integrated Products from 1993-2003, serving in design management roles for imaging systems, ASIC development, and microcontroller technologies. His research focuses on high-performance VLSI architectures for computer vision applications, including color image segmentation, digital signal processing, embedded systems, and mixed-signal design. Key research areas include hardware acceleration for image compression algorithms, real-time traffic monitoring systems, autonomous robotics, and advanced encryption implementations. His work consistently bridges theoretical algorithms with practical hardware implementations. Professional affiliations include Senior Membership in the Institute of Electrical and Electronics Engineers (IEEE). He has secured multiple research grants including a $93,320 National Science Foundation award for image processing instrumentation and several industry-sponsored equipment grants from Texas Instruments and Xilinx.

• Neural Networks
• Embedded Systems Design
• FPGA and ASIC Implementation
• +۷ مورد دیگر

Yu Yang is a Researcher at KTH Royal Institute of Technology's Division of Electronics and Embedded Systems. He has been affiliated with KTH since at least 2020 and currently holds a postdoc position. His research focuses on neuromorphic computing, FPGA/ASIC implementation, approximate computing, and embedded systems design. He also explores ergonomic applications using wearable sensors to address workplace safety and musculoskeletal disorders. Yang has taught courses like Digital Design and Embedded Hardware Design in ASIC and FPGA , demonstrating expertise in both theoretical and applied electronics. His work bridges hardware acceleration (e.g., memristor-based neural networks) with practical applications like surgeon workload analysis and posture correction systems. Notable projects include the eBrainII ASIC implementation of a human-scale cortical model and developing smart workwear systems for real-time vibrotactile feedback. Publications span IEEE conferences (DATE, FDL, ASP-DAC) and journals like Frontiers in Neuroscience and Journal of Signal Processing Systems . His research often emphasizes low-power, high-performance computing while addressing ergonomic challenges in manufacturing and healthcare sectors.

Luciano Lavagnoمشاهده پروفایل

استاد

• Asynchronous Circuit Design
• Embedded Systems
• Logic Synthesis
• +۴ مورد دیگر

Luciano Lavagno is a prominent academic in computer science and engineering, specializing in asynchronous circuit design, logic synthesis, and embedded systems. He has collaborated extensively with researchers like Alberto Sangiovanni-Vincentelli, Joaquim Cortadella, and Alex Yakovlev. Key contributions: Hazard-free asynchronous circuits, STG manipulation, FPGA synthesis frameworks Research focus: Formal verification, design methodologies, hardware-software co-design His publications from 1991–2025 demonstrate sustained innovation in asynchronous control logic, embedded system validation, and machine learning hardware acceleration. Notable works include SIS (sequential synthesis) and Petrify (asynchronous controller tool). While his 2018 DiracDeltaNet work extended into neural network optimization, his core expertise remains rooted in formal methods for circuit design.

• Post-Quantum Cryptography
• Lattice-Based Cryptography
• Hardware/Software Co-Design
• +۱۰ مورد دیگر

Tim Fritzmann is a researcher at the Department of Security in Information Technology (Technische Universität München). His work focuses on post-quantum cryptography, lattice-based algorithms, and secure hardware/software co-design for constrained environments like automotive systems and embedded devices. Post-Quantum Cryptography Lattice-Based Cryptography Hardware/Software Co-Design Error-Correcting Codes RISC-V Architecture ASIC Design His recent publications (2018–2022) highlight advancements in fault attacks, side-channel countermeasures, and efficient implementations of lattice-based protocols for IoT, automotive systems, and FPGA-SoC platforms. Key themes include parameter optimization for decryption reliability, masked accelerators, and instruction-set extensions for quantum-resistant algorithms. Research projects involve collaborations with institutions like the University of Leuven and TU München, emphasizing post-quantum security integration into real-world hardware architectures. No explicit awards or student advisement details are listed publicly.

Andrew B. Kahngمشاهده پروفایل

استاد

• VLSI Physical Design
• Design for Manufacturability
• AI in Chip Design
• +۳ مورد دیگر

Andrew B. Kahng is a Distinguished Professor of Computer Science & Engineering and Electrical and Computer Engineering at the University of California San Diego. He leads research in VLSI physical design, AI-driven chip design, and semiconductor roadmapping. His work focuses on advancing EDA tools, such as the OpenROAD Project and TILOS AI Institute, to address challenges in chip design automation. He has authored over 500 publications, holds 35 patents, and is a Fellow of both ACM and IEEE. His accolades include the 2019 Ho-Am Prize in Engineering. Key affiliations include the VLSI CAD Laboratory and leadership roles in international conferences like DAC and ISPD. Kahng has mentored numerous students, contributing to their academic and professional success. His research spans from foundational algorithms (e.g., placement and routing) to industry collaboration through initiatives like the OpenROAD Project, which provides open-source tools for chip design. Recent advancements include ML integration in EDA, pathfinding frameworks (PROBE3.0), and contributions to the semiconductor technology roadmap. His work emphasizes open-source ecosystems and interdisciplinary collaboration to drive innovation in microelectronics.

Kun Qinمشاهده پروفایل

پژوهشگر

• Hardware/Software Codesign
• RISC-V Architecture
• Open-Source Hardware
• +۳ مورد دیگر

Kun Qin is a Doctoral Candidate and Research Associate at the Technical University of Munich , affiliated with the IH02 Chair of Computer Architecture and Operating Systems (CAOS) and the I10 Chair of Computer Architecture and Parallel Systems (CAPS). His work focuses on Hardware/Software Codesign , RISC-V Architecture , and Quantum Computing . Current affiliation: Department of Computer Engineering, School of Computation, Information and Technology Research areas: FPGA/ASIC design, quantum-based systems, open-source hardware Teaching: Courses on HDL, Computer Architecture, and Operating Systems (WS23/24–WS24/25) Kun actively participates in academic service as Web Co-Chair for the ACM International Conference on Computing Frontiers (CF'24, CF'25). His research includes FPGA acceleration for RTL verification and quantum control processors. Key scientific achievement: Best Poster Award at SERESSA (2023) . Publications span topics like RISC-V verification frameworks, FPGA-based timing systems, and quantum control processors for superconducting qubits.

Woo-Chan Parkمشاهده پروفایل

استاد

• Computer Engineering
• Graphics Processing Units
• Virtual Reality
• +۴ مورد دیگر

Woo-Chan Park is a Professor in the Department of Computer Science and Engineering at Sejong University, specializing in high-performance GPU hardware/software, VR/AR technologies, and AI-driven mobile systems. He leads the eXtended Reality Research Center and actively contributes to computational hardware innovation. Education Ph.D. (2000), M.S. (1995), B.S. (1993) from Yonsei University His research focuses on real-time graphics processing, embedded systems for VR/AR, and energy-efficient AI hardware. Recent work includes advancements in mobile GPU architectures and sound propagation algorithms for immersive environments. Key publication trends highlight expertise in GPU design, ray tracing optimization, and FPGA/ASIC implementations for VR/AR applications, with a strong emphasis on latency reduction and power efficiency. Scientific Awards Recognized in 'Hot start-up to watch: silicon 60' by EE Times Park founded SiliconArts Inc. in 2001 and maintains an active research laboratory at Sejong University, accessible via his personal website . His work spans 28 years (1996-2024) with 70+ research outputs.

• Digital Signal Processing (DSP)
• Field-Programmable Gate Arrays (FPGA)
• Machine Learning Hardware Acceleration
• +۱۳ مورد دیگر

Gian Carlo Cardarilli is a researcher specializing in digital hardware design and machine learning acceleration. His work focuses on FPGA implementations, Residue Number System (RNS) architectures, and reconfigurable computing for applications in wireless communication, edge AI, and fault-tolerant systems. Key collaborations with institutions like IEEE and ACM through publications. Active in translating theoretical algorithms into practical hardware solutions for real-time systems. Research interests include: Optimizing deep learning models for heterogeneous platforms. Developing radiation-hardened memory systems. Creating energy-efficient signal processing architectures. Advancing reconfigurable functional units for embedded processors. His article analyses span fields like Quantum Cellular Automata , Variable Fractional Delay Filters , and RNS-Based Position Estimation , reflecting a trend toward adaptive, low-power, and domain-specific hardware.

Christian Heidornمشاهده پروفایل

پژوهشگر

• Deep Learning
• Hardware-Software Co-Design
• Neural Networks
• +۵ مورد دیگر

Christian Heidorn is a Researcher at the Chair of Computer Science 12 (Hardware-Software Co-Design) within the Department of Computer Science at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany. He has held this position since 2018 and teaches "Fundamentals of Computer Engineering" regularly across multiple semesters. His educational background includes an M.Sc. in Medical Engineering (2015-2018) and a B.Sc. in Medical Engineering (2012-2016), both from FAU. Born in 1989 in Dachau, Germany, he maintains an office in Room 02.128 at Cauerstr. 11, Erlangen. Dr. Heidorn's research focuses on the Application of Deep Learning on Tightly Coupled Processor Arrays and Invasive Computing . His work bridges medical engineering with computer architecture, particularly emphasizing neural network deployment on specialized hardware. His research projects include OpTC and KISS Invasive Computing, which optimize neural networks for embedded systems and processor arrays. His recent publications demonstrate a strong trend toward efficient neural network deployment on embedded systems, with emphasis on automotive applications (AURIX microcontrollers), hardware-aware neural network pruning, and processor array optimization. His work spans both theoretical neural architecture search and practical implementations for real-world applications. His notable scientific contributions include: Development of the OpTC toolchain for neural network deployment on automotive microcontrollers Hardware-aware evolutionary filter pruning techniques for CNNs ALPACA: An accelerator chip design for nested loop programs Efficient mapping of CNNs onto tightly coupled processor arrays Dr. Heidorn has supervised numerous Master's and Bachelor's theses on topics ranging from neural network compression to robotic hand control using EMG data and processor array optimization. His advising reflects his dual expertise in medical engineering and computer architecture, with many projects focusing on practical embedded applications of deep learning. He is actively involved in research projects related to invasive computing and tightly coupled processor arrays, with a particular focus on making deep learning more accessible on resource-constrained devices for automotive and medical applications.

James Garlandمشاهده پروفایل

مدرس

• Machine Learning
• Embedded Systems
• FPGA/ASIC Design
• +۴ مورد دیگر

Dr. James Garland is a Lecturer in the Department of Electronic Engineering and Communications at South-East Technological University (SETU), part of the engCORE academic unit. He holds a PhD in Computer Science from Trinity College Dublin (2022). His research focuses on micro-architectural implementations of deep learning algorithms in FPGA/ASIC/embedded systems, with applications in robotics and aerospace engineering. Key areas include defect detection via unmanned aircraft systems, image classification, and GAN-based enhancement for license plate recognition. Education: PhD in Computer Science (Trinity College Dublin, 2022). Research interests span machine learning optimization, embedded systems design, and aerospace robotics. His work emphasizes low-complexity hardware solutions for high-performance computing and energy efficiency. Recent articles explore topics like super-resolution GANs, zero-shot learning in pre-trained models, and spatial mapping for aircraft defect localization. He actively contributes to peer-reviewed journals, including Journal of Universal Computer Science and IEEE Access . Media coverage includes collaborations with the Irish Department of Aerospace and Mechanical Engineering. Teaching responsibilities include courses on artificial intelligence, control systems, and avionics fundamentals.

Khan Wahidمشاهده پروفایل

استاد

• Health informatics
• Wireless capsule endoscopy
• Wearable health monitoring
• +۵ مورد دیگر

Professor Khan Wahid is a faculty member in the Department of Electrical and Computer Engineering at the University of Saskatchewan , affiliated with the Division of Biomedical Engineering . His research focuses on health informatics, IoT infrastructure, medical imaging, and wearable health monitoring , with notable contributions to wireless capsule endoscopy, smart-city applications, and sensor systems. He holds a GCC Stars in Global Health Award (2013) and has secured funding from multiple government and institutional grants. Education: BSc, MSc, PhD in relevant fields (details not specified in text). Research Interests : Health informatics & smart-health systems IoT design/deployment and drone infrastructure Medical imaging reconstruction (CT/MRI) Wireless sensor networks and body area networks Quantum-dot cellular automata (QCA) for nanoelectronics FPGA/ASIC-based embedded systems Funding & Recognition : Harper Government investment in medical imaging (2014) UofS GCC Stars in Global Health Award (2013) Advising & Grants : Supervises graduate students in interdisciplinary projects (specific names not listed). Active in securing grants for IoT-enabled healthcare and agricultural sensing systems. Collaborates on projects involving smart-pill devices, fluorometers for cancer detection, and LiDAR-based plant phenotyping. Labs & Teams : Leads projects integrating biomedical engineering, IoT, and nanotechnology within the College of Engineering. Collaborations span academic and industrial partners for medical device innovation.

Ramesh Karriمشاهده پروفایل

استاد

• Hardware Cybersecurity
• Trustworthy Integrated Circuits
• Cyber-Physical Systems Security
• +۶ مورد دیگر

Ramesh Karri is a Professor and Chair of the Electrical and Computer Engineering Department at New York University Tandon School of Engineering. He co-founded the NYU Center for Cyber Security (CCS) in 2009 and co-directed it from 2016-2024. He is also a Fellow of the IEEE and has led initiatives such as the Embedded Systems Challenge (ESC), a red-blue team cybersecurity competition. Education: Ph.D. in Computer Science and Engineering, University of California, San Diego (1993) B.E. in Electrical and Computer Engineering, Andhra University (1985) Research Focus: His work centers on hardware cybersecurity, including trustworthy integrated circuits, cyber-physical systems, nano-enabled security, and biochip security. He pioneered security-aware CAD tools and has developed metrics for hardware trojan detection through initiatives like the Trust-Hub. Awards & Leadership: Recipient of the Humboldt Fellowship and NSF CAREER Award Editor-in-Chief of ACM Journal of Emerging Computing Technologies Leadership roles at IEEE conferences (ICCD, HOST, DFTS) Grants & Labs: Directs the Center for Advanced Technology in Telecommunications (CATT) and NYU CCS. His labs focus on additive manufacturing security, digital microfluidic systems, and AI-driven hardware design.