Luca Benini is a Full Professor at the Department of Information Technology and Electrical Engineering at ETH Zurich. He works at the Institute for Integrated Systems, located at Gloriastrasse 35, 8092 Zurich, Switzerland. His contact number is +41 44 632 66 64. Research Interests: Focus on VLSI design and FPGA-based systems development. Teaching: Offers the course VLSI 1: HDL Based Design for FPGAs in the Fall semester 2025. Contact: lbenini@iis.ee.ethz.ch
Shweta Shinde is an Assistant Professor at ETH Zürich's Department of Computer Science. She leads the Secure & Trustworthy Systems (SECTRS) group and is affiliated with the Institute of Information Security and the ZISC Center. Her research focuses on foundational and practical aspects of trusted computing, system security, and program analysis to protect devices ranging from smartphones to cloud servers. Key areas include AMD SEV-SNP, Arm CCA, Intel SGX, and hardware-software co-design for security. Dr. Shinde has made significant contributions to confidential computing, including frameworks like OpenCCA and tools for analyzing hardware vulnerabilities. Her work has been recognized with Best Paper Awards and Distinguished Paper Awards at top venues. She advises a group of PhD students, including Mark Kuhne, Supraja Sridhara, and Benedict Schlüter. Her service includes program committee roles at IEEE Security & Privacy, USENIX Security, and as Track Co-Chair for AsiaCCS 2026.
Prof. Dr. Timothy Roscoe is a Full Professor in the Department of Computer Science at ETH Zurich. His research focuses on operating systems, networking, and distributed systems. He was inducted as an ACM Fellow in 2014 for contributions to these fields. Previously, he worked at Intel Research Berkeley, UC Berkeley (Adjunct Professor), and Sprint Labs. His work includes foundational contributions to systems like PlanetLab, P2 Declarative Networking, and the Nemesis OS. Roscoe holds a PhD from the University of Cambridge and has led projects in cloud computing, wide-area network measurement, and secure systems design. His current research emphasizes hardware-software co-design, formal verification of systems, and scalable memory architectures. Education: PhD in Computer Science, University of Cambridge (1995) Key Roles: Principal Researcher at Intel Berkeley Lab, Visiting Researcher at National ICT Australia Research Highlights: Contributions to distributed systems (PlanetLab), declarative networking (P2), and secure microkernels (seL4 integration). Current projects address challenges in disaggregated memory systems, coherent interconnects, and trustworthy embedded systems. Awards: ACM Fellow (2014), numerous grants and industry collaborations. Labs/Teams: Systems Group at ETH Zurich, focusing on OS design, hardware architectures, and formal methods.
Gustavo Alonso is Full Professor at the Department of Computer Science (D-INFK) of ETH Zurich and Head of the Institute for Computing Platforms . He has been at ETH since 1995, first as a post-doc, then as Assistant Professor from April 1998, and promoted to Full Professor in October 2001. Within the Systems Group he leads the Information and Communication Systems Research Group . Education: 1989 – Telecommunications Engineering (undergraduate), Madrid Technical University (UPM-ETSIT), Spain 1992 – M.S. Computer Science, University of California, Santa Barbara (UCSB) 1994 – Ph.D. Computer Science, University of California, Santa Barbara (UCSB) Research Interests: His work spans databases, distributed systems, cloud-computing architecture, FPGAs, hardware acceleration for data science, parallel and reconfigurable computing . The group investigates how modern heterogeneous hardware—from GPUs to SmartNICs—can be integrated into data-processing systems to achieve orders-of-magnitude performance gains, energy savings, and new functionality such as in-network computation and serverless acceleration. Scientific Awards & Honors: Fellow of the ACM (Association for Computing Machinery) Fellow of the IEEE (Institute of Electrical and Electronics Engineers) Distinguished Alumnus, Department of Computer Science, UC Santa Barbara Four Test-of-Time / Most Influential Paper Awards across databases, programming languages, cloud computing, and software engineering Labs & Projects: He directs the Information and Communication Systems Research Group within the Systems Group ( systems.ethz.ch ). The lab develops open-source platforms such as Coyote v2 for FPGA abstractions, Shuhai for HBM benchmarking, and MicroRec for micro-second recommendation serving, while collaborating with industry on SmartNICs, serverless analytics, and cloud-scale data analytics.
Swiss Federal Institute of Technology in LausanneSwitzerland
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
Swiss Federal Institute of Technology in LausanneSwitzerland
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
Dr. David Cock is a Senior Lecturer and Senior Researcher at ETH Zürich's Department of Computer Science, affiliated with the Systems Group. He holds a PhD from UNSW (2014) and a B.Sc. (hons) from UNSW (2004). His research focuses on formal verification, trustworthy systems, and hardware-software co-design, with notable contributions to projects like Enzian (a CPU/FPGA platform) and seL4 (formally verified kernel). He teaches Advanced Operating Systems and Informal Methods courses. Key achievements include the ACM Software System Award (2022) for seL4 and leadership in projects addressing hardware complexity and security. Research interests include formal methods for hardware modeling (Sockeye project), runtime verification, and mitigating timing channels. His work bridges theoretical foundations with practical systems, emphasizing secure and reliable computing platforms. Projects like Trustworthy BMC aim to enhance baseboard management systems' assurance. Collaborations span academia and industry, with open-source contributions to hardware designs and formal tools. Publications span formal verification, hardware modeling, and secure systems, with recent focus on heterogeneous computing and declarative hardware specifications. Teaching emphasizes practical formal techniques and OS design, leveraging real-world hardware (e.g., Barrelfish). His lab, the Systems Group, explores cutting-edge challenges in systems software and architecture.
Swiss Federal Institute of Technology in LausanneSwitzerland
Dr. Samuel Burri is a researcher affiliated with the Department of Electrical and Computer Engineering at the Ecole Polytechnique Federale de Lausanne (EPFL) in the School of Engineering. His work spans interdisciplinary domains including photonics, biomedical imaging, and sensor technology. Research Interests: Photonics and quantum imaging Time-resolved single-photon detection Biomedical and fluorescence lifetime imaging Computational imaging algorithms CMOS-integrated sensor arrays High-resolution optical devices Recent Publications (2017–2025) highlight advancements in SPAD arrays, LinoSPAD systems, and quantum 3D imaging, with applications in biomedical diagnostics and optical coherence analysis. Collaborations include institutions like Università degli Studi di Bari and EPFL STI IMT AQUA .
Zurich University of Applied Sciences (ZHAW)Switzerland
Tobias Welti is a Senior Lecturer at the Zurich University of Applied Sciences (ZHAW) School of Engineering, specializing in System on Chip Design and Computer Engineering . He leads the research focus area on System on Chip – Embedded AI and Edge Processing and serves as Deputy Programme Director for Electrical Engineering. Education: CAS in Didactics of Higher Education (PHZH, 2019–2020) BSc in Computer Science (UAS Zurich, 2010–2015) MSc in Chemistry (ETH Zurich, 1998–2003) His research spans System-on-Chip design , FPGA-based AI acceleration , and low-latency wireless video transfer for applications including medical endoscopes. Recent work includes the MAX78002 CNN accelerator and EdgeAI-Trust EU project. Key trends in his publications include heterogeneous computing (FPGA-CPU integration), real-time neural network deployment , and wireless system reliability . These appear in venues like the Embedded World Conference and Embedded Computing Conference (ECC).
University of Applied Sciences and Arts Northwestern SwitzerlandSwitzerland
Stefan Brantschen is a Lecturer at the University of Applied Sciences and Arts Northwestern Switzerland , affiliated with the School of Engineering and Environment . He works at the intersection of digital microelectronics, algorithm development, and hardware verification using VHDL. Role: Research associate and lecturer in digital design Expertise: FPGA/ASIC implementation, architecture development, functional safety standards (DO-254) His research focuses on digital microelectronics , emphasizing practical implementation from concept to real-world deployment. He also contributes to functional safety verification frameworks in industrial applications. Stefan supervises Master projects in digital microelectronics and teaches VHDL programming and digital design methodologies.
Ataberk Olgun is a Lecturer at the Department of Information Technology and Electrical Engineering at ETH Zürich, where he conducts research in the SAFARI Research Group under Professor Onur Mutlu. His work focuses on computer architecture with particular emphasis on memory systems, DRAM reliability, and security vulnerabilities such as RowHammer. His educational background includes BSc and MSc degrees from TOBB ETÜ (Ankara University of Economics and Technology) under Professor Oğuz Ergin's supervision. Prior to his doctoral work at ETH Zürich, he worked at Kasirgalabs until 2021, leading the design of a RISC-V system-on-chip manufactured using SKY130 technology, and previously developed authentication methods based on behavioral biometrics with Professor Kemal Bicakci. Olgun's research interests center on designing reliable and energy-efficient memory systems. He has developed FPGA-based testing platforms for DDR3/4 and HBM2 DRAM chips, created end-to-end systems for processing-in-memory techniques, and made significant contributions to understanding and mitigating the RowHammer problem. His work often combines hardware design with system-level considerations to address fundamental challenges in modern memory technology. His publication record shows consistent output in top-tier venues including ACM TACO, USENIX Security, ISCA, MICRO, and HPCA, with a clear trend toward increasingly sophisticated investigations of DRAM vulnerabilities and innovative mitigation strategies. Recent work focuses on fine-grained DRAM architectures, scalable RowHammer mitigation techniques, and experimental characterization of emerging memory technologies. As part of the SAFARI Research Group at ETH Zürich, Olgun collaborates extensively with Professor Onur Mutlu and other researchers on memory systems research. His technical expertise spans FPGA-based prototyping, DRAM characterization, hardware security, and memory controller design. Olgun maintains an active research presence with numerous ongoing projects investigating next-generation memory technologies, security vulnerabilities in modern DRAM, and energy-efficient memory system designs. His work bridges theoretical understanding with practical implementation through FPGA-based experimental platforms.
Javier Moya Paya is a Senior Scientist at ETH Zürich’s Systems Group, where he leads the Heterogeneous Accelerated Compute Cluster (HACC) under the AMD Xilinx University Program. Previously, he served as Head of Engineering/CTO at GRAPIN AG (2018–2022), developing cloud-native FPGA-based computing solutions, and as Senior R&D Engineer at the Competence Center for Intelligent Sensor Networks (CC-ISN) at Lucerne School of Engineering and Architecture (2012–2018). He holds a Ph.D. in Electronics Engineering (2012) and degrees from the Universitat Politècnica de València (UPV, Spain). His research focuses on hardware design, FPGA accelerators, and high-performance computing. Education: B.Sc. in Telecommunications Engineering (2007), UPV M.Sc. in Signal Processing and Communications (2008), UPV Ph.D. in Electronics Engineering (2012), UPV Research Interests: Javier’s work bridges hardware design and cloud computing, emphasizing FPGA-based acceleration, real-time signal processing systems, and scalable computing architectures. His contributions include advancing hyper-scale data center technologies and optimizing parallel computing frameworks. Labs/Teams: Integral to ETH Zürich’s Systems Group, he drives innovation in the HACC cluster, leveraging FPGA and heterogeneous computing for cutting-edge applications.
Zurich University of Applied Sciences (ZHAW)Switzerland
Dr. Stephan Neuhaus is a Senior Lecturer at the Zurich University of Applied Sciences (ZHAW), School of Engineering, where he contributes to the Research Focus Information Security. His work bridges applied research and practical implementation in cybersecurity, with a focus on software security, embedded systems, and human factors. Research Focus: Information Security Institution: ZHAW School of Engineering Location: Winterthur, Switzerland His research interests span information security, software testing, embedded systems security, network transparency, and usable security. He investigates how security mechanisms can be effectively implemented in real-time systems and how users interact with security-critical systems like password entry and phishing detection. His recent publications, from 2016 to 2025, reflect a strong trend in applied cybersecurity research. Key themes include fuzzing for GNSS modules, real-time security policies using BPF on FPGAs, privilege handling frameworks, and network observability. These works appear in top venues such as IEEE and ACM conferences, demonstrating technical depth and relevance to both industry and academia. Dr. Neuhaus has led and contributed to several applied research projects, including Malicious Node (lateral movement detection), OptiPhish (phishing awareness training), ATLAS (data management for pharma), and Identity Management for Wireless Networks. These projects highlight his leadership and collaboration in interdisciplinary, real-world security challenges. He is actively involved in research teams and collaborates with colleagues across institutions, particularly in projects involving secure embedded systems and network security. His work often involves FPGA implementations, software toolchains, and human-centered security evaluation.
Western Switzerland University of Applied SciencesSwitzerland
Alberto Dassatti is a Full Professor at HES-SO University of Applied Sciences Western Switzerland and Director of the Reconfigurable & Embedded Digital Systems (REDS) Institute. He is affiliated with the School of Engineering and Management of the Canton of Vaud. His work focuses on embedded systems, FPGA applications, high-performance computing, and topological data analysis. He has led and collaborated on numerous projects funded by institutions like Innosuisse and HES-SO Rectorat, totaling over CHF 1.2 million in grants. His research spans computational storage systems, medical sensor technologies, and signal processing frameworks for wireless communication. Key projects include developing the CarbonViz energy visualization tool, advancing topological methods for AI reliability, and creating the BB-Sensors system for neonatal vital monitoring. He has contributed to open-source frameworks like giotto-tda and gr-dnn, emphasizing interdisciplinary collaboration between hardware and software domains. His publications span topics such as FPGA-GPU communication, real-time embedded systems optimization, and heterogeneous computing architectures. He actively participates in conferences like NeurIPS and IEEE SOC, showcasing innovations in reconfigurable computing and energy-efficient systems.
Swiss Federal Institute of Technology in LausanneSwitzerland
Marco Mattavelli is a Professor at the École Polytechnique Fédérale de Lausanne (EPFL), affiliated with the School of Engineering (STI) and the Microsystems Engineering Laboratory (MM). His research focuses on data compression, hardware design for embedded systems, biomedical electronics, and blockchain/metaverse applications. He leads the GRAMM lab and has contributed to standards like MPEG-G for genomic data. His work spans FPGA-based systems, signal processing, and implantable medical devices. Education and affiliations: EPFL faculty since at least 2000, with roles in teaching and research. Collaborations include MPEG standards development, multidisciplinary projects in genomics and biomedical engineering. Research interests emphasize interdisciplinary innovation: genomic data compression, high-performance embedded systems, and leveraging blockchain for digital assets. His lab develops cutting-edge solutions for medical devices and energy-efficient electronics. Publications highlight contributions to neural clustering algorithms, genomic compression, and metaverse data analysis. Over 200 publications in top venues like IEEE Transactions and conferences like DCC, ICASSP, and BioCAS. Grants and labs: Active in securing research funding for projects in biomedical sensors, heterogeneous computing, and genomic standards. The GRAMM lab is central to his research activities.
