معرفی
Javier Moya Paya is a Senior Scientist at ETH Zürich’s Systems Group, where he leads the Heterogeneous Accelerated Compute Cluster (HACC) under the AMD Xilinx University Program. Previously, he served as Head of Engineering/CTO at GRAPIN AG (2018–2022), developing cloud-native FPGA-based computing solutions, and as Senior R&D Engineer at the Competence Center for Intelligent Sensor Networks (CC-ISN) at Lucerne School of Engineering and Architecture (2012–2018). He holds a Ph.D. in Electronics Engineering (2012) and degrees from the Universitat Politècnica de València (UPV, Spain). His research focuses on hardware design, FPGA accelerators, and high-performance computing.
Education:
- B.Sc. in Telecommunications Engineering (2007), UPV
- M.Sc. in Signal Processing and Communications (2008), UPV
- Ph.D. in Electronics Engineering (2012), UPV
Research Interests: Javier’s work bridges hardware design and cloud computing, emphasizing FPGA-based acceleration, real-time signal processing systems, and scalable computing architectures. His contributions include advancing hyper-scale data center technologies and optimizing parallel computing frameworks.
Labs/Teams: Integral to ETH Zürich’s Systems Group, he drives innovation in the HACC cluster, leveraging FPGA and heterogeneous computing for cutting-edge applications.
