جست‌وجوی استاد و پژوهشگر

Nathan Beckmannمشاهده پروفایل

استاد

• Computer Architecture
• Embedded Systems
• Energy-Efficient Computing
• +۴ مورد دیگر

Nathan Beckmann is a Courtesy Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University, part of the College of Engineering. His research focuses on computer architecture, embedded systems, energy-efficient computing, and memory hierarchy design. He explores topics such as dataflow architectures, near-data computing, and cache optimization to enhance performance and reduce energy consumption in modern systems. His work spans both theoretical and applied aspects, including hardware-software co-design for reconfigurable systems, low-power IoT architectures, and novel caching strategies for emerging memory technologies like flash and MRAM. Key contributions include frameworks for ultra-low-power CGRAS, energy-minimal dataflow SoCs, and sustainable caching solutions. Dr. Beckmann's recent articles emphasize innovations in spatial dataflow programming models, task parallelism control, and polymorphic cache hierarchies. His research often targets real-world applications in edge computing, embedded systems, and high-performance datacenters.

• Space Engineering
• Aerospace Systems
• Control Systems
• +۳ مورد دیگر

Dr. Xiaofeng Wu is a Senior Lecturer in Space Engineering at the University of Sydney's School of Aerospace, Mechanical and Mechatronic Engineering. His research focuses on space systems, robotics, and control engineering with applications in satellite technology, additive manufacturing, and autonomous navigation. He holds a BEng from Northwestern Polytechnical University and a PhD from Loughborough University. **Education**: BEng in Space Engineering, School of Astronautics, Northwestern Polytechnical University (China) PhD in VLSI Design for Real-Time Control, Loughborough University (UK) **Research Interests**: Dr. Wu's work spans space engineering innovations such as satellite attitude control systems, on-orbit 3D printing, and robotic manipulators. He integrates neural networks, Kalman filters, and reinforcement learning to address challenges in space robotics and autonomous navigation. Recent projects include lunar navigation systems and fault-tolerant manufacturing solutions for space environments. **Grants & Collaborations**: He leads projects funded by NSW Space Research Network (SRN) and SmartSat CRC, focusing on lunar navigation, on-orbit refueling, and satellite communication networks. Collaborates with Reach Robotics on space robotics solutions. **Teams & Labs**: Member of the Sydney Institute of Agriculture. Involved in the INSPIRE-2 CubeSat project and QB50 initiative. Teaches courses like Spacecraft Design and Instrumentation.

Rob A. Rutenbarمشاهده پروفایل

استاد مدعو

• Integrated Circuit Design
• Hardware Accelerators for AI
• Nanoscale Statistics in Chip Design
• +۵ مورد دیگر

Rob A. Rutenbar is the Senior Vice Chancellor for Research at the University of Pittsburgh and holds Distinguished Professor appointments in the School of Computing and Information and Swanson School of Engineering. He previously served as Head of Computer Science at the University of Illinois (2010-2017) and chaired Electrical and Computer Engineering at Carnegie Mellon University for 25 years. His research focuses on integrated circuit design tools, nanoscale statistical modeling, and hardware accelerators for AI. He founded companies Neolinear (acquired by Cadence) and Voci Technologies (acquired by Medallia). Rutenbar has authored over 200 publications and mentored 50+ students. He is an ACM/IEEE Fellow and recipient of the Phil Kaufman Award and ACM SIGDA Pioneering Achievement Award. Education: PhD in Computer Engineering (University of Michigan, 1984), MS (1979), BS in Electrical Engineering (Wayne State University, 1978). Research Interests: Tools for analog IC design, statistical models for nanoscale circuits, and AI hardware architectures. Notable projects include the Center for Circuit & System Solutions (C2S2) and the first EDA MOOC on Coursera with 100k+ learners. Awards: Includes ACM SIGDA Pioneering Achievement Award (2021), AAAS Fellow (2019), Phil Kaufman Award (2017), and Donald O. Pederson Best Paper Award (2011, 2013). Leadership: Launched Pitt Momentum Funds, LifeX Labs, and the CS+X interdisciplinary degree program at Illinois. Serves as Chair-Elect of the APLU Council on Research.

• Digital Communications
• Neural Networks
• Medical Engineering
• +۳ مورد دیگر

Matthieu ARZEL is an Associate Professor in the Department of Mathematical and Electrical Engineering at IMT Atlantique. He holds an HDR (2021), PhD (2006), and Engineer degree (2002) from Telecom Bretagne/ENST. His research focuses on iterative processing for digital communications, low-power integrated circuits, high-speed digital circuits, and FPGA implementations in domains like neural networks, medical engineering, and communication systems. Key research interests include neuromorphic hardware, neural network pruning, federated learning compression, and energy-efficient signal processing. He has supervised 18 PhD students and contributed to projects like Ouessant coprocessor architectures and clique-based neural network circuits. His work bridges algorithm-architecture interactions, emphasizing low-power and embedded system applications. Recent publications highlight innovations in FPGA-based deep learning deployment and efficient neural network compression techniques. Publications span topics from real-time semantic segmentation on FPGA to collusion-resistant watermarking. His contributions address challenges in hardware-software co-design, iterative decoders for MIMO systems, and biomedical signal processing.

Martin Schulzمشاهده پروفایل

استاد

• Parallel and Distributed Architectures
• Performance Monitoring and Analysis
• Memory System Optimization
• +۴ مورد دیگر

Prof. Martin Schulz is a Full Professor and Chair for Computer Architecture and Parallel Systems at Technische Universität München (TUM), joining in 2017. He also serves on the board of directors at the Leibniz Supercomputing Centre. Previously, he worked at Lawrence Livermore National Laboratory (LLNL) and Cornell University. His research focuses on parallel architectures, quantum computing integration, HPC optimization, and fault tolerance. He has published over 250 papers and chairs the MPI Forum, a key standard in HPC. Education: Doctorate in Computer Science (TUM, 2001), Master of Science (UIUC). Research Interests: Parallel systems, performance analysis, quantum computing, memory optimization, and tool support for HPC. Awards: Gordon Bell Award (2006), R&D 100 Award (2011), Best Paper Awards at IPDPS and SC. Grants/Projects: SEANERGYS, PlasmaPEPS, OpenCUBE, and others. Active in academic service, including program chairs for ISC, EuroMPI, and IPDPS.

• Network Security
• Decentralized Systems
• Privacy-Preserving Technologies
• +۷ مورد دیگر

Prof. Björn Scheuermann is a Professor in the Department of Computer Science at Technische Universität Kaiserslautern, Germany. His research focuses on network security, decentralized systems, privacy-preserving technologies, and distributed algorithms. He has contributed to foundational work on anonymization protocols (e.g., Tor improvements), blockchain systems, and vehicular networks. His work often bridges theoretical computer science with practical implementations in domains like satellite communication and industrial IoT. Key areas of research include: Decentralized Systems: Analysis of IPFS, Bitcoin, and blockchain architectures. Anonymity Networks: Improving Tor's fairness and privacy guarantees. Network Security: Collaborative intrusion detection in SDN, firewall acceleration via FPGA. Wireless & Satellite: Optimizing data transmission for low-earth-orbit satellites and industrial sensors. Recent trends in his publications emphasize: Integration of machine learning for adaptive network security (e.g., COML-IDS framework). Dynamic routing protocols for fault tolerance (e.g., OD³R). Privacy in emerging technologies like mobile data donation apps and decentralized storage. His work has been published in top-tier venues like IEEE/ACM Transactions, IFIP Networking, and ACM SIGCOMM workshops. Collaborations span academia and industry, focusing on practical applications of secure and efficient network architectures.

Miriam Leeserمشاهده پروفایل

استاد

• Reconfigurable Computing
• FPGA Accelerators
• Wireless Communications
• +۴ مورد دیگر

Miriam Leeser is a Professor and Associate Chair of Research in the Department of Electrical and Computer Engineering at Northeastern University. She leads the Reconfigurable and GPU Computing Lab, focusing on heterogeneous architectures, FPGA accelerators, and their applications in wireless communications, machine learning, and data privacy. Her work emphasizes practical implementations of theoretical advancements, such as cloud-edge computing frameworks and secure multi-party computation using FPGAs. Leeser holds a PhD in Computer Science from the University of Cambridge and a BS in Electrical Engineering from Cornell University. She has been at Northeastern since 1996 and is a Senior Member of both the IEEE and ACM. Notable recognitions include the National Science Foundation Young Investigator Award and her status as a Charter Member of the IEEE Computer Society Distinguished Contributor Program. Her research portfolio includes projects funded by the NSF on topics like resilient cloud infrastructure (CAREFREE), cross-layer wireless coexistence, and FPGA-enabled secure computation. The Reconfigurable Computing Lab develops tools and libraries to simplify accelerator usage, particularly for emerging applications in IoT, medical imaging, and 5G/6G systems. Key Projects: CAREFREE, P4-based FPGA Testbeds, Secure Function Evaluation via FPGAs, MIMO Systems Acceleration Grants: Over $2M in NSF awards for cloud infrastructure and cybersecurity Labs: Reconfigurable and GPU Computing Lab (RCL) Leeser’s publications span FPGA optimization, hardware-software co-design, and privacy-preserving technologies. Recent work highlights include accelerating large language models with token-adaptive quantization and low-latency optical wireless transceivers.

Warren Grossمشاهده پروفایل

استاد

• Integrated Circuits and Systems
• Error-Correcting Codes
• Hardware Acceleration
• +۵ مورد دیگر

Warren Gross is a Professor and Chair of the Department of Electrical & Computer Engineering at McGill University's Faculty of Engineering. Holding the prestigious James McGill Professor title, he leads research in integrated hardware systems from his office in Montreal's McConnell Engineering Building. His work bridges theoretical coding theory with practical VLSI implementations for next-generation communication networks. Professor Gross specializes in Integrated Circuits and Systems with deep expertise in error-correcting codes, particularly polar and Reed-Muller codes. His research spans hardware acceleration for machine learning, stochastic computing architectures, and VLSI design for low-latency wireless systems. Current projects focus on 6G air interface technologies, energy-efficient edge AI, and novel decoding algorithms that balance performance with hardware constraints. The ISIP Lab (Integrated Systems and Image Processing) serves as his primary research hub, advancing both theoretical frameworks and physical implementations. Analysis of his 2023-2025 publications reveals three dominant trends: (1) Hardware-optimized decoding algorithms for polar codes targeting sub-1ms latency in 6G systems; (2) Model compression techniques for transformer networks deployed on resource-constrained edge devices; (3) Stochastic computing approaches for combinatorial optimization problems. These themes reflect his dual focus on communication theory and efficient hardware realization, with increasing emphasis on machine learning integration. Scientific recognition includes: James McGill Professor (McGill University's highest academic honor) As Department Chair and research leader, Professor Gross oversees multiple collaborative projects with industry partners in telecommunications and semiconductor sectors. His lab maintains active partnerships with 5G/6G standardization bodies and chip manufacturers, though specific grant details aren't publicly enumerated. The ISIP Lab operates advanced VLSI design facilities and FPGA testbeds supporting both academic research and industry prototyping. Research infrastructure includes specialized labs for stochastic computing implementation, polar code decoder validation, and edge AI acceleration. Current efforts focus on quantum-inspired annealing techniques for MIMO detection and hardware-friendly transformer architectures, with several patents pending in decoding methodology and model compression.

Ken Choiمشاهده پروفایل

استاد

• Ultra-Low-Power VLSI Design
• Nanometer Circuit Design
• Design Automation
• +۳ مورد دیگر

Ken Choi is a Professor of Electrical and Computer Engineering at Illinois Institute of Technology's Armour College of Engineering. He joined Illinois Tech in 2007 after working as a senior CAD engineer and technical consultant at Samsung and Sequence Design. His research focuses on ultra-low-power VLSI design, nanoscale circuit optimization, and carbon nanotube FET applications. Education: Postdoctoral Research Associate at University of Tokyo (2005), Ph.D. in ECE from Georgia Tech (2003). Key research interests include Design for Power (DFP) and Design for Manufacturing (DFM) in VLSI systems, as well as low-power SOC design for multimedia applications. He has received multiple awards, including Best Paper Awards from the International Symposium on Wireless Sensor Networks and IEEE ISOCC conferences. His work spans topics like radiation-hardened latch designs, energy-efficient encoder architectures, and clock-gating techniques for ultra-low-power applications.

Thomas Moonمشاهده پروفایل

استادیار

• Signal Processing
• Wireless Communication Systems
• mmWave Radar
• +۵ مورد دیگر

Thomas Moon is a Teaching Assistant Professor in the Department of Electrical & Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC), holding this position since 2019. He previously served as a postdoctoral researcher at UIUC (2017–2019) and a Principle Test Development Engineer at IBM/Globalfoundries (2015–2017). His academic journey includes a Ph.D. in ECE from Georgia Institute of Technology (2015) and a B.S. in EEE from POSTECH, South Korea (2008). Research Interests: Current research focuses on Radar Tracking via Bayesian Estimators , Radar Security , and Wireless Sensing using mmWave and Phase-Arrays . Previous work includes mmWave Phased Array Test Systems , Sub-Nyquist Rate Sampling for Wideband Signals , and High-Speed Signal Testing Methodologies . His work bridges theoretical signal processing with practical hardware implementations, emphasizing cost-effective solutions and real-time applications. Recent Contributions: Recent articles emphasize radar security (e.g., BlueFMCW interference mitigation), mmWave phased array calibration, and embedded DSP education. His 2015 work on sparse signal characterization earned the JETTA-TTTC Best Paper Award. Teaching & Advising: Teaches courses like ECE 398MA (Modern Communication with Python/SDR) and ECE 420 (Embedded DSP Lab). He mentors undergraduate students in senior projects focusing on remote sensing, signal processing, and wireless communication. Labs & Infrastructure: Engages with mmWave radar systems and software-defined radio platforms, leveraging FPGA-based testing modules and Android-based DSP implementations.

Simone Rossiمشاهده پروفایل

استادیار

• Machine Learning
• Deep Learning
• Generative Models
• +۳ مورد دیگر

Simone Rossi is an Assistant Professor in the Data Science department at EURECOM. His research focuses on Bayesian methods, generative models, and deep learning, with particular emphasis on uncertainty quantification, diffusion processes, and scalable probabilistic models. He has contributed to foundational work on functional priors for Bayesian neural networks, conformal prediction for in-context learning, and optimization of diffusion models. Education: Not explicitly mentioned in the provided text. His research interests span machine learning, probabilistic modeling, and theoretical computer science. He explores topics like score-based generative models, continuous-time diffusion processes, and efficient Bayesian inference techniques. Recent work includes analyzing scaling laws for uncertainty in deep learning and improving LLM reasoning capabilities for Text2SQL tasks. His publications reflect contributions to top conferences like NeurIPS, ICML, and AABI, with a focus on both theoretical advancements and practical applications. Notable achievements include a Runner-up Best Paper Award at PAM 2024 for work on data augmentation in traffic classification. Scientific Awards: Runner-up Best Paper Award at PAM 2024 Dr. Rossi collaborates actively with industry and academia, contributing to open-source tools and foundational research in probabilistic deep learning. His work bridges theory and practice, addressing challenges in scalable Bayesian methods and generative model efficiency.

Mark Nelmsمشاهده پروفایل

استاد

• Power Electronics
• Power Systems
• Renewable Energy
• +۳ مورد دیگر

Mark Nelms is the Godbold Professor and Chair of the Department of Electrical and Computer Engineering at Auburn University’s Samuel Ginn College of Engineering. With a Ph.D. in Electrical Engineering from Virginia Tech and master’s/undergraduate degrees from Auburn, his research focuses on power electronics, energy conversion, power systems, and renewable energy integration. He has authored/co-authored seminal works like Basic Engineering Circuit Analysis and contributed extensively to microgrid reliability studies, inverter control methodologies, and fault mitigation in electrical machines. Education Ph.D., Electrical Engineering, Virginia Tech M.S., Electrical Engineering, Auburn University B.S., Electrical Engineering, Auburn University His recent research spans advanced control systems for inverters, microgrid stability analysis, and optimization of renewable energy storage solutions. Publications highlight innovations in proportional-resonant controllers, FPGA-based hardware acceleration, and thermal impact studies of induction motors. Scientific contributions include the IEEE Industry Application Society’s 2019 Distinguished Service Award. Key collaborative efforts involve grid-connected inverter control, pumped storage hydropower integration with wind systems, and adaptive fault-tolerant designs for permanent magnet synchronous machines.

• Nanoelectronic Circuit Design
• Neuromorphic Computing
• Hardware Security
• +۳ مورد دیگر

Garrett S. Rose is a Professor and Department Head in the Department of Electrical Engineering and Computer Science at the University of Tennessee, Knoxville. His research focuses on nanoelectronic circuit design, neuromorphic computing, and hardware security. He holds a PhD in Electrical Engineering from the University of Virginia (2006) and has held roles at AFRL and NYU Polytechnic School of Engineering. His work explores emerging nanoscale devices like memristors for neuromorphic systems and security applications. Education: BS in Computer Engineering (Virginia Tech, 2001), MS and PhD in Electrical Engineering (University of Virginia, 2003/2006). His research areas include memristor-based neuromorphic architectures, hardware security primitives, and nanoelectronic device modeling. He leads the SENECA Research Group, which develops neuromorphic systems for applications like robotics and edge computing. Research highlights include memristive neural networks, PUF-based security systems, and cross-disciplinary projects funded by agencies like AFRL and DARPA. His recent work emphasizes co-design methodologies for neuromorphic hardware and applications such as spiking neural network implementations and sensor-integrated systems. He has advised multiple postdoctoral and graduate researchers and collaborates on grants related to neuromorphic computing and hardware security. His lab develops tools like the DANNA neuromorphic architecture and the RAVENS neuroprocessor, emphasizing real-world applications through hardware-software integration.

Peter Milderمشاهده پروفایل

دانشیار

• Hardware Design
• FPGA Acceleration
• Signal Processing
• +۷ مورد دیگر

Peter Milder is an Associate Professor in the Department of Electrical and Computer Engineering at Stony Brook University. His research focuses on hardware acceleration, FPGA-based systems, and domain-specific compilers for applications in machine learning, signal processing, and networking. He leads projects on automatic hardware generation tools like Argus for CNNs and FFT Gen for signal processing transforms. Education details are not explicitly provided in the text, but his work spans multiple interdisciplinary areas including formal verification (e.g., model checking on FPGAs), wireless edge computing (OPSEL protocol), and high-performance sorting algorithms. He has advised numerous PhD students and collaborates with researchers across academia and industry. Research Highlights: Developed voltage-scaling techniques for DNN accelerators. Created Waverunner, an FPGA-accelerated state machine replication system. Organized IEEE Transactions special issues and NSF-funded projects on edge computing and machine learning hardware. Awards: ACM TODAES Best Paper Award (2014). NSF grants for sparse transformer acceleration and FPGA-based spectrum sensing. Grants & Funding: NSF XPS Program (2015): Cloud FPGA deep learning. NSF ECCS (2020): Sparsity-aware NLP hardware. Lab/Collaborations: Collaborates with Professors Michael Ferdman, Fan Ye, and others on FPGA, edge computing, and embedded systems. His work often bridges hardware design with software frameworks.

Georgios Karakonstantisمشاهده پروفایل

پژوهشگر

• Energy-Efficient Systems
• Approximate Computing
• FPGA/GPU Accelerators
• +۴ مورد دیگر

Dr. Georgios Karakonstantis is a Visiting Scholar at Queen's University Belfast's School of Electronics, Electrical Engineering and Computer Science. He specializes in energy-efficient and dependable systems for embedded devices and data centers, focusing on approximate computing, FPGA/GPU accelerators, and cross-layer design techniques. His work addresses challenges in Edge and Cloud environments through innovations in hardware-software co-design and error resilience. Research Interests: Energy-efficient processors and memories Error-resilient computing architectures Approximate computing for multimedia/ML applications Accelerators in Cloud/Edge ecosystems Machine learning for hardware modeling Awards: Best Paper Award at IEEE DATE 2020 Altera Innovate Design Contest Winner Prize Nominated for IEEE MICRO 2020 Best Paper Advising: Supervised PhD students in areas such as variation-aware processors (Ioannis Tsiokanos), energy-efficient memories (Konstantinos Tovletoglou), and heterogeneous architectures (Umar Ibrahim Minhas). Active in grants including UniServer and EU-funded projects on Edge computing.