جست‌وجوی استاد و پژوهشگر

Jingtong Huمشاهده پروفایل

دانشیار

• Cyber-Physical Systems
• Infrastructure Security
• Non-Volatile Memory Systems
• +۶ مورد دیگر

Jingtong Hu is an Associate Professor at the Swanson School of Engineering, University of Pittsburgh, where he also holds the William Kepler Whiteford Faculty Fellowship. His research focuses on Cyber-Physical Systems and Infrastructure Security, with significant contributions to embedded systems, non-volatile memory architectures, and hardware/software co-design for energy-constrained environments. Dr. Hu received his PhD from the University of Texas at Dallas (2007-2013) and his Bachelor of Engineering from Shandong University (2003-2007). His research spans multiple interdisciplinary areas including energy harvesting systems, non-volatile processors, FPGA acceleration, and machine learning at the edge. His recent publications demonstrate a strong focus on algorithm-hardware co-design, particularly for vision transformers, federated learning, and non-volatile memory systems. His work often addresses the challenges of implementing AI on resource-constrained edge devices, with emphasis on energy efficiency, reliability, and performance optimization. The trend in his publications shows increasing focus on sustainable AI processing, heterogeneous computing architectures, and personalized machine learning for IoT applications. Selected Awards: IEEE Transactions on Computer-Aided Design Donald O. Pederson Best Paper Award (2021) ACM SIGDA Meritorious Service Award (2019) Multiple Best Paper Award nominations at top conferences including DAC, ASP-DAC, and CODES+ISSS Dr. Hu's research has been supported by multiple grants focusing on energy-efficient computing, non-volatile memory systems, and hardware acceleration for machine learning. His collaborative work spans numerous institutions and involves interdisciplinary teams working at the intersection of computer architecture, embedded systems, and artificial intelligence. His publications show extensive collaboration with researchers at the University of Pittsburgh, particularly with Albert K. Jones and Yiyu Shi. His laboratory work focuses on implementing practical systems for energy harvesting powered devices, non-volatile processors, and hardware accelerators for machine learning applications. Current projects appear to emphasize sustainable AI processing at the edge, heterogeneous FPGA acceleration, and personalized federated learning for health monitoring applications.

• Reconfigurable Computing
• Field-Programmable Gate Arrays (FPGA)
• High-Level Synthesis
• +۳ مورد دیگر

Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.

Baker Mohammadمشاهده پروفایل

استاد

• Very-Large-Scale Integration (VLSI)
• Hardware Accelerators for Artificial Intelligence
• Hardware Security
• +۷ مورد دیگر

Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.

• Electrical and Electronic Engineering
• Computer Hardware
• Computer Software
• +۷ مورد دیگر

Professor Peter Y. K. Cheung is a Professor of Digital Systems at Imperial College London, holding dual affiliations within the Department of Electrical and Electronic Engineering and the Dyson School of Design Engineering. His work focuses on reconfigurable systems, FPGA architectures, and high-level synthesis tools. He co-founded one of the UK's leading FPGA research groups with Professor Wayne Luk, addressing challenges in variability mitigation, reliability, and application-specific FPGA deployments. His research spans Field-Programmable Gate Arrays (FPGAs) Reconfigurable computing Neural network acceleration Cryptographic protocols Embedded systems He has pioneered techniques such as logic shrinkage for FPGA-based neural networks and developed frameworks like LUTNet for efficient inference. His contributions also include fault-tolerant FPGA designs and methodologies for distributed computation protocols. Key collaborations include work with the Department of Computing on FPGA-based AI acceleration and cybersecurity applications. His recent work explores edge computing, secure decentralized systems, and pandemic modeling using adaptive control strategies. Notable projects include the DSCS protocol for secure distributed computation, acceleration of gravitational wave detection algorithms, and energy-efficient CNN implementations. His research bridges hardware-software co-design with real-world applications in healthcare, finance, and aerospace.

Jing Liمشاهده پروفایل

دانشیار

• Computer Architecture
• Compiler Design
• Distributed Systems
• +۷ مورد دیگر

Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.

Yogananda Isukapalliمشاهده پروفایل

استاد آموزشی

• Signal Processing
• Computer Engineering
• Digital Design
• +۵ مورد دیگر

Yogananda Isukapalli is a Teaching Professor and Vice Chair in the Computer Engineering Program at the Electrical and Computer Engineering Department , University of California, Santa Barbara . He joined the faculty in Winter 2017 after a career as a staff scientist at Broadcom (2010–2017), where he designed Wi-Fi chips (11n/11ac/11ax) and worked on underwater wireless communication models during a postdoctoral stint at Scripps Institution of Oceanography (2009–2010). His PhD in Communication Theory and Systems from UC San Diego (2009) forms the basis of his expertise in wireless systems and digital design .

Michael Ferdmanمشاهده پروفایل

دانشیار

• Computer Architecture
• Operating Systems
• Machine Learning
• +۷ مورد دیگر

Michael Ferdman is an Associate Professor in the Department of Computer Science at Stony Brook University, where he leads research in computer architecture and systems. His office is located in Room 343 at Stony Brook, NY 11794-2424, and he can be contacted via phone (631-632-8449) or email. Ferdman directs the Computer Architecture and Systems Laboratory (compas.cs.stonybrook.edu), focusing on next-generation server infrastructure. Ferdman's research spans the entire computing stack with emphasis on: FPGA integration for server environments (Intel HARP, Microsoft Catapult) Machine learning accelerators for convolutional neural networks Server systems optimization in the post-Moore era Network processing and software-defined networking Programming models for emerging memory technologies (HBM, 3D XPoint) Reconfigurable hardware and high-level synthesis His work addresses both performance and security challenges in modern computing infrastructure. Analysis of his 15 most recent publications (2022-2025) reveals consistent focus on: Hardware acceleration techniques (FPGAs, specialized processors) Memory hierarchy optimization and cache management Security vulnerabilities in web applications and systems Post-Moore computing architectures Parallel processing and distributed systems His research shows strong emphasis on practical implementations bridging hardware and software layers. Awards recognizing his contributions include: Graduate Teaching Award (2014) Best Paper Award at ASPLOS XVII Best Paper Finalist at HPCA XVII Three IEEE Micro Top Picks selections (2009, 2012) He teaches advanced courses including CSE 502, CSE 602, and CSE 506 at Stony Brook University.

• Global Navigation Satellite Systems (GNSS)
• Avionics Systems
• Wireless Communication
• +۷ مورد دیگر

René Jr Landry is a full Professor in the Department of Electrical Engineering at École de technologie supérieure (ETS), Université du Québec, specializing in Global Navigation Satellite Systems (GNSS), avionics, and wireless communication technologies. His academic journey includes a B.Ing. from Polytechnique Montréal, M.Sc. from University of Surrey (UK), and Ph.D. from SupAréo in Toulouse. He maintains active research leadership through two key laboratories: LASSENA (Laboratory of Space Technologies, Embedded Systems, Navigation and Avionics) and LACIME (Communications and Microelectronic Integration Laboratory). His research spans critical aerospace navigation domains including GNSS signal processing, inertial navigation systems, software-defined radio for avionics, radio frequency interference mitigation, and indoor positioning technologies. Landry's work addresses real-world challenges in satellite navigation robustness, precision positioning in urban/denied environments, and next-generation avionic system security. His current projects focus on blockchain-enhanced IoT security, AI-driven GNSS disruption analysis, and adaptive RF front-ends for multi-band avionics applications. Analysis of his recent publications reveals strong emphasis on resilient positioning systems through multi-constellation integration (particularly Iridium-NEXT), blockchain applications for navigation security, and explainable AI techniques for GNSS signal quality assessment. His work increasingly bridges traditional navigation engineering with cutting-edge security and machine learning paradigms. 2014 Prix d'excellence du c.a. pour les services à la collectivité Landry has supervised over 100 graduate students across doctoral, master's, and research projects since 2005, with current supervision extending through Summer 2025. His research funding supports multiple industry partnerships focused on avionics certification, software-defined radio implementations, and next-generation navigation systems. The LASSENA laboratory under his leadership develops certified avionic products from open-source SDR platforms and advances multi-sensor fusion techniques for challenging navigation environments. His research infrastructure includes specialized facilities for GNSS signal simulation, avionics hardware testing, and multi-sensor integration. Current work emphasizes flight-tested validation of RF front-end technologies, blockchain-secured navigation data, and real-time interference mitigation systems for aviation applications.

Jason Dahlstromمشاهده پروفایل

استادیار مدعو

• Embedded Systems
• Computer Architecture
• Engineering Education
• +۳ مورد دیگر

Jason Dahlstrom is an Adjunct Assistant Professor of Engineering at Dartmouth College's Thayer School of Engineering and Owner of Web Sensing LLC. His research focuses on embedded systems security, computer architecture optimization, and engineering education innovations. He holds a BS in computer engineering (University of New Hampshire, 2006), MS in biomedical engineering (Dartmouth, 2008), and PhD in embedded system security (Dartmouth, 2015). His work emphasizes cybersecurity for critical infrastructure, particularly in vehicle systems and military communication networks. Key contributions include real-time binary analysis frameworks, FPGA-integrated security monitors, and tactical network interface controllers. He has authored patents related to data security appliances and distributed sensing systems. Recent publications explore vehicle system hardening, cross-domain container security, and hardware-assisted monitoring. His research bridges theoretical computer architecture with practical embedded system implementations, addressing modern threats in connected devices and defense applications.

Luca Carloniمشاهده پروفایل

استاد

• Computer Science
• Embedded Systems
• Hardware Design
• +۶ مورد دیگر

Luca Carloni is a Professor of Computer Science and Department Chair at Columbia University's Columbia Engineering. He leads the System-Level Design Group, focusing on heterogeneous system-on-chip (SoC) architectures, networks-on-chip (NoC), and embedded systems. Carloni holds a Laurea Summa Cum Laude in Electronics Engineering from the University of Bologna and a PhD in Electrical Engineering and Computer Sciences from UC Berkeley. His work emphasizes specialized hardware design, energy-efficient computing, and FPGA-based prototyping. Research interests include system-level design methodologies for SoCs, embedded accelerators, and quantum computing hardware. He has pioneered frameworks like Embedded Scalable Platforms (ESP) and tools like MosaicSim for rapid SoC prototyping. Carloni has received numerous awards, including the NSF CAREER Award (2006), IEEE Fellow (2017), and multiple best paper awards at DATE and CloudCom conferences. He has served on editorial boards of IEEE Transactions on CAD and ACM Transactions on Embedded Computing , and chaired key conferences like EMSOFT and ESWeek. His research addresses challenges in heterogeneous architectures, power management, and the intersection of machine learning with embedded systems. Current projects explore quantum control systems, brain-computer interfaces, and energy-efficient datacenter computing.

Lin Zhongمشاهده پروفایل

استاد

• Computer Science
• Quantum Computing
• Operating Systems
• +۳ مورد دیگر

Lin Zhong is the Joseph C. Tsai Professor of Computer Science at Yale University, leading the Efficient Computing Lab. He holds a Ph.D. from Princeton University and M.S./B.S. degrees from Tsinghua University. Previously, he served at Rice University from 2005 to 2019. His research focuses on optimizing computing efficiency, quantum error correction, operating systems, and mobile systems. Education: Ph.D., Princeton University M.S., Tsinghua University B.S., Tsinghua University Research Interests: His work spans quantum computing (e.g., decoding algorithms for surface codes), operating systems (safety, correctness, and lightweight kernels), and mobile/networking systems (massive MIMO, energy-efficient designs). Recent trends include integrating large language models (LLMs) into robotics and securing cloud-based AI workflows. Awards: NSF CAREER Award ACM SIGMOBILE RockStar (2014) and Test of Time (2022) Fellowships from IEEE and ACM Best Paper Awards at ACM MobileHCI, IEEE PerCom, ACM MobiSys, and more Lab & Teams: His Efficient Computing Lab explores systems for quantum error correction (e.g., FPGA-based decoders), secure embedded systems, and LLM-driven robotics. Projects include TimelyLLM (real-time LLM serving) and Blindfold (confidential memory management).

Yizhou Sunمشاهده پروفایل

استاد

• Machine Learning
• Artificial Intelligence
• Graph Neural Networks
• +۳ مورد دیگر

Professor Yizhou Sun is affiliated with the University of California Los Angeles (UCLA) and the Henry Samueli School of Engineering and Applied Science . Her academic work focuses on Machine Learning , Artificial Intelligence , and Graph Neural Networks within the Computer Science department. Her research spans High-Level Synthesis , Causal Inference , and Computational Biology , with recent publications addressing neural network compression, language model safety, and dynamical system modeling. The trends in her recent 2025 and 2024 publications emphasize Deep Learning , Graph Theory , and Language Model Optimization , reflecting interdisciplinary applications in Biomedical Data , Hardware Design , and Physical Simulation .

• Optical fiber communication
• Space-division multiplexing (SDM)
• Wavelength-division multiplexing (WDM)
• +۵ مورد دیگر

Itsuro Morita is Professor in the School of Fundamental Science and Engineering, Faculty of Science and Engineering, Waseda University, Tokyo. Before joining Waseda in 2022 he spent 23 years at KDDI R&D Laboratories, advancing from researcher to executive research fellow, and has been a visiting researcher at Stanford University. He is an IEEE Fellow and IEICE Fellow recognized for pioneering large-capacity, long-haul optical transmission systems. Education: 2004 – 2005 Tokyo Institute of Technology, Graduate School of Science & Engineering, Department of Electrical and Electronic Engineering (Doctoral coursework) 1990 – 1992 Tokyo Institute of Technology, Graduate School of Science & Engineering, Department of Physical Electronics (M.E.) 1986 – 1990 Tokyo Institute of Technology, School of Engineering (B.E.) Research Interests: Morita’s work sits at the intersection of optical fiber communication and software-defined networking. He explores ultra-high-capacity transmission via space-division multiplexing (multi-core/few-mode fibers), real-time MIMO digital signal processing for modal crosstalk mitigation, and SDN/NFV orchestration of disaggregated optical networks. Additional interests include quality-of-transmission estimation using machine learning, telemetry-enabled control planes (gRPC/gNMI), and metro-embedded edge/cloud architectures for IoT services. Publication Trends: Recent articles emphasize two converging themes: (i) petabit-per-second SDM/WDM experiments using novel fiber geometries and real-time DSP, and (ii) cloud-native SDN control frameworks that integrate machine-learning-based QoT prediction, YANG/NETCONF modeling, and open APIs (TAPI/OpenConfig) for multi-domain, partially disaggregated networks. These works collectively push both the physical capacity frontier and the agility of next-generation optical infrastructure. Scientific Awards: C&C Prize 2024 (NEC C&C Foundation) – contributions to WDM optical submarine cable systems IEICE Achievement Award 2021 – pioneering research on 10-Pbit/s ultra-large-capacity SDM transmission Telecom System Technology Award 2021 – 10.16-Pbit/s dense SDM/WDM transmission record IEEE Fellow (2021) – contributions to large-capacity high-speed transmission systems IEICE Fellow (2020) – research on trans-oceanic high-speed optical signal transmission Ichimura Industrial Award – Contribution Prize 2018 – development of terabit-class submarine cable systems Maejima Hisoka Award 2012 – proposal and demonstration of distributed-control soliton communication Minister of Economy, Trade and Industry Award for Advanced Technology 2006 – 160 Gbit/s ultra-high-speed optical transmission technology Advising & Grants: At Waseda University Morita advises graduate students on experimental photonic networking and leads externally funded projects on petabit SDM transmission and SDN orchestration. While specific grant numbers are not disclosed, his continuous industry-university collaborative testbeds (with KDDI, CTTC, and others) indicate substantial competitive funding. Labs & Teams: He heads the Optical Space-Division-Multiplexing Laboratory at Waseda, maintaining joint experimental facilities with KDDI Research and international partners (e.g., CTTC, Spain). The group operates real-time coherent MIMO testbeds, multi-domain SDN controllers, and fiber-level SDM prototypes capable of petabit-per-second demonstrations.

Lisa Willsمشاهده پروفایل

استادیار

• Computer Architecture
• Hardware Acceleration
• Hardware-Software Co-Design
• +۵ مورد دیگر

Lisa Wills serves as Assistant Professor of Computer Science at Duke University's Trinity College of Arts & Sciences and holds a joint appointment in Electrical and Computer Engineering at the Pratt School of Engineering since 2019. Her research bridges computer architecture and domain-specific applications, with a focus on hardware acceleration for computationally intensive fields. Dr. Wills earned her Ph.D. from Columbia University in 2014. Her academic journey reflects a deep commitment to advancing hardware-software co-design methodologies for real-world computational challenges. Her research centers on developing efficient hardware accelerators for big data analytics, particularly in genomics, graph processing, and database systems. She pioneers frameworks that simplify accelerator deployment while tackling critical bottlenecks in genomic data analysis, protein structure prediction, and privacy-preserving computing. Current work focuses on hardware-aware machine learning systems and energy-efficient architectures for emerging AI applications. Analysis of her publication record reveals a clear trajectory: from foundational work in database processing units (2014-2016) to specialized genomic accelerators (2019-2021), then evolving toward ML-enhanced design automation (2022-2023) and cutting-edge architectural abstractions (2024-2025). Her research consistently targets the intersection of hardware efficiency and domain-specific computational demands, with increasing emphasis on AI/ML workloads. Google ML and Systems Junior Faculty Award (2025) Dr. Wills actively mentors doctoral students including Chris Kjellqvist (lead architect of Beethoven accelerator framework), Mason Ma (PyTFHE FHE framework), and Mansi Choudhary (COCOSSim accelerator simulator). Her research is supported by significant grants including the NSF AI Institute: Athena ($20M, 2021-2027), Meta-funded ProSE accelerator project (2023-2026), and NSF CAREER award (2021-2026), totaling over $25M in active funding. She directs the APEX Lab (Application-driven Programmable Efficient Accelerated Systems), which develops open-source frameworks like Beethoven for FPGA/ASIC accelerator deployment and focuses on lowering barriers for non-hardware researchers to leverage custom acceleration in genomics, AI, and big data applications.

Lisa Wu Willsمشاهده پروفایل

استادیار

• Computer Architecture
• Hardware-Software Co-design
• Hardware Accelerators
• +۶ مورد دیگر

Lisa Wu Wills is an Assistant Professor in the Department of Computer Science and Electrical and Computer Engineering at Duke University, leading the APEX Lab (Application-driven Programmable Efficient Accelerated Systems Lab). Her research focuses on hardware acceleration for big data analytics in genomics, graphs, and databases to advance healthcare and natural sciences. Education: Ph.D. in Computer Science, Columbia University, 2014 Research Interests: Dr. Wills pioneers computer architecture and hardware-software co-design to create efficient accelerators for emerging applications. Her work targets genomics , graph analytics , and database systems , emphasizing simplified hardware deployment and energy efficiency for scientific breakthroughs in healthcare and AI. Publication Trends: Her 2022-2025 publications reveal a strong focus on open-source frameworks (Beethoven, PyTFHE) for accelerator development, hardware acceleration in privacy-preserving computing, and optimization for large language models. Key themes include transfer learning for EDA, domain-specific architectures for genomics, and energy-efficient image processing. Scientific Awards: Google ML and Systems Junior Faculty Award (2025) Advising and Grants: Dr. Wills mentors three PhD students: Chris Kjellqvist (Beethoven framework architect), Mason Ma (PyTFHE lead for FHE applications), and Mansi Choudhary (COCOSSim simulator creator). Her 2025 Google award funds research on accelerating vector databases and retrieval-augmented generation for LLMs. Labs and Teams: She directs the APEX Lab at Duke, developing tools like Beethoven (open-source accelerator composer) and PyTFHE for hardware-software integration, enabling domain scientists to leverage custom acceleration with minimal hardware expertise.