Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.
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Subhasish Mitra is the William E. Ayer Professor of Electrical Engineering and Computer Science at Stanford University, holding dual appointments in both departments. He leads the Stanford Robust Systems Group and serves on the leadership team of the Microelectronics Commons AI Hardware Hub under the US CHIPS and Science Act. His research spans Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences, with breakthroughs in X-Compact test compression, carbon nanotube computing, and 3D integration. He has held international roles like the Carnot Chair at CEA-LETI and Visiting Professorships globally. Education & Honors: Recipient of over 40 awards including the IEEE Computer Society’s Harry H. Goode Memorial Award, ACM/IEEE’s A. Richard Newton Technical Impact Award, and the Intel Achievement Award. He earned top academic accolades from IIT Kharagpur and Jadavpur University, and is a Fellow of ACM and IEEE. Research Impact: Pioneered first-of-their-kind systems like the carbon nanotube computer and monolithic 3D integration. His work on robust computing techniques like QED validation and X-Compact compression has industry-wide adoption, saving billions in manufacturing costs. Collaborates with industry leaders like Intel, Google, and Samsung. Publications & Grants: Over 400 publications, including award-winning papers in DAC, ISSCC, and IEEE journals. Leads grants from NSF, DoE, and industry partnerships. His lab explores cutting-edge topics like neuromorphic computing, 3D thermal scaffolding, and AI hardware acceleration. Administration & Outreach: Serves as Associate Chair (Faculty Affairs) for Stanford’s Computer Science Department. Recognized by students for mentorship, and frequently invited to global forums like the World Economic Forum and National Academy of Engineering.
Geng Yuanمشاهده پروفایل
استادیار
Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.
André DeHon is the Oliver C. Boileau Jr. and Nan Eleze Boileau Professor of Electrical Engineering at the University of Pennsylvania, with affiliations in the Electrical and Systems Engineering (ESE) and Computer and Information Science (CIS) departments. He founded the Penn Computer Engineering (CMPE) program and directs the DARPA-sponsored CyberSavvy Security Center. His research spans reconfigurable computing, FPGA architecture, interconnect design, hardware security, and energy efficiency, with a focus on adapting to fabrication imperfections and runtime variability. His work explores programmable substrates (e.g., CMOS VLSI, molecular electronics) and algorithmic mappings to create resilient, efficient systems. Current projects include runtime feedback mechanisms (REFINE), partial reconfiguration (ExHiPR), and security frameworks like SCALPEL and μSCOPE. Recent publications highlight advancements in FPGA compilation (PLD, HiPR), security (SCALPEL, μSCOPE), and interconnect optimization (Asymmetry in NoC). These studies intersect computer architecture, security, and embedded systems. Scientific awards and recognitions: 2023 IEEE Fellow 2020 IEEE Mary Kenneth Keller Teaching Award 2018 ACM Fellow TCFPGA Hall of Fame (2019) Best Paper at ICFPT 2015 Academic leadership: He chairs the ACM/SIGDA Technical Committee on FPGAs and Reconfigurable Computing, previously held faculty roles at Caltech (1999–2006), and was a postdoc at UC Berkeley (1996–1999). Education includes MIT SB (1990), SM (1993), and PhD (1996) in Electrical Engineering and Computer Science.
Morteza Fayaziمشاهده پروفایل
استادیار
Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.
Debjit Palمشاهده پروفایل
پژوهشگر ارشد
Debjit Pal is a Post-Doctoral Associate at the School of Electrical and Computer Engineering, Cornell University, and a member of the Computer Systems Laboratory. His research focuses on machine learning techniques for hardware verification, SoC validation, and FPGA optimization. Education: Ph.D. in Computer Engineering (University of Illinois at Urbana-Champaign, 2019) M.S. in Computer Science (IIT Kharagpur, 2012) B.E. in Electronics Engineering (Jadavpur University, 2008) Research Interests: Machine Learning for Electronic Design Automation (EDA) System-on-Chip (SoC) Verification Edge Intelligence as a Service Compiler Optimizations for Reconfigurable and High-Performance Computing Scientific Awards: IEEE CEDA Student Research Award (2016) Best Paper Nomination (ICCAD 2015, DAC 2018, ASP-DAC 2019) E. J. McCluskey Best Doctoral Thesis Competition Semi-Finalist (2020) Travel Grants for ICCAD/DAC/ASPDAC (2018-2019) Professional Roles: Technical Program Committee Member (DAC, VLSID), Reviewer (IEEE TVLSI, DATE, ICCAD). Collaborates with researchers like Zhiru Zhang and Shobha Vasudevan.
Ronald G. Dreslinski is the Morris Wellman Faculty Development Assistant Professor in the Department of Electrical Engineering and Computer Science at the University of Michigan, within the College of Engineering. He leads the Computer Engineering Lab (CEL) and directs multiple government-funded research initiatives. His research focuses on Computer Architecture , Hardware Design Automation , and Electronic Design Automation (EDA) , specializing in autonomous system-on-chip synthesis and reconfigurable computing. His work aims to democratize hardware design by eliminating barriers of cost, expertise, and uncertainty through tools enabling no-human-in-the-loop implementation. Dr. Dreslinski manages significant funding from defense and science agencies. Current projects include: DARPA DSSoC (DASH) DARPA Space-BACN (Cochon) DARPA Prowess (Dr. Dash) IARPA Agile (PANDO) NSF Fuse (Regaining the Edge) Past projects encompass: DARPA CRAFT (CERTUS) DARPA PERFECT DARPA SDH (Transmuter) DARPA IDEA (FASoC, OpenROAD) NASA/AFRL (HPSC) He drives the OpenROAD project toward 24-hour autonomous chip design, with industrial adoption by Intel and IHP for shuttle services. His lab develops open-source tools like FASoC for synthesizable analog-digital SoC composition, advancing portability and correctness-by-construction methodologies.
Callie Haoمشاهده پروفایل
استادیار
Callie Hao is an Assistant Professor in the Department of Electrical and Computer Engineering at the Georgia Institute of Technology since 2021, holding the ON Semiconductor Junior Professorship. Her research bridges hardware efficiency and algorithmic innovation with significant industry and federal recognition. Education: Ph.D. in Electrical Engineering, Waseda University (2017) M.S. and B.S. in Computer Science and Engineering, Shanghai Jiao Tong University Research Focus: Dr. Hao pioneers software/hardware co-design for edge AI, specializing in hardware-efficient machine learning algorithms, FPGA-based reconfigurable computing, graph neural networks, and electronic design automation (EDA). Her work emphasizes neural architecture search, high-level synthesis optimization, and memory-efficient systems for embedded and IoT applications, driven by the philosophy that "1 + 1 > 2" for transformative efficiency gains. Publication Impact: Her 15 most recent publications (2023-2026) reveal a strategic shift toward machine learning-driven EDA tools, with 60% focused on high-level synthesis frameworks and 40% on graph neural network acceleration. Key trends include simulation speed breakthroughs (LightningSim), automated accelerator generation (GNNBuilder), and cryptographic hardware innovations (Cryptonite), predominantly published in top-tier venues like MICRO, ICCAD, and DAC. Awards & Recognition: NSF CAREER Award (2024) and Intel Rising Star Faculty Award (2023) Best Paper Awards at MLCAD 2024 and GLSVLSI 2021 ON Semiconductor Junior Professorship (2025) and Sutterfield Family Early Career Professorship (2022) DAC-SDC competition championships (2018-2020) Mentorship & Funding: Dr. Hao advises 8+ Ph.D. students in the Sharc Lab, with Rishov Sarkar winning the Oscar P. Cleaver Award and Qualcomm Innovation Fellowship. Her research is funded by DARPA (2021) for ultra-light video intelligence systems and supported by industry awards from Amazon and Sony. She actively serves on program committees for DAC, ICCAD, and DATE conferences. Lab Leadership: As director of the Sharc Lab (Software/Hardware Co-design lab), she cultivates interdisciplinary research at the intersection of FPGA design, machine learning, and EDA, requiring expertise in Verilog/HLS, GNNs, and compiler technologies while maintaining strict focus on real-world hardware implementation.
Prof. Dan Jiao is the Synopsys Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School. She leads the Rapid-Heterogeneous Integration (Rapid-HI) Design Institute and serves as Editor-in-Chief of the IEEE Journal on Multiscale and Multiphysics Computational Techniques. Her research focuses on computational electromagnetics, multiphysics modeling, and AI-driven design automation for advanced integrated circuits and quantum systems. She has held academic positions since 2005, progressing from Assistant to Full Professor, and has extensive industry experience at Intel Corporation (2001–2005). Education: PhD in Electrical Engineering, University of Illinois at Urbana-Champaign (2001) Senior Staff Engineer at Intel Corporation (2001–2005) Research Interests: Fast numerical methods for large-scale electromagnetic analysis AI/ML integration in design automation (EDA/MDA) Quantum circuits and spin qubit systems Heterogeneous integration and advanced packaging Multiphysics co-simulation for nano-scale devices Signal/power integrity in high-speed systems Key Projects: Leads the NSTC AIDRFIC program (first NSTC R&D Jump Start project), the DARPA NGMM Rapid-HI Design Institute, and the GENIE-RFIC generative design tool initiative. Also directs the Consortium for Electromagnetic Science and Technology. Awards & Honors: 2022 ACES Computational Electromagnetics Award IEEE Fellow (2016) Intel Outstanding Researcher Award (2019) MTT-S Distinguished Microwave Lecturer (2020–2023) 2013 Schelkunoff Prize Paper Award Advising & Grants: Advised over 30 PhD/master's students and led projects funded by NSF, DARPA, Intel, SRC, and industry partnerships. Key grants include NSF CAREER (2008), ONR Young Investigator (2006), and multiple industry-sponsored initiatives. Labs & Teams: Rapid-HI Design Institute (DARPA NGMM) Quantum device co-design group Multiphysics modeling team
Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.
Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.
Martin D F Wong serves as the Edward C. Jordan Professor of Electrical and Computer Engineering and Executive Associate Dean for the College of Engineering at the University of Illinois at Urbana-Champaign. He is affiliated with the Coordinated Science Laboratory and has been instrumental in advancing electronic design automation research. His educational background includes: B.Sc. in Mathematics, University of Toronto (1979) MS in Mathematics, University of Illinois at Urbana-Champaign (1981) Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (1987) Wong's research centers on combinatorial optimization and algorithm design for VLSI systems, with particular expertise in lithography-aware physical design, field-programmable systems, and electronic packaging. His work bridges theoretical algorithms with practical semiconductor manufacturing challenges as feature sizes shrink below 20 nanometers. Current research focuses on integrating chip design with next-generation lithography technologies including triple-patterning, self-aligned double patterning, directed self-assembly, and extreme ultraviolet processes. His publication record shows consistent contributions to electronic design automation, with emphasis on manufacturing-aware physical design algorithms and circuit optimization techniques. Recent work addresses the critical interface between circuit layout and lithography processes as semiconductor technology advances to 14nm and beyond. Scientific recognition includes: Fellow of IEEE and ACM 2000 IEEE Donald O. Peterson Best Paper Award Multiple Best Paper Awards at DAC, ICCD, and ICCAD conferences IBM Faculty Awards (2000, 2004) NSF Research Initiation Award Wong has secured significant research funding including a $450,000 NSF grant for lithography-aware physical design and has supervised over 49 PhD students. His work continues the legacy of integrated circuit innovation at Illinois, building on foundational contributions like Jack Kilby's integrated circuit invention. Current research initiatives focus on optimizing chip design for next-generation manufacturing processes where optical interference challenges require co-design of layout and fabrication. He leads research within the Coordinated Science Laboratory, focusing on electronic design automation algorithms that address the growing complexity of semiconductor manufacturing at nanometer scales.
Muhammad Rashedمشاهده پروفایل
استادیار
Dr. Muhammad Rashed is an Assistant Professor in the Department of Computer Science and Engineering at the University of Texas at Arlington, within the College of Engineering. He holds a Ph.D. in Computer Engineering from the University of Central Florida (2024) and a B.S. in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology (2015). Ph.D. : Computer Engineering, University of Central Florida, 2024 B.S. : Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, 2015 His research focuses on electronic design automation (EDA), in-memory computing, AI acceleration, and sustainable computing. He explores novel computing paradigms to overcome the limitations of traditional architectures, particularly in data-intensive applications such as AI and scientific computing. His work emphasizes hardware-software co-design and leveraging emerging non-volatile memories for energy-efficient processing. The 15 most recent publications highlight a consistent focus on in-memory computing, particularly in path-based and flow-based architectures, logic synthesis, and AI acceleration. Key themes include optimization, fault tolerance, verification, and the use of advanced data structures like sentential decision diagrams. His work is published in top-tier venues such as DAC, ICCAD, ASP-DAC, and IEEE/ACM journals. Scientific Awards: UTA CARES Grant for OER Creation Research Experiences for Undergraduates (REU) Grant Alireza Seyedi Doctoral Research Innovation Endowed Scholarship David T. & Jane M. Donaldson Memorial Scholarship IEEE/ACM William J. McCalla ICCAD Best Paper Award Nomination Best Research Video Award, Design Automation Conference (DAC) Dr. Rashed advises several graduate and undergraduate students in the NextGen Computing Lab and is involved in research grants including the UTA CARES Grant and REU funding. He actively contributes to academic service through roles such as conference TPC member, journal reviewer (e.g., IEEE TCAD, ACM TODAES), and committee participation in the department and college. His lab, the NextGen Computing Lab, is dedicated to building scalable, energy-efficient computing systems for next-generation AI and scientific workloads, aligning with national initiatives in advanced computing.
Austin Rovinskiمشاهده پروفایل
استادیار
Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.
Ningyuan Caoمشاهده پروفایل
استادیار
Ningyuan Cao is an Assistant Professor in the Department of Electrical Engineering at the University of Notre Dame, College of Engineering. He leads the Circuit and System Intelligence Research Lab , focusing on the intersection of advanced hardware design and real-time/low-power machine learning applications. Education : Ph.D., Electrical and Electronics Engineering, Georgia Institute of Technology (2020) M.S., Electrical Engineering, Columbia University (2015) B.S., Electrical and Electronics Engineering, Shanghai Jiao Tong University (2013) His research investigates custom analog/mixed-signal circuits , digital architecture , and micro-system design for machine learning acceleration, distributed intelligence, and data-driven IC design automation. Key application domains include Internet-of-Everything, tactile internet, and mixed reality systems. Recent publications highlight work on Bayesian neural networks , privacy-preserving bio-signal encoders , transformer-based surrogate models , and compute-in-memory architectures . Technical themes span neuromorphic computing, uncertainty quantification, and hardware security.