Martin D F Wong

Martin D F Wong serves as the Edward C. Jordan Professor of Electrical and Computer Engineering and Executive Associate Dean for the College of Engineering at the University of Illinois at Urbana-Champaign. He is affiliated with the Coordinated Science Laboratory and has been instrumental in advancing electronic design automation research.

His educational background includes:

• B.Sc. in Mathematics, University of Toronto (1979)
• MS in Mathematics, University of Illinois at Urbana-Champaign (1981)
• Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (1987)

Wong's research centers on combinatorial optimization and algorithm design for VLSI systems, with particular expertise in lithography-aware physical design, field-programmable systems, and electronic packaging. His work bridges theoretical algorithms with practical semiconductor manufacturing challenges as feature sizes shrink below 20 nanometers. Current research focuses on integrating chip design with next-generation lithography technologies including triple-patterning, self-aligned double patterning, directed self-assembly, and extreme ultraviolet processes.

His publication record shows consistent contributions to electronic design automation, with emphasis on manufacturing-aware physical design algorithms and circuit optimization techniques. Recent work addresses the critical interface between circuit layout and lithography processes as semiconductor technology advances to 14nm and beyond.

Scientific recognition includes:

• Fellow of IEEE and ACM
• 2000 IEEE Donald O. Peterson Best Paper Award
• Multiple Best Paper Awards at DAC, ICCD, and ICCAD conferences
• IBM Faculty Awards (2000, 2004)
• NSF Research Initiation Award

Wong has secured significant research funding including a $450,000 NSF grant for lithography-aware physical design and has supervised over 49 PhD students. His work continues the legacy of integrated circuit innovation at Illinois, building on foundational contributions like Jack Kilby's integrated circuit invention. Current research initiatives focus on optimizing chip design for next-generation manufacturing processes where optical interference challenges require co-design of layout and fabrication.

He leads research within the Coordinated Science Laboratory, focusing on electronic design automation algorithms that address the growing complexity of semiconductor manufacturing at nanometer scales.