جستجوی استاد راهنمای دانشگاهی

Sandip Kunduمشاهده پروفایل

استاد

• Hardware Security
• VLSI Design
• CAD Algorithms
• +۷ مورد دیگر

Sandip Kundu is a Professor of Electrical and Computer Engineering at the University of Massachusetts Amherst since 2005. Prior roles include Senior Researcher at Intel (1997–2005) and IBM Research (1988–1997). He holds a Ph.D. from the University of Iowa (1988) and a B.Tech from IIT Kharagpur (1984). Research Interests: Focuses on hardware security, VLSI design, CAD algorithms, microarchitecture, and neural processing. Notable contributions include work on physically unclonable functions (PUF), blockchain-based IC traceability, and securing embedded systems against adversarial attacks. Key Activities: Served as Associate Editor for multiple IEEE journals and held visiting professorships at institutions like University of Freiburg (Germany), Kyushu Institute of Technology (Japan), and Tsinghua University (China). Awarded IEEE Fellow and JSPS Invitational Fellowships. Awards: Includes five best paper awards, Intel’s Development Leadership Pioneer Award, IBM’s Outstanding Technical Achievement Award, and recognition as a Distinguished Visitor by IEEE Computer Society. Grants & Labs: Active in NSF-funded research and leads the Advanced VLSI Design and Test Group, exploring secure hardware design, neuromorphic computing, and resilient architectures for edge devices.

Martin Elsmanمشاهده پروفایل

استاد

• Programming Languages
• Theory of Computation
• Functional Programming
• +۵ مورد دیگر

Martin Elsman is a full-time Professor in the Programming Languages and Theory of Computation section at the Department of Computer Science, University of Copenhagen (DIKU). He serves as head of the PLTC section and head of studies for the BSc education in Computer Science and Economics. Elsman is also an active maintainer of several software tools including the MLKit and SMLtoJs. Joined DIKU in 2012 after 4 years at SimCorp (2008-2012) and previous Associate Professorship at IT University of Copenhagen (2003-2008). Co-developer of Futhark, TAIL APL compiler, SMLtoJs, and SMLserver. Education: M.Sc. in Engineering, Technical University of Denmark Ph.D. in Computer Science, University of Copenhagen (DIKU), supervised by Mads Tofte. Research Interests: Elsman works on programming language design and implementation, with a focus on functional programming, module systems, domain-specific languages for financial contracts, region-based memory management, compilation techniques for parallelism, program optimization, and static type systems. His work spans both theoretical and applied domains, including blockchain-based financial contract execution, web technology, and GPU programming using functional languages. Publication Trends: His recent articles focus on functional programming, array programming, parallelism, and memory management. Topics include region inference, type systems for data-parallelism, program optimization techniques, and domain-specific compilation for financial and quantum computing. He frequently collaborates with Troels Henriksen and others on tools like Futhark and MLKit.

Oskar Mencerمشاهده پروفایل

استاد

• Numerical methods and simulations
• Imaging
• Discretization of space, time and value
• +۷ مورد دیگر

Oskar Mencer is a Professor in the Department of Computing at Imperial College London , where he has been a member of academic staff since 2000. He was also a Consulting Professor at Center for Computational Earth and Environmental Science , Stanford University (2009-2010). His research focuses on Multiscale Dataflow Computing , exploring the interaction of hardware and software systems through domain-specific representations, parallel programming, VLSI design, and compiler methodologies. He has contributed to fields including high-performance computing, FPGA optimization, and computational finance. Dr. Mencer's work has been recognized with a Special Award from Com.sult (2012), Imperial College Research Excellence Award (2007), and a Top EPSRC Advanced Fellowship (2001). He has received multiple best paper awards, including at ICFPT'08 and ASAP 2008, and his 2000 paper on stream architectures was recognized as historically significant in 2015. His publications demonstrate a strong emphasis on FPGA acceleration , custom architectures , and parallel processing across geophysics, finance, and neuroscience applications. Special Award for Dataflow Innovation (2012) Best Paper Award - ICFPT'08 Best Paper Award - ASAP 2008 He has served on technical committees for conferences such as FPL , DATE , and FPT , and leads the Computer Architecture Research Group (currently inactive).

• Trustworthy computing
• Energy harvesting
• Intelligent system design
• +۷ مورد دیگر

Youhua Shi is a full Professor in the Faculty of Science and Engineering at Waseda University, Japan. He obtained his Doctor of Engineering from Waseda in 2005 and is an active member of IEICE, IPSJ, IEEE, and two Japanese academic societies. His research portfolio integrates trustworthy computing, hardware security of AI accelerators, energy-harvesting interface circuits for triboelectric nanogenerators, and low-power VLSI design-for-test methodologies. Education: Doctor of Engineering, Waseda University (2005) Graduate studies, Waseda University, Division of Engineering (completed 2005) Research Interests: Prof. Shi pursues trustworthy and secure silicon systems, spanning hardware Trojans in automated AI-accelerator flows, radiation-hardened latch design for soft-error resilience, and power-efficient CNN accelerators exploiting zero-gating and data-reuse techniques. Parallel work targets energy-autonomous IoT through advanced interface circuits for triboelectric nanogenerators, achieving record energy-per-cycle beyond the classical CMEO limit. Publication Trends: Recent articles (2024-2025) emphasize two thrusts: (i) security of AI/FPGA accelerators—proposing stealthy hardware-Trojan frameworks embedded within design-space-exploration flows that can misclassify up to 97% of inputs—and (ii) power electronics for triboelectric harvesters—introducing dual-output rectifiers and Bennet-doubler biasing that multiply output power >150× over conventional full-wave rectifiers, enabling battery-free IoT nodes. Scientific Awards: APCCAS Best Student Paper Award – 2020 IEEK Best Paper Award – 2012 Students & Collaboration: He has mentored numerous doctoral and master’s scholars, including Yirui Su, Chao Guo, Jinghao Ye, Lin Ye, Saki Tajima, and Masaru Oya, many of whom serve as first authors on his high-impact publications, indicating an active and productive advising role. Labs & Teams: While the text does not name a specific laboratory, his continued affiliation with Waseda University’s Faculty of Science and Engineering and his extensive project output imply he leads a research group focused on secure & energy-efficient VLSI systems, collaborating closely with colleagues such as Prof. Masao Yanagisawa and Prof. Nozomu Togawa.

• Computer Architecture
• Computer Engineering
• VLSI
• +۳ مورد دیگر

Vijaykumar is a Professor in the Elmore Family School of Electrical and Computer Engineering at Purdue University. His research focuses on computer architecture, VLSI design, and circuit optimization. He is affiliated with the Max W and Maileen Brown Family Hall at the West Lafayette campus. Education: B.E. (Hons) in Electrical and Electronics Engineering, M.Sc.(Tech) in Computer Science from Birla Institute of Technology and Science, Pilani, India (1990) M.S. in Computer Science from University of Wisconsin (1992) Ph.D. in Computer Science from University of Wisconsin (1997) His research spans machine learning acceleration, GPU computing, and hardware security. Recent work includes neural radiance field optimizations, speculative execution security, and processing-in-memory architectures. Publications demonstrate expertise in scalable verification, distributed rendering, and efficient data movement. He has contributed to GPU kernel concurrency, sparse tensor acceleration, and memory consistency verification. His email contact is vijay@ecn.purdue.edu , with office location at BHEE 320, Purdue University.

• Computer Architecture
• Hardware Acceleration
• Deep Learning
• +۶ مورد دیگر

Hyuk-Jae Lee is a prominent researcher in computer architecture and hardware acceleration for deep learning systems, with an extensive publication record spanning over two decades. His work primarily focuses on hardware implementations for video processing, memory systems, and neural network acceleration. Through numerous collaborations with researchers at Korean institutions (particularly with Hyun Kim, Chae-Eun Rhee, and Xuan Truong Nguyen), Lee has established himself as a leading figure in circuit design for AI applications. Lee's research interests center around computer architecture, hardware acceleration, deep learning systems, video coding and compression, memory systems, and image processing. His work demonstrates a consistent focus on bridging the gap between theoretical algorithms and practical hardware implementations, with particular emphasis on optimizing performance and efficiency for real-world applications. His recent work shows a strong shift toward accelerating large language models and transformer-based architectures, reflecting current trends in AI hardware. Analysis of Lee's recent publications (2023-2025) reveals a clear research trajectory toward solving memory bandwidth and computational efficiency challenges in modern AI systems. His work spans the spectrum from low-level circuit design to high-level system architecture, with particular strength in memory systems optimization and hardware acceleration for neural networks. The consistent publication record in top-tier IEEE journals demonstrates sustained research productivity and impact in the field. Throughout his career, Lee has collaborated extensively with a core group of researchers, suggesting stable research teams and laboratories focused on hardware acceleration. His publications in IEEE Transactions on Circuits and Systems, IEEE Transactions on Computers, and IEEE Transactions on Video Technology indicate recognition by multiple relevant academic communities.

• Computer Systems
• Soft Computing
• Combinatorial Optimization
• +۵ مورد دیگر

Kazushi Kawamura is an Assistant Professor at the Tokyo Institute of Technology 's AI Computing Research Unit , with prior roles at Waseda University and the Institute of Science Tokyo. His academic journey began at Waseda University, where he earned a Dr. Eng in 2016. 2025.04 - Now: Assistant Professor, School of Fundamental Science and Engineering, Tokyo Tech 2024.10 - 2025.03: Assistant Professor, School of Fundamental Science and Engineering, Waseda 2020.04 - 2025.03: Specially Appointed Assistant Professor, Institute of Integrated Research, Institute of Science Tokyo His research spans combinatorial optimization , annealing processors , Ising machines , and FPGA-based computing systems . He has contributed extensively to LSI design methodology and high-level synthesis . Key publication trends include neural network compression , parallel annealing algorithms , edge AI inference , and sparse matrix operations on FPGAs. His work often integrates theoretical optimization with practical hardware implementations . 2023 CS Achievement Award 2016 ISOCC Best Paper Multiple Algorithm Design Contest Prizes (2014-2019) IPSJ SLDM Outstanding Student Awards Kawamura teaches courses like Physical Electronics Laboratory and Machine Learning at Waseda, with recent projects such as Amorphica (metamorphic annealer) and Pianissimo (sub-mW DNN accelerator). He serves on committees for IEEE , IPSJ , and IEICE , focusing on system design and circuit optimization.

Erdal Orukluمشاهده پروفایل

دانشیار

• Reconfigurable computing
• Advanced computer architectures
• Hardware/software co-design
• +۸ مورد دیگر

Erdal Oruklu is an Associate Professor of Electrical and Computer Engineering and Associate Chair at the Department of Electrical and Computer Engineering, Illinois Institute of Technology (IIT). He joined IIT in 2005 after completing his Ph.D. in Computer Engineering at IIT. His research focuses on reconfigurable computing, advanced computer architectures, VLSI design, and embedded systems, with applications in ultrasonic imaging, signal processing, and machine learning. Education: B.Sc. in Electronics and Communications Engineering from Technical University of Istanbul (1995), M.Sc. in Electrical Engineering from Bogazici University (1999), and Ph.D. in Computer Engineering from IIT (2005). Research interests include real-time ultrasonic embedded systems, system-on-chip (SoC) design, high-speed computer arithmetic, and sensor technologies. He leads the VLSI and SoC Research Laboratory and co-directs the ECASP Laboratory. His work has been supported by grants from NSF, DOE, and industry partnerships. Notable contributions include reconfigurable architectures for ultrasonic flaw detection, polymorphic computing architectures, and FPGA-based implementations of signal processing algorithms. He has supervised numerous Ph.D. and M.S. students, contributing to advancements in hardware/software co-design, embedded systems, and cybersecurity. He holds senior membership in IEEE and serves on editorial boards and technical committees for major conferences. Awards include Best Paper Awards at MWSCAS and EIT, and recognition as an outstanding professor.

Thomas W. Repsمشاهده پروفایل

استاد

• Program analysis
• Abstract interpretation
• Model checking
• +۷ مورد دیگر

Thomas W. Reps is the J. Barkley Rosser Professor & Rajiv and Ritu Batra Chair in the Computer Sciences Department of the University of Wisconsin-Madison, where he has been a faculty member since 1985. He is also President of GrammaTech, Inc., which he co-founded in 1988 to commercialize research on programming environments. Reps received his Ph.D. in Computer Science from Cornell University in 1982, winning the ACM Doctoral Dissertation Award. His research spans program analysis, abstract interpretation, model checking, programming languages, and computer security. Reps's most influential work includes pioneering program slicing techniques with Susan Horwitz, development of the Cornell Program Synthesizer and Synthesizer Generator with Tim Teitelbaum, and significant contributions to interprocedural dataflow analysis. His recent work extends into quantum computing and advanced program synthesis techniques. The analysis of his publications reveals consistent focus on program analysis techniques, with recent papers exploring quantum circuit verification, abstract transformer synthesis, and program synthesis. His work bridges theoretical foundations with practical applications, often addressing scalability challenges in program analysis. NSF Presidential Young Investigator Award (1986) Packard Fellowship (1988) ACM Fellow (2005) ACM SIGPLAN Programming Languages Achievement Award (2017) Elected foreign member of Academia Europaea (2013) Multiple best paper awards including ETAPS (2004, 2008) Reps has advised numerous students, several of whom have received departmental and national recognition. His work on the Wisconsin Program-Slicing Tool led to commercial products through GrammaTech. He has served on advisory boards for significant projects including Year 2000 remediation for the Department of Defense and F/A-22 avionics software integration.

Delphine Demangeمشاهده پروفایل

دانشیار

• Programming languages implementation
• Compiler verification
• Formal semantics
• +۳ مورد دیگر

Delphine Demange is an Associate Professor in Computer Science at the University of Rennes, affiliated with Inria, CNRS, and IRISA. She works in the Epicure research group (formerly Celtique) and focuses on formal semantics, compiler verification, program transformations, static analysis, computer-aided verification, and language-based security. Her career spans roles at the University of Pennsylvania as a postdoctoral researcher and a PhD at ENS Cachan-Brittany Extension under Thomas Jensen and David Pichardie. Her research interests center on formal methods for programming languages , particularly through compiler verification , static analysis , and language-based security . She has mechanized semantics for dataflow circuits and SSA-based optimizations, bridging theoretical rigor with practical compiler correctness. Her work often leverages interactive theorem provers like Coq to ensure robustness. Delphine’s recent publications (2025–2010) highlight her expertise in formal verification of compilers, dataflow analysis , and concurrent systems . Notable trends include mechanized semantics for gated SSA and dataflow circuits , verified intermittent computing models, and concurrent garbage collectors using rely-guarantee methodologies. Scientific Awards: EAPLS Best PhD Dissertation Award (2012) Gilles Kahn PhD Thesis Award (2013) Teaching: She has taught undergraduate and master’s courses including Java programming, algorithmics, deductive verification with Why3, compilation, and software security. Her pedagogical contributions span functional programming, semantics, and logic. Professional Service: Delphine has served on steering committees for CC (2021–2024), co-chaired JFLA 2024 and 2023, and participated in program committees for conferences like CGO, OOPSLA, and POPL.

Sotirios Xydisمشاهده پروفایل

استادیار

• Hardware/Software Co-design
• High Level Synthesis
• Hardware Accelerators
• +۷ مورد دیگر

Sotirios Xydis is an Assistant Professor in the Division of Computer Science at the School of Electrical and Computer Engineering, National Technical University of Athens (NTUA), with prior faculty appointment at Harokopion University of Athens (2020-2023). He maintains ongoing collaboration with the Institute of Communication and Computer Systems (ICCS) since 2014 and previously served as an engineer at HEDNO (2015-2018) and postdoctoral researcher at Politecnico di Milano (2011-2013). His academic credentials include: BSc in Electrical and Computer Engineering, NTUA (2005) MSc in Techno-Economic Systems, NTUA (2011) PhD in Electrical and Computer Engineering, NTUA (2011) Dr. Xydis specializes in hardware/software co-design , energy-efficient hardware acceleration , and memory management for embedded and cloud-edge systems. His research bridges low-power circuit design , heterogeneous architecture optimization , and resource management frameworks , with particular emphasis on AI workloads and serverless infrastructures. Current projects target Edge AI accelerators (CONVOLVE), disaggregated memory systems, and LLM inference optimization through hardware-aware algorithms. Analysis of his 2023-2025 publications reveals three dominant trends: (1) Energy-efficient hardware accelerators for Edge AI using approximate computing techniques, (2) Memory/resource management innovations for disaggregated serverless environments, and (3) GPU/FPGA optimization for LLM inference through dynamic frequency scaling and predictive throttling. These works consistently address the power-performance tradeoffs in heterogeneous computing systems. His scientific recognition includes: Best Paper Award, IEEE/NASA/ESA AHS (2007) Best Paper Award, ACM PARMA (2013) Best Paper Award, ACM Computing Frontiers (2020) Hipeac Award at DAC (2019, 2020) Dr. Xydis has secured over 15 European/national research grants as Principal Investigator and Technical Coordinator, focusing on hardware acceleration frameworks and energy-efficient computing. His advising encompasses graduate research in hardware design and optimization, though specific student names aren't publicly listed. Current projects include CONVOLVE for Edge AI and CollectiveHLS for collaborative hardware synthesis. He is a core member of NTUA's Microelectronics Laboratory (Microlab) and collaborates with ICCS on hardware acceleration projects. His team develops frameworks like CollectiveHLS and throttLL'eM, with active participation in DATE, DAC, and ISCA conference communities.

• programming technologies
• architecture-independent parallel programming
• evolutionary software development
• +۳ مورد دیگر

Alexander Ivanovich Legalov is a Professor at the Department of Software Engineering within the Faculty of Computer Science at the National Research University Higher School of Economics (HSE). He has been working at HSE since 2020, bringing 47 years of scientific and teaching experience to his role. Prior to joining HSE, he served as a Professor at the Siberian Federal University from 2006 to 2020. Professor Legalov earned his Candidate of Technical Sciences degree in 1983 and was awarded the academic title of Associate Professor in 1987. He achieved the Doctor of Technical Sciences degree in 2005 and was granted the academic title of Professor in 2007. His educational background includes a specialization in "Design and production of radio equipment" with the qualification of "Engineer-designer-technologist of radio equipment" from the Krasnoyarsk Polytechnic Institute in 1978. Professor Legalov's research focuses on programming technologies, particularly architecture-independent parallel programming and evolutionary software development. His work explores innovative approaches to parallel programming, including procedural-parametric programming paradigms and functional-dataflow models. He has made significant contributions to language design and transformation, particularly in extending C language capabilities and developing tools for parallel program development. His research demonstrates a consistent trajectory toward creating more flexible and efficient programming paradigms that can adapt to different architectural constraints. HSE University Honorary Diploma (May 2025) Gratitude from the Faculty of Computer Science, National Research University Higher School of Economics (August 2022) Badge of honor "For the development of students' research work" (October 2006) Professor Legalov actively supervises student research, currently guiding Kosov P.V. in dissertation research for the degree of candidate of sciences on "Language and instrumental means of evolutionary development of programs based on the procedural-parametric programming paradigm." He teaches courses on Computer Architecture and Operating Systems for second-year students in the Software Engineering bachelor's program at HSE. Professor Legalov participates in editorial boards of several scientific journals, including "Systems Management, Communications and Security" since 2017, and "Reports of the Russian Academy of Higher School Sciences" since 2010. His technical contributions include multiple registered software programs for functional-dataflow parallel programming languages.

Hao Zhengمشاهده پروفایل

استادیار

• Computer Architecture
• AI/ML Systems
• Domain-specific Accelerators
• +۴ مورد دیگر

Hao Zheng is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida , specializing in computer architecture and AI/ML systems . He received his Ph.D. from The George Washington University in 2021, advised by Prof. Ahmed Louri. Research Focus: Domain-specific accelerators, wafer-scale integration, hardware-software co-design, and AI-assisted chip design. Teaching: EEL6938 (Computer Architecture for AI/ML) since Fall 2025. His recent work explores graph neural networks , vision transformer acceleration , and secure on-chip communication , with publications at top venues like ISCA, MICRO, and DAC. He serves as an Associate Editor for IEEE Transactions on Computers and IEEE Transactions on Sustainable Computing. Notable honors include the NSF CAREER Award (2025) , GWU ECE Best Dissertation (2022) , and multiple AMD Fellowships for his students. His iCAT Lab focuses on cutting-edge research in computer architecture, supported by grants from L3Harris and NVIDIA .

Arlei Silvaمشاهده پروفایل

استادیار

• Data Science
• Network Science
• Machine Learning
• +۵ مورد دیگر

Arlei Silva is an Assistant Professor of Computer Science at Rice University. He holds a Ph.D. from the University of California, Santa Barbara (UCSB), and M.Sc. and B.Sc. degrees from Universidade Federal de Minas Gerais, Brazil. His research focuses on data science, network science, machine learning, and graph algorithms, with applications in flood prediction, graph anomaly detection, and temporal graph analysis. He has held visiting roles at Rensselaer Polytechnic Institute and has contributed to projects like trajectory compression and network process discovery. Education: Ph.D. in Computer Science, University of California, Santa Barbara (2019) M.Sc. in Computer Science, Universidade Federal de Minas Gerais, Brazil (2011) B.Sc. in Computer Science, Universidade Federal de Minas Gerais, Brazil (2008) Research Interests: His work integrates machine learning and graph theory to address challenges in network dynamics, spatiotemporal modeling, and anomaly detection. Recent projects include FloodGNN-GRU for flood prediction, DOPPLER for dataflow optimization, and Pole for signed network embeddings. Awards: SNAKDD Best Paper Runner-up (2013) Best M.Sc. Thesis (Brazilian Computer Society, 2011) Best Undergraduate Research (top 6, Brazilian Computer Society, 2009) Labs/Teams: Engages in interdisciplinary projects at Rice, focusing on environmental informatics and network science. His GitHub repositories include work on trajectory compression, anomaly detection, and spectral algorithms for graph cuts.

Arijit Raychowdhuryمشاهده پروفایل

استاد

• Low Power Digital Circuits
• Compute-in-Memory (CIM)
• Adaptive Clocking and Power Management
• +۷ مورد دیگر

Arijit Raychowdhury is a Professor and the Steve W. Chaddick School Chair at Georgia Tech's School of Electrical and Computer Engineering (ECE). He leads the Center for the Co-Design of Cognitive Systems (CoCoSys) and directs the DoD-sponsored SCALE Workforce Development Program in SoC Design. Current affiliations: Georgia Tech (ECE), Integrated Circuits and Systems Research Lab Prior affiliations: Intel Corporation (6 years), Texas Instruments (1.5 years) Research interests focus on low-power circuits, compute-in-memory (CIM) systems, cryogenic electronics, and neuro-symbolic AI. His work bridges circuit design with emerging device technologies and machine learning applications. Scientific contributions include: Over 250 publications and 27 patents Leadership in top conferences (ISSCC, VLSI Symposium, DAC, CICC) Pioneering 3D Gaussian Splatting acceleration, adaptive echo-cancellation networks, and CIM architectures Advancing GaN-based power converters and cryogenic CMOS Awards : IEEE Fellow (2022) SRC Technical Excellence Award (2021) Qualcomm Faculty Award (2021, 2020) IEEE/ACM Innovator under 40 (2018) Intel Young Faculty Award (2015) Dimitris N. Chorafas Award (2007) Leadership : • Director of CoCoSys Center • Site Director for SCALE Program • Distinguished Lecturer, IEEE Solid-State Circuits Society