جست‌وجوی استاد و پژوهشگر

• Wireless Communication
• Antenna Design
• Microwave Engineering
• +۶ مورد دیگر

Dr. Sam Lemey is an Associate Professor at the Faculty of Engineering and Architecture , Ghent University , and a researcher at IMEC . His work focuses on advanced antenna systems, microwave engineering, and wireless communication technologies. Primary affiliations: Ghent University, IMEC Key research areas: Millimeter-wave systems, UWB antennas, smart surfaces, RF-energy harvesting His research explores millimeter-wave distributed antenna systems for virtual reality and robotics, air-filled substrate-integrated waveguide (AFSIW) components , and machine learning applications in RF signal optimization. He has developed low-cost antenna arrays for 5G/6G, terahertz communication systems , and textile-integrated antennas for wearable IoT devices. Publications show trends in beamforming networks , radio-over-fiber integration, and human exposure reduction strategies. His work frequently involves collaborations with engineers and physicists on heterogeneous integration projects.

Navid Asadiمشاهده پروفایل

دانشیار

• Hardware Security
• Reverse Engineering
• 3D Imaging
• +۷ مورد دیگر

Navid Asadi is an Associate Professor in the Electrical & Computer Engineering Department at the University of Florida, affiliated with the Materials Science & Engineering department. He leads the Security and Assurance (SCAN) Lab, equipped with $12M in advanced imaging tools, and serves as Associate Director of the Florida Semiconductor Institute and the Microelectronics Security Training (MEST) center. His research focuses on hardware security, reverse engineering, 3D imaging, and semiconductor assurance. Dr. Asadi has received NSF CAREER (2022) and multiple best paper awards, including from IEEE HOST and ASME ISFA. He pioneered the IEEE PAINE conference and collaborates with agencies like NSF, AFRL, and industry partners. Education: PhD, Mechanical Engineering, University of Connecticut, 2014 MS, Biomedical Engineering, Amir Kabir University of Technology, 2009 BS, Mechanical Engineering, K.N. Toosi University of Technology, 2007 Research Interests: Dr. Asadi’s work spans hardware security mechanisms, advanced packaging inspection, AI-driven defect detection, and semiconductor supply chain assurance. He develops novel techniques for X-ray compatibility metrics, PCB inspection via deep learning, and physical security of silicon photonics. His lab addresses challenges in heterogeneous integration, counterfeit detection, and runtime system-on-chip (SoC) validation. Awards: NSF CAREER Award (2022) Best Paper Award, HOST International Conference (2016) D.E. Crow Innovation Award (University of Connecticut) Labs & Initiatives: Directs the SCAN Lab and oversees the MEST center, training engineers in microelectronics security. His work integrates quantum sensing, THz spectroscopy, and optical neural networks to enhance hardware assurance. Current projects include AI-driven inspection systems, chiplet authentication (ChiPICA), and defense against probing attacks.

Shahin Tajikمشاهده پروفایل

استادیار

• Hardware Security
• Cybersecurity
• FPGA Security
• +۷ مورد دیگر

Shahin Tajik is an Assistant Professor at the Department of Electrical & Computer Engineering at Worcester Polytechnic Institute (WPI), with affiliations in Cybersecurity. He joined WPI in July 2020 after serving as an Assistant Research Professor at the Florida Institute for Cybersecurity Research (FICS) at the University of Florida. He holds a Ph.D. in Electrical Engineering from the Technical University of Berlin (2017), an M.S. from the same institution (2013), and a B.S. from K. N. Toosi University of Technology (2010). His research focuses on hardware security, including non-invasive/semi-invasive side-channel analysis, Physically Unclonable Functions (PUFs), FPGA security, and anti-tamper mechanisms. Notable contributions include his ACM CCS’17 paper on optical contactless probing of FPGA bitstream encryption, which won the 2017 CSAW Applied Research Competition. He is also the recipient of the NSF CAREER Award for his work on power delivery network-aware hardware security. Dr. Tajik has served as a reviewer for IEEE and ACM journals and as a technical program committee member for conferences like CHES, HOST, and FDTC. His recent research explores tamper detection via impedance sensing, laser fault injection defenses, and secure edge computing through the Northeastern Microelectronics Coalition (NEMC), where he leads the Secure Edge Computing tech area. Education: Ph.D., Electrical Engineering, Technical University of Berlin (2017) M.S., Electrical Engineering, Technical University of Berlin (2013) B.S., Electrical Engineering, K. N. Toosi University of Technology (2010) His work bridges theoretical advancements with practical defenses, emphasizing hardware's physical layer vulnerabilities. Recent trends in his publications address challenges like chiplet verification, impedance-based tamper detection, and leveraging AI for forensic analysis of electronic components. Awards: NSF CAREER Award (2024) 1st Place, CSAW Applied Research Competition (2017) His grants include funding for laser-assisted attack monitoring (2022) and NSF support for student travel to hardware security events (2024). He collaborates on initiatives like CHIPS Act’s Microelectronics Commons program through NEMC, advancing secure edge computing infrastructure. Labs/Teams: Technical co-lead for Secure Edge Computing at NEMC, involved in interdisciplinary projects addressing hardware security across academia and industry.

Frank Kagan Gürkaynakمشاهده پروفایل

پژوهشگر

• Energy-Efficient Microelectronics
• Cryptographic Hardware Security
• Digital Integrated Circuit Design
• +۴ مورد دیگر

Frank Kagan Gürkaynak is Director of the Microelectronics Design Center (DZ) and a Researcher at ETH Zurich's Department of Information Technology and Electrical Engineering (D-ITET). He leads the PULP open-source hardware project and works closely with Prof. Luca Benini in the Integrated Systems Laboratory (IIS). His academic journey includes BSc/MSc from Istanbul Technical University and a PhD from ETH Zurich. Roles: Microelectronics Design Center Director, Senior Scientist in IIS, VLSI course lecturer Research focuses on energy-efficient digital circuits, cryptographic hardware security, and open-source processor architectures. Key projects include EU-funded initiatives like European Processor Initiative (EPI), Convolve, and NeuroSoC, along with SNSF grants Tiny Trainer and PEDESITE. Active in teaching VLSI design, embedded systems, and essential engineering skills. Publications emphasize secure cryptographic accelerators, low-power processor clusters, and GALS system design methodologies. Contributions include energy-efficient ASICs for IoT to HPC domains and pioneering work in side-channel attack-resistant hardware.

Margaret Martonosiمشاهده پروفایل

استاد

• Computer Architecture
• Quantum Computing
• Power-Efficient Systems
• +۳ مورد دیگر

Margaret Martonosi is the William M. Addy ’82 University Professor of Computer Science at Princeton University, a position she has held since 1994. Her research focuses on computer architecture, with significant contributions to both classical and quantum systems. She has led major initiatives such as co-founding the ACM CARES movement and served as Director of the NSF Directorate for Computer and Information Science and Engineering (CISE) from 2020 to 2024. Her work emphasizes power-efficient designs, quantum hardware/software co-design, and scalable hybrid computing frameworks. Her academic leadership includes roles in broadening participation in computing through the Computing Research Association (CRA-W) and mentorship recognized by awards like the ACM Frances E. Allen Award. She has authored over 200 papers, with impactful contributions in security (e.g., SoCurity frameworks), quantum architectures (e.g., ARQUIN, HetArch), and heterogeneous computing (e.g., DCRA chiplet systems). Her recent research addresses challenges in quantum-classical integration and post-Moore’s Law computing paradigms. Publications highlight innovations like TensorQC for hybrid quantum-classical systems and CutQC for distributed quantum circuit optimization. Her NSF leadership shaped federal computing research priorities, emphasizing quantum science, AI, and cyberinfrastructure. She maintains active roles in technical societies and serves on non-profit boards focused on advancing computing equity and accessibility. Key grants include the $115M quantum science center (with Princeton’s electrical engineering collaboration) and EPiQC (Enabling Practical-Scale Quantum Computation). Her lab develops tools like MosaicSim for agile hardware-software co-design and RTLCheck for verifying hardware consistency models. Leadership Roles: NSF CISE Director (2020–2024), ACM CARES Co-founder, CRA-W Board Key Projects: Quantum-Supercomputing Integration, Power-Efficient Architectures, Formal Verification Frameworks Recent Focus: Quantum Benchmarking (SuperMARQ), Edge Computing Security, Chiplet-Based Systems

Andreas G. Andreouمشاهده پروفایل

استاد

• Computing Machinery
• Sensory Information Processing
• Theoretical Neuroscience
• +۶ مورد دیگر

Andreas G. Andreou is a Professor at Johns Hopkins University with primary appointments in the Department of Electrical and Computer Engineering, and secondary appointments in the Department of Computer Science and the Whitaker Biomedical Engineering Institute. He co-founded the Johns Hopkins University Center for Language and Speech Processing (CLSP) and co-directs the Andreou Lab alongside Philippe Pouliquen. His research focuses on brain-inspired microsystems for sensory information processing, neuromorphic computing, and theoretical neuroscience. Education: Born in Nicosia, Cyprus; resides in Baltimore, Maryland. Research Interests: Computing Machinery, Sensory Information Processing, Theoretical Neuroscience, Pattern Analysis, Machine Intelligence, Microsystems Technologies, and Integrated Circuits. Awards: IEEE Fellow, 3rd Best Paper Award at IEEE BioCAS 2018, and recognition for the award-winning Stethovest wearable acoustic sensing array. His lab explores energy-efficient computing beyond Moore's Law, integrating neuroscience principles into microsystem design. Recent projects include quantum-inspired neuromorphic optimizers, AI-generated chips using ChatGPT4, and applications in cardiac acoustics and wearable technology. Collaborations span institutions like NSF, JHU-APL, and the Telluride Neuromorphic AI workshop. His work is supported by grants from DARPA, NSF, NIH, ONR, AFRL, and JHU-APL. He also holds honorary professorships at the University of Cyprus and Universidad Nacional del Sur.

Erik Jan Marinissenمشاهده پروفایل

پژوهشگر

• Semiconductor Testing
• 3D Integrated Circuits
• Design-for-Test
• +۵ مورد دیگر

Erik Jan Marinissen serves as Scientific Director at imec (Leuven, Belgium) and holds a Visiting Researcher position at Eindhoven University of Technology's Department of Electronic Systems. With over 270 publications and 18 patent families, his career spans NXP Semiconductors, Philips Research, and imec since 1992. He holds MSc and PDEng degrees from Eindhoven University of Technology (1990, 1992). His research focuses on semiconductor test engineering for advanced technologies, particularly 3D-stacked ICs , chiplet-based packages , and sub-5nm CMOS nodes . Key contributions include diagnostic frameworks for Network-on-Chips, test standards for TSV-based integration, and cell-aware testing methodologies. His work bridges industrial applications (NXP, Philips) and academic research through imec's ecosystem. Marinissen's publication trends show increasing focus on heterogeneous integration (2018-2024), with 60% of recent articles addressing chiplet interconnect testing and 3D IC validation. His 2023-2024 work pioneers device-aware testing for quantum components and 3nm technology nodes. Most Significant Paper Awards at IEEE ITC (2008, 2010) Best Paper Awards at IWLPC (2018), LATS (2019), DATE (2020) IEEE Standards Association Emerging Technology Award (2017) HiPEAC Tech Transfer Award (2015) IEEE Fellow (2011) As founder of the 3D-TEST workshop series and IEEE Std P1838 Working Group, he has secured industry-wide adoption of test standards. His supervision of 43 MSc/PhD students demonstrates strong academic mentorship, while his editorial roles at IEEE Design & Test and Springer's Journal of Electronic Testing shape research dissemination. Current work at imec focuses on test solutions for STT-MRAMs and silicon photonics.

Qian Xuمشاهده پروفایل

پژوهشگر ارشد

• Quantum Error Correction
• Fault-Tolerant Quantum Computing
• Quantum Computing
• +۳ مورد دیگر

Qian Xu is a Sherman Fairchild Postdoctoral Scholar Research Associate at the Walter Burke Institute for Theoretical Physics, California Institute of Technology (Caltech), supervised by John Preskill. Their research focuses on quantum error correction and fault-tolerant quantum computing within Caltech's theoretical physics ecosystem. Education: Ph.D. in Quantum Science and Engineering, University of Chicago (2024), advised by Liang Jiang. Thesis: 'Towards Practical Fault-Tolerant Quantum Computing'. B.S. in Physics, Nanjing University (2019). Research Interests: Xu pioneers approaches to minimize space-time overhead in fault-tolerant quantum systems through novel error-correcting codes and noise-robust processor design. Their work integrates quantum error correction, quantum control, and reservoir engineering to develop practical quantum computing architectures. Key innovations include tailored codes for biased noise environments and hardware-efficient protocols for bosonic qubit systems. Current investigations span quantum LDPC codes, homological product codes, and cat qubit stabilization techniques. Publication Trends: Xu's 12 publications (2021-2024) reveal three dominant research thrusts: (1) Low-overhead fault tolerance using quantum LDPC and homological product codes; (2) Hardware-efficient bosonic qubit systems (cat/squeezed cat codes); (3) Noise-adaptive topological code design. This work demonstrates consistent focus on reducing physical resource requirements while maintaining fault tolerance, with increasing emphasis on experimental feasibility through collaborations with quantum hardware groups. Labs and Teams: As a member of Caltech's Walter Burke Institute for Theoretical Physics, Xu collaborates extensively with the Preskill research group and experimental teams at Harvard/MIT. Their work bridges theoretical quantum information science and near-term quantum device engineering through the Institute's cross-disciplinary framework.

Giovanni Ansaloniمشاهده پروفایل

مدرس

• Embedded Systems
• Reconfigurable Computing
• Low-Power Design
• +۲ مورد دیگر

Dr Giovanni Ansaloni is Senior Scientist and Lecturer at EPFL's Embedded Systems Laboratory. His research focuses on energy-efficient computing architectures including reconfigurable systems, near-memory processing, and hardware accelerators for edge AI and biomedical applications. He develops frameworks for deploying machine learning models on resource-constrained devices, specializing in hardware-software co-design for embedded systems. Recent work explores RISC-V based accelerators, in-memory computing architectures, and optimization techniques for health monitoring applications. His teaching covers embedded systems design and applications, bridging theoretical concepts with practical implementation challenges in low-power computing platforms.

Hui Zhaoمشاهده پروفایل

دانشیار

• Computer Architecture
• Network-on-Chip (NoC)
• GPU Acceleration
• +۳ مورد دیگر

Hui Zhao is an active Associate Professor in the Department of Computer Science and Engineering at the University of North Texas, maintaining an office in Discovery Park (F297C) with direct contact via Hui.Zhao@unt.edu. His academic role encompasses both teaching responsibilities and dual-path research leadership spanning computational engineering and cognitive science. Dr. Zhao's research program uniquely bridges two high-impact domains: computer architecture and cognitive neuroscience. In hardware systems, he pioneers Network-on-Chip (NoC) innovations for deep learning acceleration, GPU optimization for genomic analysis, and reconfigurable interconnection networks for heterogeneous chiplets. Concurrently, his neuroscience work investigates brain network dynamics underlying children's academic achievement, arithmetic performance, stress responses, and fear processing using fMRI methodologies. This interdisciplinary fusion enables hardware designs informed by neural computation principles and cognitive models enhanced by computational engineering. Analysis of his 2021-2025 publications reveals a strategic research trajectory where 70% of output focuses on hardware acceleration (particularly NoC architectures and GPU optimization), while 30% explores cognitive neuroscience applications. Key trends include increasing integration of machine learning for performance prediction (2022-2025) and expanding cognitive studies from basic distance perception (2021) to complex multi-task academic achievement models (2025). His work consistently targets real-world applications in education technology, mental health interventions, and high-performance computing. No scientific awards were documented in the source materials. While the provided texts do not specify student advisees or grant funding details, his prolific publication rate (15+ articles annually since 2021) suggests active mentorship of graduate researchers and sustained external funding. The interdisciplinary nature of his work implies collaboration across computer science, neuroscience, and psychology departments. Lab infrastructure details were not explicitly mentioned, though his research areas suggest involvement with hardware testbeds for NoC/GPU systems and access to neuroimaging facilities for cognitive studies, likely operating through University of North Texas' Discovery Park research complex.

• Data Management Systems
• Database Systems
• Operating Systems
• +۴ مورد دیگر

Prof. Jana Giceva Makreshanska is a Professor of Database Systems at the Technical University of Munich (TUM), affiliated with the TUM School of Computation, Information and Technology and the Department of Computer Science. Her research focuses on systems support for data management, leveraging modern hardware architectures including operating systems, compilers, and computer architecture. She holds a PhD from ETH Zurich (2017) and previously served as faculty at Imperial College London. Notable awards include the ERC Starting Grant (2024), VMware Early Career Faculty Award (2019), and ETH Medal (2018). Education: PhD in Computer Science, ETH Zurich (2017) Research roles at Microsoft Research and Oracle Labs Research Interests: Her work addresses holistic system design challenges in data management, including optimizing query processing for modern hardware, compiler integration, and emerging architectures like chiplets. She explores efficient data processing techniques for big data and transactional systems. Recent Contributions: Her recent work includes innovations in disaggregated systems (HotOS 2023), chiplet-aware scheduling (2025), and universal graph data structures (VLDB 2022). Her publications span topics like NVMe array optimization, FPGA-based partitioning, and hybrid OLTP/OLAP systems. Awards: ERC Starting Grant (2024) Best Paper Runner-Up at VLDB 2022 ACM SIGMOD Highlights Award (2023) Teaching & Service: Current courses include 'Cloud-Based Data Processing' and 'Data Processing on Modern Hardware'. She chairs diversity initiatives at SoCC 2023, serves on program committees for OSDI, VLDB, and SIGMOD, and leads gender equality efforts at TUM. Labs/Teams: Maintains the Lehrstuhl III (I3) database systems group at TUM, collaborating on projects like LakeVilla and ARCAS.

Matt Sinclairمشاهده پروفایل

استادیار

• Computer Architecture
• Heterogeneous Computing
• GPU Architecture
• +۷ مورد دیگر

Matt Sinclair is an Assistant Professor in the Computer Sciences Department at the University of Wisconsin–Madison, with affiliate appointments in the Electrical and Computer Engineering Department and the Teaching Academy. He leads the Heterogeneous Architectures Lab (HAL) and is actively involved in the gem5 Project Management Committee, focusing on modern heterogeneous computing systems. His research interests include computer architecture, GPU design, parallel programming, operating systems, and high-performance computing. He develops tools and methodologies for programming and optimizing future heterogeneous systems, particularly focusing on GPUs. His work spans architectural design, efficient software implementation, and simulation frameworks. Recent publications highlight advancements in gem5 simulation accuracy, GPU energy modeling, synchronization mechanisms, and scheduling policies for ML workloads. His research has led to improvements in GPU memory bandwidth modeling, extensible power modeling, and full-system heterogeneous simulation capabilities. Scientific awards include the NSF CAREER Award, the David J. Kuck Outstanding PhD Thesis Award, and a Qualcomm Innovation Fellowship. He has also received honors such as the ACM SIGARCH–IEEE TCCA Outstanding Dissertation Award Honorable Mention and multiple fellowships. He mentors a diverse group of graduate and undergraduate students, many of whom have published at top venues and moved on to roles at NVIDIA, AMD, Microsoft, and leading graduate programs. He is involved in teaching and curriculum development, particularly through the Excel Initiative and as a former Madison Teaching & Learning Fellow. He also stewards the ISCA Hall of Fame, contributing to the academic community beyond research.

Torsten Hoeflerمشاهده پروفایل

استاد

• High-Performance Computing
• Parallel Computing
• Computer Networks
• +۳ مورد دیگر

Prof. Torsten Hoefler is a Full Professor at the Department of Computer Science, ETH Zürich. His research focuses on High-Performance Computing (HPC), parallel systems, networking, and AI-infrastructure. He leads projects on scalable interconnects, network topology design, and cloud computing benchmarks like SeBS. His work bridges theoretical foundations with practical implementations in distributed systems. Research Interests : High-Performance Computing & Networking Parallel Algorithms & Architectures AI Infrastructure & Distributed Systems Chiplet Interconnects & Topology Optimization Key Contributions : Developed tools like ATLAHS (AI/HPC network simulation) Advanced RDMA-based communication protocols (SDR-RDMA) Benchmarks for serverless computing (SeBS-Flow) His recent articles (2025) emphasize adaptive networks, low-precision AI models, and energy-efficient HPC systems. He also explores ethical computing and sustainability in supercomputing through initiatives like Core Hours & Carbon Credits.

Borivoje Nikolicمشاهده پروفایل

استاد

• Integrated Circuits (VLSI)
• Computer Architecture
• Signal Processing
• +۳ مورد دیگر

Borivoje Nikolic is a Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He holds a Ph.D. from UC Davis (1999) and academic degrees from the University of Belgrade (Dipl.Ing. 1992, M.Sc. 1994). His research focuses on integrated circuits, VLSI design, and energy-efficient electronics, with contributions to analog/digital circuit design, signal processing algorithms, and wireless communication systems. Notable roles include Technical Program Chair for the 2022 Symposium on VLSI Technology and Circuits, and General Chair for the 2024 IEEE Symposium on VLSI Technology and Circuits. He was an IEEE Distinguished Lecturer (2014–2015). His work has led to over 100 publications in top-tier venues like ISSCC, IEEE Journal of Solid-State Circuits, and IEEE Transactions on Circuits and Systems. Research interests span: VLSI Design Automation and Generators Low-Power and Energy-Efficient Circuits Wireless Communication Systems and MIMO Architectures Robotics and Heterogeneous SoC Design His publications highlight innovations in clock generators, data converters, and hardware-software co-design for AI/ML acceleration. Awards include the NSF CAREER Award (2003), IEEE Fellow (2017), and the 2024 SSCS Innovative Education Award.

Xuejun Fanمشاهده پروفایل

استاد

• Electronics Packaging Reliability
• Material Characterization
• Finite Element Analysis
• +۵ مورد دیگر

Dr. Xuejun Fan is a Regents' Professor and Mary Ann and Lawrence E. Faust Endowed Professor in the Department of Mechanical Engineering at Lamar University. His career spans academia and industry, with expertise in microelectronics packaging reliability, material characterization, and thermal management. He earned his Ph.D. in Solid Mechanics from Tsinghua University (1989) and held roles at Taiyuan University of Technology, University of Tokyo, and Intel Corporation before joining Lamar University in 2007, where he was promoted to full professor in 2013. Education: Ph.D. (Solid Mechanics, Tsinghua University), M.S. & B.S. (Applied Mechanics, Tianjin University) Dr. Fan's research focuses on multi-physics modeling of electronic packaging, moisture-induced reliability in IC devices, electromigration analysis in interconnects, and thermal management for LEDs and power electronics. His work includes nanoscale material characterization and warpage-free packaging design . Publications highlight applications in heterogeneous integration and corrosion-resistant nanomaterials . His 15 most recent articles emphasize chiplet packaging , electromigration modeling , and AI-driven reliability optimization . Key trends include thermal-mechanical stress analysis in SiC modules and moisture diffusion in nanocopper pastes. Scientific Awards: IEEE Fellow, EuroSimE Achievement Award, Top 2% Scientist (2024), Distinguished Faculty Research Fellow Dr. Fan mentors graduate students in finite element analysis , electromigration , and material testing using equipment like DMA/TMA/TGA analyzers and Labsphere Illumia Pro . He serves as Associate Editor for IEEE Transactions and Microelectronics Reliability, and contributes to industry standards via IEEE EPS.