Dr Giovanni Ansaloni is Senior Scientist and Lecturer at EPFL's Embedded Systems Laboratory. His research focuses on energy-efficient computing architectures including reconfigurable systems, near-memory processing, and hardware accelerators for edge AI and biomedical applications. He develops frameworks for deploying machine learning models on resource-constrained devices, specializing in hardware-software co-design for embedded systems. Recent work explores RISC-V based accelerators, in-memory computing architectures, and optimization techniques for health monitoring applications. His teaching covers embedded systems design and applications, bridging theoretical concepts with practical implementation challenges in low-power computing platforms.
Prof. Jana Giceva Makreshanska is a Professor of Database Systems at the Technical University of Munich (TUM), affiliated with the TUM School of Computation, Information and Technology and the Department of Computer Science. Her research focuses on systems support for data management, leveraging modern hardware architectures including operating systems, compilers, and computer architecture. She holds a PhD from ETH Zurich (2017) and previously served as faculty at Imperial College London. Notable awards include the ERC Starting Grant (2024), VMware Early Career Faculty Award (2019), and ETH Medal (2018). Education: PhD in Computer Science, ETH Zurich (2017) Research roles at Microsoft Research and Oracle Labs Research Interests: Her work addresses holistic system design challenges in data management, including optimizing query processing for modern hardware, compiler integration, and emerging architectures like chiplets. She explores efficient data processing techniques for big data and transactional systems. Recent Contributions: Her recent work includes innovations in disaggregated systems (HotOS 2023), chiplet-aware scheduling (2025), and universal graph data structures (VLDB 2022). Her publications span topics like NVMe array optimization, FPGA-based partitioning, and hybrid OLTP/OLAP systems. Awards: ERC Starting Grant (2024) Best Paper Runner-Up at VLDB 2022 ACM SIGMOD Highlights Award (2023) Teaching & Service: Current courses include 'Cloud-Based Data Processing' and 'Data Processing on Modern Hardware'. She chairs diversity initiatives at SoCC 2023, serves on program committees for OSDI, VLDB, and SIGMOD, and leads gender equality efforts at TUM. Labs/Teams: Maintains the Lehrstuhl III (I3) database systems group at TUM, collaborating on projects like LakeVilla and ARCAS.
Saksham Agarwal is an Assistant Professor in the departments of Electrical and Computer Engineering and Computer Science at the University of Illinois at Urbana-Champaign (UIUC). His research focuses on the intersection of networking, systems, and hardware, with a particular emphasis on host congestion control, datacenter architectures, and network protocols. He received his Ph.D. in Computer Science from Cornell University under the supervision of Prof. Rachit Agarwal and completed his undergraduate studies at IIT Kanpur. Research Interests: Host congestion control, datacenter networks, hardware-software co-design, network protocols, and systems optimization. His work includes seminal contributions like hostCC (host congestion control architecture) and Harmony (congestion-free datacenter architecture). Awards: ACM SIGCOMM Doctoral Dissertation Award (2025), Cornell CS Dissertation Award (2025), IRTF Applied Networking Research Prize (2025), Google PhD Fellowship (2019), Best Student Paper Awards (SIGCOMM 2024 and SIGCOMM 2018). Teaching: CS 438/ ECE 438 Communication Networks, ECE 598MCI Modern Cloud Infrastructure. Advising: Current students include Midhul Vuppulapati (SIGCOMM'24 Best Paper recipient), Shreyas Kharbanda, and Omar Eqbal. Labs/Teams: Lead researcher on host congestion control and datacenter network projects. Collaborates on open-source implementations of hostCC and Harmony .
Anand Raghunathan is a Silicon Valley Professor and Chair of the VLSI area at Purdue University's Elmore Family School of Electrical and Computer Engineering. He serves as Associate Director of the $36M SRC/DARPA Center for Brain-inspired Computing (C-BRIC) and Co-Director of the Purdue/TSMC Center for a Secure Microelectronics Ecosystem (CSME). His research focuses on Brain-inspired computing Energy-efficient machine learning System-on-chip design Post-CMOS devices Heterogeneous computing Educated with a B.Tech from IIT Madras, and MA/PhD in Electrical Engineering from Princeton University, he directs Purdue's Integrated Systems Laboratory (ISL) which explores domain-specific architectures and compute-in-memory technologies. His work spans security for embedded systems, battery-efficient computing, and computational imaging commercialized through High Performance Imaging, Inc. Research keywords include: Neural network acceleration Hardware-software co-design Security vulnerabilities Post-CMOS devices Transformer optimization Scientific awards include: IEEE Fellow MIT TR35 innovator 9 Best Paper Awards 2 NEC Technology Commercialization Awards Purdue Faculty Excellence Award Advising and grants: Co-founded High Performance Imaging, Inc. Founded Purdue/TSMC Center for Secured Microelectronics Ecosystem Hold 29 U.S. and 16 international patents Chair of 5 IEEE/ACM conferences Editorial roles in ACM/IEEE journals Labs and teams: Integrated Systems Laboratory (ISL) Collaborations with NEC Labs, Princeton University, and IIT Madras Lead $36M SRC/DARPA C-BRIC Center
Prof. Torsten Hoefler is a Full Professor at the Department of Computer Science, ETH Zürich. His research focuses on High-Performance Computing (HPC), parallel systems, networking, and AI-infrastructure. He leads projects on scalable interconnects, network topology design, and cloud computing benchmarks like SeBS. His work bridges theoretical foundations with practical implementations in distributed systems. Research Interests : High-Performance Computing & Networking Parallel Algorithms & Architectures AI Infrastructure & Distributed Systems Chiplet Interconnects & Topology Optimization Key Contributions : Developed tools like ATLAHS (AI/HPC network simulation) Advanced RDMA-based communication protocols (SDR-RDMA) Benchmarks for serverless computing (SeBS-Flow) His recent articles (2025) emphasize adaptive networks, low-precision AI models, and energy-efficient HPC systems. He also explores ethical computing and sustainability in supercomputing through initiatives like Core Hours & Carbon Credits.
Borivoje Nikolic is a Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley. He holds a Ph.D. from UC Davis (1999) and academic degrees from the University of Belgrade (Dipl.Ing. 1992, M.Sc. 1994). His research focuses on integrated circuits, VLSI design, and energy-efficient electronics, with contributions to analog/digital circuit design, signal processing algorithms, and wireless communication systems. Notable roles include Technical Program Chair for the 2022 Symposium on VLSI Technology and Circuits, and General Chair for the 2024 IEEE Symposium on VLSI Technology and Circuits. He was an IEEE Distinguished Lecturer (2014–2015). His work has led to over 100 publications in top-tier venues like ISSCC, IEEE Journal of Solid-State Circuits, and IEEE Transactions on Circuits and Systems. Research interests span: VLSI Design Automation and Generators Low-Power and Energy-Efficient Circuits Wireless Communication Systems and MIMO Architectures Robotics and Heterogeneous SoC Design His publications highlight innovations in clock generators, data converters, and hardware-software co-design for AI/ML acceleration. Awards include the NSF CAREER Award (2003), IEEE Fellow (2017), and the 2024 SSCS Innovative Education Award.
Martin Radetzki is a full Professor at the Institute for Computer Architecture and Parallel Systems (University of Stuttgart) , specializing in Embedded Systems . His work focuses on network-on-chip (NoC) design, fault tolerance, memory optimization, and simulation frameworks. Key research areas: NoC synthesis, deadlock-free routing, performability analysis, and power-efficient memory subsystems Recent publications emphasize integer linear programming frameworks for co-designing floorplanning and routing, chiplet-based systems , and machine learning-enabled performance evaluation His methodologies address cross-layer challenges in NoC design, combining formal optimization with practical implementation for heterogeneous processing elements. Collaborative projects include fault resilience analysis, parallel simulation techniques, and memory allocation strategies for SoCs. Dr. Radetzki supervises research with students like Shuang Liu and Manuel Strobel , contributing to IEEE Transactions on Computers , ACM TECS , and conferences such as DATE and MCSoC . Current work explores optimal routing topologies for emerging chip architectures.
Christophe Bobda is a Citi Endowed Professor in Advanced Technologies and Associate Chair for Academics at the University of Florida's Department of Electrical & Computer Engineering within the Herbert Wertheim College of Engineering. His research focuses on FPGA-based systems, cybersecurity, embedded systems, and resilient architectures. He holds a Ph.D. from the University of Paderborn, Germany, and degrees from Universities in Germany and Cameroon. Research interests include System-on-Chip design, reconfigurable computing, and robotics. Notable contributions span secure cloud FPGA deployment, multi-tenant hardware security, and near-sensor processing architectures. He received the HWCOE International Educator of the Year award in 2024. Recent work emphasizes FPGA security in cloud environments, with projects like CIVIC-FPGA and ISO-TENANT addressing isolation and attack mitigation. His lab explores embedded imaging and robotics applications, leveraging low-power and high-performance FPGA solutions. NSF grants support his research in FPGA acceleration and datacenter infrastructure. Publications highlight advancements in event-based vision systems, 3D semantic modeling, and hardware trojan detection. Ongoing projects include chiplet interfaces for on-device AI and galvanic isolation for physical attack prevention. His work bridges theoretical cybersecurity with practical FPGA implementations for resilient systems.
Avinash Karanth is the Joseph K. Jachinowski Professor and Director of the School of Electrical Engineering and Computer Science (EECS) at Ohio University's Russ College of Engineering and Technology. He leads the Technologies for Emerging Computer Architecture Laboratory (TEAL) and has held faculty roles since 2006. His research focuses on computer architecture, machine learning accelerators, network-on-chips (NoCs), photonic interconnects, and hardware security. Education: Ph.D. (2006) and M.S. (2003) in Electrical and Computer Engineering from the University of Arizona; B.E. (2000) in Electronics and Communications Engineering from Manipal Institute of Technology. His research interests include energy-efficient architectures, photonic computing, and fault-tolerant systems. Notable awards include the NSF CAREER Award (2011) and Presidential Research Scholar Award (2017). He has published over 100 peer-reviewed articles and holds multiple patents in NoC design and photonic interconnects. Karanth serves as an Associate Editor for IEEE Transactions on Computers and has chaired major conference tracks like IPDPS and DAC. His work spans grants from NSF, Air Force Research Lab, and AMD. Key projects include photonic accelerators for DNNs, sustainable computing with phase-change memory, and secure hardware monitoring frameworks like d-GUARD. The TEAL lab explores emerging technologies to bridge exascale computing and energy efficiency challenges.
Gianluca Mittone is a postdoctoral researcher at the University of Turin's Computer Science Department, affiliated with the Parallel Computing group. His work bridges High-Performance Computing (HPC) and Artificial Intelligence (AI), focusing on Federated Learning (FL) as a privacy-preserving, scalable solution for AI applications. Co-Principal Investigator for FL-as-a-Service platform in TIM Edge & Cloud Continuum IPCEI project Recipient of HPC-Europa3 and EuroPar Foundation awards Research interests center on FL deployment in HPC/cloud environments , including RISC-V hardware exploration for decentralized AI, cross-facility FL workflows, and HPC benchmarking. Publications demonstrate expertise in privacy-preserving AI , edge inference , and medical applications like cardiovascular diagnostics through machine learning. Article analysis reveals integration of HPC systems with emerging AI architectures (including Large Language Models), with subfields spanning confidential FL , drug-target interaction , survival analysis , and RISC-V AI frameworks . Awards highlight recognition in both HPC and FL domains, while collaborations with Telecom Italia and participation in TEXTAROSSA project underscore industry-academia impact. HPC-Europa3 scholarship EuroPar foundation studentship Best PhD Symposium Award (EuroPar 2023) PRAISE Score endorsed by European Society of Cardiology (2023 guidelines)
Miltiadis Moralis-Pegios is a Lecturer at the Department of Informatics, School of Informatics, Aristotle University of Thessaloniki (AUTH). He has been actively involved in academic teaching and research projects since 2002. Current Courses : Information Theory and Coding (Spring 2024–25) Research Interests : Focus on silicon photonics, neuromorphic computing, and optical networking for high-speed data centers. Applications include graphene-based secure IoT, environmental pollution detection via hyperspectral sensors, and plasmonic circuits for AI hardware. Notable Research : Participation in projects like Heterogeneously integrated photonic chiplets for AI engines , Smart environmental sensing systems , and Graphene optical platforms (2024–2027). Earlier work includes optical transceivers for data centers and flood risk management systems. Collaborations : Extensive involvement in EU-funded initiatives (EDAR, IN LIFE, HARC) and national projects (e.g., VERITAS , Archimedes ).
Michael Meidinger is a doctoral student and scientific assistant at the Chair of Integrated Systems within the TUM School of Computation, Information and Technology at the Technical University of Munich. His research focuses on chiplet architectures (interconnect design and smart functionalities) and reinforcement learning for runtime optimization of MPSoCs and autonomous driving systems. Education: B.Sc. and M.Sc. in Electrical Engineering and Information Technology (2018–2023) from TUM He contributes to projects like the BCDC chiplet-based system and the Duckietown Lab , where he develops tools for autonomous driving research, such as DuckieVisualizer. He supervises student projects in areas including interconnect protocol enhancements, robotics, and real-time object recognition.
Olivier Markowitch is a Professor at the Computer Sciences Department of the Faculty of Sciences at Université Libre de Bruxelles (Free University of Brussels). He currently serves as Dean of the Faculty of Sciences and is the university's information security advisor. Previously, he was Head of the Computer Sciences Department and co-president of the university's ethics committee. He co-founded the inter-university Master in Cybersecurity program and co-organized the Cybersecurity Research Center at ULB. His research focuses on: Design and analysis of cryptographic protocols Communication protocol security Side-channel attack methodologies Blockchain applications Hardware security (Network-on-Chip) Secure computation outsourcing Analysis of his 100+ publications reveals consistent focus on applied cryptography, with recent work emphasizing blockchain-based auction systems, hardware security for multi-core architectures, lightweight encryption for IoT devices, and theoretical advances in cryptographic protocols. His publications frequently address both theoretical foundations and practical implementations. Markowitch has supervised doctoral candidates in areas including lattice-based cryptography and secure Network-on-Chip protocols. He leads institutional cybersecurity initiatives and teaches courses in algorithms, cryptography, and computer security.
Maciej Besta is a leading researcher at ETH Zurich's Institute for Computing Platforms, where he heads research initiatives at the Scalable Parallel Computing Lab (SPCL) and contributes to the ETH Future Computing Laboratory (EFCL). Working under the mentorship of Professor Torsten Hoefler, he has established himself as a prominent figure in high-performance computing, graph processing, and large language models. Position: Researcher at Institute for Computing Platforms, ETH Zurich Research Leadership: Head of Sparse Graph Computations and Large Language Models Research at SPCL Collaboration: Leads project management for SPCL's contributions to ETH Future Computing Laboratory Besta's research spans multiple abstraction levels, from hardware and network topologies to middleware, algorithms, and programming models. His primary focus areas include graph-enhanced language models, graph neural networks, graph databases, and sparse models, with applications across various computational settings. He approaches these problems through rigorous performance modeling and formal reasoning, emphasizing both scalability and practical implementation. His recent publications reveal a clear trend toward integrating graph structures with language models and AI systems. Besta has pioneered work on graph databases, knowledge graphs of thoughts, and higher-order graph neural networks, while maintaining his strong foundation in high-performance computing and network topology design. His research bridges traditional HPC with cutting-edge AI, creating novel approaches for efficient large-scale computation. IEEE TCSC Award for Excellence in Scalable Computing (Early Career, 2023) Multiple Best Paper Awards at Supercomputing conferences (2022, 2023) ACM SIGHPC Doctoral Dissertation Award (2022) ETH Medal for outstanding doctoral thesis (2021) Fellow of The Explorers Club (2022) Besta actively mentors ETH Zurich students through semester projects, Bachelor's, and Master's theses, focusing on graph processing and related computer science challenges. His mentorship extends beyond technical guidance, incorporating lessons from his extensive polar and mountaineering expeditions that emphasize mental resilience, efficient risk management, and leadership. He has supervised numerous student projects that have resulted in high-impact publications at top-tier conferences. As a core member of the Scalable Parallel Computing Lab, Besta collaborates with researchers across ETH Zurich and international institutions. His unique approach integrates insights from extreme environment expeditions into research methodology, creating a distinctive framework for tackling complex computational problems. The lab's work under his leadership spans theoretical modeling, practical implementation, and real-world deployment of high-performance systems.
