Juan Manuel Cebrian Gonzalez is an Assistant Professor at the Department of Computer Engineering and Technology, Faculty of Informatics, University of Murcia. His work focuses on computer architecture, parallel systems, and energy-efficient computing. Doctorate: University of Murcia (2011), thesis on fine-grain power and thermal management in multicore processors. Research interests: Designing architectural mechanisms for optimizing power consumption and thermal management in multicore systems, cache coherence in parallel architectures, and vectorization techniques for high-performance computing. His work also explores heterogeneous architectures, fault tolerance, and efficient memory systems. Recent article trends: Focus on cache management, speculative execution, lock-free constructs, and performance-energy trade-offs in edge and heterogeneous computing. Key methodologies include gem5 simulation, Arm SVE, and AVX-512 vectorization. Collaboration: Supervised by Dr. Juan Luis Aragón Alcaraz and Dr. Stefanos Kaxiras. Active in the Computer Architecture and Parallel Systems research group.
Alberto Ros is a Full Professor at the University of Murcia , Spain, in the Computer Engineering Department (DITEC) . His work focuses on cache coherence , memory hierarchy designs , memory consistency , and processor microarchitecture , with over 100 peer-reviewed publications. Dr. Ros earned his MS (2004) and PhD (2009) in Computer Science from the University of Murcia. He interned at the School of Informatics, University of Edinburgh , and held postdoctoral positions at the Technical University of Valencia and Uppsala University . He is an IEEE Senior Member . Research interests include optimizing hardware for multicore systems. His work spans cache coherence protocols, transactional memory, speculative execution, and data/instruction prefetching techniques. He led the ERC Consolidator Grant (2018) and ERC Proof of Concept Grant (2023) to improve multicore architecture performance. Recent publications emphasize hardware transactional memory efficiency, speculative execution, and secure cache systems. Notable works include cache locking, memory dependency prediction, and fine-grain coherence protocols. Scientific awards : Inducted into the MICRO Hall of Fame ISCA Hall of Fame 27 HiPEAC paper awards (MICRO, ISCA, HPCA, ASPLOS) Winner, ML-based Data Prefetching Competition Winner, 1st Instruction Prefetching Championship IEEE MICRO TopPicks for ISCA'17, MICRO'21 (honorable), MICRO'16 (honorable) Best paper awards at HiPC'16, FORTE'16 Honorable mention at HPCA'24 Nomination at ISCA'22 Grants as Principal Investigator include ERC Proof of Concept (2023) ERC Consolidator (2018) Europe Excellence (2018) Seneca Foundation, Young Leaders in Research (2014) . Dr. Ros is affiliated with the Computer Architecture and Parallel Systems Group (CAPS) at the University of Murcia and previously with UPMARC at Uppsala University.
Antonio Maria Gonzalez Colas is a Full Professor at the Universitat Politècnica de Catalunya (UPC), affiliated with the Department of Computer Architecture within the Faculty of Computer Science of Barcelona (FIB). He leads the ARCO research group focused on Microarchitecture and Compilers and is actively engaged in high-impact research in computer architecture, GPUs, and energy-efficient computing. His collaborations extend to the Barcelona Supercomputing Center and various national and European research initiatives. Research Interests: His primary research areas include computer architecture, microarchitecture, compilers, GPUs, and processor design. He focuses on energy-efficient computing, deep neural network (DNN) accelerators, GPU simulation and optimization, memory systems, and architectural support for machine learning and autonomous systems. His work often integrates compiler techniques with hardware design for performance and efficiency. Scientific Production Trends: His recent publications demonstrate a strong focus on energy-efficient hardware for AI workloads, particularly DNN and speech recognition acceleration, GPU architectural innovations, memory optimization, and real-time rendering. He frequently publishes in top-tier venues such as ISCA, MICRO, HPCA, and IEEE/ACM journals. ICREA Academia Award 2024 HiPEAC 2024 Paper Award ACM Senior Member (2020) Advising and Grants: He has advised numerous PhD students whose theses cover topics like energy-efficient architectures for autonomous driving, speech recognition, and neural networks. He leads competitive R&D projects, including an ERC Advanced Grant and projects funded by the Spanish National Program and the ICREA Academia program, focusing on domain-specific architectures and cognitive computing units. Labs and Teams: He is the principal investigator of the ARCO (Microarchitecture and Compilers) research group at UPC, a leading team in computer architecture research in Spain. The group is part of a larger collaborative network within UPC and with international partners.
Jose Luis Abellan Miguel is a Ramón y Cajal Fellow and Tenure-Track Associate Professor at the University of Murcia's Department of Computer Engineering and Technology. He leads the EcoArTech team and is a European R3 researcher. Previously, he held roles at the University of Ferrara, Boston University, and Universidad Católica de Murcia. His research focuses on GPU architectures, accelerators for machine learning, and privacy-preserving computing, particularly Fully Homomorphic Encryption (FHE). He has authored over 70 peer-reviewed publications and contributed to conferences like ISCA, HPCA, and MICRO. Education: Bachelor's, Master's, and PhD in Computer Science and Engineering (University of Murcia, 2007–2012) Research Interests: Abellan's work emphasizes architectural enhancements for GPU systems, customized accelerators for ML and FHE, and efficient synchronization/communication in many-core architectures. His contributions include tools like MGPU-Sim and STONNE for simulation, and frameworks like FIDESlib for FHE on GPUs. Recognition: HiPEAC Paper Awards (2011, 2019–2024) Top Picks in Hardware and Embedded Security 2024 European R3 Certificate (2024) Editorial roles at ACM TACO and Frontiers in Electronics Grants & Leadership: Recipient of a Ramón y Cajal fellowship and a Consolidación Investigadora grant. He chairs sessions at conferences like ISPASS and serves on TPCs for venues including DATE, HPCA, and MICRO. His lab collaborates with institutions like Georgia Tech, Northeastern University, and Intel. Labs/Teams: He leads the EcoArTech team, focusing on next-gen computing systems via architectural simulators. Collaborators include researchers from MIT, Boston University, and industry partners like NVIDIA and Intel.
Carlos Molina Clemente is an Associate Professor of Computer Architecture at Rovira i Virgili University in Tarragona, Spain. He holds a M.Sc. in Computer Engineering (Universitat Politècnica de Catalunya, 1996) and a Ph.D. in Computer Science (UPC, 2005). His research focuses on Computer Architecture, Mobile/Sensor Networks, and Cloud Computing. He leads the Cloudlab research group and coordinates initiatives like GTDAWIN and BIOGEI. Key research areas include multicore scheduling, LoRaWAN protocols, LIDAR data analysis, and serverless computing. He has published over 50 articles in top-tier conferences/journals and supervised three doctoral theses. His work spans projects on cache architectures, real-time systems, and educational multicomputing solutions. Affiliations include the Department of Computer Engineering and Mathematics (DEIM) at URV, with offices at Campus Sescelades (Avinguda Països Catalans 26, Tarragona). Research highlights include contributions to non-uniform cache policies, predictive mobile network algorithms, and energy-efficient sensor networks.
Manuel Eugenio Acacio Sanchez is a Professor in the Department of Computer Engineering and Technology at the University of Murcia's Faculty of Informatics. His research focuses on computer architecture, parallel systems, cache coherence, and hardware transactional memory. He earned his Ph.D. from the University of Murcia in 2003 with a thesis on directory-based coherence protocols for distributed-shared memory multiprocessors. Doctorate: Universidad de Murcia (2003) Academic Rank: Professor Research Interests include Hardware transactional memory Cache coherence protocols GPU and DNN accelerators Energy-efficient computing Parallel architectures Recent Article Trends emphasize cycle-level simulation tools (e.g., STONNE), hardware transactional memory optimizations, and neural network accelerator design. His work bridges microarchitectural improvements and application-specific efficiency in multicore systems. Labs & Teams : Affiliated with the Computer Architecture and Parallel Systems research group, previously part of the Architecture and Parallel Computing group.
Alberto Ros Bardisa is a Professor at the Department of Computer Engineering and Technology within the Faculty of Informatics at the University of Murcia. He holds a Doctorate from the same university, completing his thesis on Efficient and Scalable Cache Coherence for Many-Core Chip Multiprocessors in 2009. His research focuses on computer architecture , with particular emphasis on cache coherence protocols , hardware transactional memory , speculative execution , and many-core systems . He has contributed to optimizing memory subsystems, concurrency management, and scalability in parallel computing environments. His work often bridges hardware-software co-design to enhance performance and security in modern architectures. Dr. Ros Bardisa is affiliated with the Computer Architecture and Parallel Systems research group and previously contributed to the Architecture and Parallel Computing group. His publications (over 130+ listed) reflect a sustained focus on advancing cache efficiency, transactional memory systems, and speculative execution techniques. His current work explores innovative solutions for fine-grain coherence , secure prefetching , and atomic operation optimization , with recent contributions in 2025 addressing novel protocols like WoperTM and MASCOT.
Manuel E. Acacio is Full Professor in the Computer Engineering Department at the University of Murcia, Spain, leading the Computer Architecture & Parallel Systems (CAPS) research group. His research advances multiprocessor systems through innovations in cache coherence protocols, hardware transactional memory, and synchronization mechanisms. Recent work explores efficient concurrency management, speculative execution, and hardware support for deep neural networks.
Ricardo Fernández Pascual is an Associate Professor at the Computer Engineering Department (DITEC) of the Universidad de Murcia , Spain. He teaches introductory and advanced computer architecture courses like ' Estructura y Tecnología de Computadores ' and ' Organización y Arquitectura de Computadores '. His academic work focuses on computer architecture , particularly in memory hierarchies for chip multiprocessors cache coherence protocols fault tolerance energy-efficient design His PhD thesis (2009) at the Universidad de Murcia, titled ' Fault-tolerant Cache Coherence Protocols for CMPs ', was supervised by José Manuel García Carrasco and Manuel Eugenio Acacio Sánchez. He has also collaborated with institutions like Intel Barcelona Research Center and FORTH. Recent research trends in his publications include optimizing coherence directories for manycore scalability hybrid photonic-electronic interconnects fault-tolerant mechanisms in CMP architectures transactional memory enhancements dynamic resource management private-shared cache organization He has advised PhD student Antonio García Guirado, who completed his thesis on energy-efficient cache-coherent multi-cores in 2013. His work has been published in leading journals like IEEE Transactions on Parallel and Distributed Systems, Journal of Parallel Distributed Computing, and conferences including ICS, HPCA, and SBAC-PAD.
Juan Luis Aragon Alcaraz is a Full Professor in Computer Architecture at the University of Murcia (Spain), affiliated with the Faculty of Informatics and the Department of Computer Engineering and Technology. He obtained his PhD in Computer Engineering from the University of Murcia in 2003 and held a postdoctoral position as a Visiting Assistant Professor and Researcher at the University of California, Irvine. He has held visiting researcher positions at EPFL (2013) and Princeton University (2015–2022). His research focuses on computer architecture, emphasizing heterogeneous parallel systems, GPUs, memory hierarchies, and energy-efficient microarchitecture design. He has advised 7 PhD theses and co-authored over 60 publications in top-tier conferences and journals. His work includes contributions to GPU-accelerated medical imaging, energy-efficient graphics pipelines, and hardware-software co-design for parallel systems. Key research trends in his articles include optimizing GPU performance for real-time applications, energy efficiency in graphics rendering, and scalable latency tolerance in manycore systems. His patents include innovations in presbyopia correction devices leveraging GPU and FPGA technologies. Dr. Aragón has taught numerous courses in computer architecture and design, including Computer Architecture and Organization, Advanced Aspects in Multicore Architectures, and Embedded Systems Technologies. His labs and collaborations span academic-industrial partnerships, emphasizing practical applications of his theoretical contributions.
Adria Armejach Sanosa is a Senior Lecturer in the Department of Computer Architecture at the Faculty of Computer Science of Barcelona (FIB), Universitat Politècnica de Catalunya (UPC). He is also affiliated with the Barcelona Supercomputing Center (BSC-CNS), a leading institution in high-performance computing in Europe. His research spans computer architecture, high-performance computing, memory systems, and hardware acceleration for genomics and machine learning. PhD from UPC His research interests focus on optimizing computer systems for performance and efficiency, particularly in the areas of hardware transactional memory, cache optimization, RISC-V architectures, and acceleration of bioinformatics workloads. He investigates how to improve data movement, prefetching, and parallelism in large-scale heterogeneous systems. His work combines architectural innovations with practical implementations on real-world HPC platforms. The most recent articles reflect a strong trend towards high-performance computing for genomics, sparse data handling, and efficient hardware/software co-design. Topics include genomics benchmarking on ARM processors, tensor marshaling, RTL simulation scalability, and low-precision training for deep neural networks. These works demonstrate a consistent focus on bridging architectural research with real-world applications in science and AI. HiPEAC Paper Award 2024 HiPEAC Paper Award Armejach has advised several doctoral students, including J. Pavón, G. López, and J. Osorio. He has been involved in numerous competitive R&D+i projects such as Digital Autonomy for RISC-V in Europe, Laboratorio Zettaescala de Barcelona, and Genome Analysis Acceleration on HPC Architectures. These projects are often funded by national and European programs, indicating strong recognition and support for his research. He collaborates extensively within the CAP (High-Performance Computing) research group and with key figures like Miquel Moreto, Mateo Valero, and Osman Unsal. He is a member of the CAP research group and contributes to initiatives like the Laboratory for Open Computer Architecture and systems (RISC-V Chip Development) and the Barcelona Zettascale Lab. These labs focus on open hardware, European technology sovereignty, and next-generation supercomputing. His work on Metro-MPI for RTL simulation and hardware accelerators for databases highlights his contributions to both design automation and data-intensive computing.
