Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He previously served as an Assistant Professor at Georgia Tech (2013-2017) and holds the Halicioğlu Chair in Computer Architecture . As founder/director of the Alternative Computing Technologies (ACT) Laboratory and associate director of UCSD's Center for Machine Integrated Computing and Security (MICS) , his research drives cross-stack solutions for next-generation computer systems. Early tenure recipient at UCSD Coined the term "dark silicon" in computer architecture Developed Tabla/DnnWeaver open-source frameworks Research Interests span: Approximate Computing Neural Acceleration FPGA/ASIC Hardware Design Machine Learning Systems Dark Silicon Challenges Security/Privacy in Accelerated Systems Scientific Recognition : 4 CACM Research Highlights 4 IEEE Micro Top Picks Distinguished Paper Award (HPCA 2016) Inducted to ISCA Hall of Fame (2018) Teaching : Developed courses on accelerator design (CSE 240D) and alternative computing (CS 8803 ACT) Advocates for hands-on FPGA-based learning in Processor Design with FPGAs courses
Brandon Reagen is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University's Tandon School of Engineering, with affiliations in Computer Science, the Center for Advanced Technology in Telecommunications (CATT), and the NYU Center for Cybersecurity (CCS). He holds a PhD in Computer Science from Harvard (2018) and undergraduate degrees in Computer Systems Engineering and Applied Mathematics from the University of Massachusetts, Amherst (2012). His research focuses on computer architecture, hardware acceleration for deep learning and privacy-preserving computation, and VLSI design. He pioneered efficient deep learning accelerator designs through unsafe optimizations and contributed to benchmarking frameworks like Aladdin and MachSuite. His work spans privacy-preserving machine learning, secure computing systems, and hardware-software co-design for cryptographic protocols. Key achievements include the NSF CAREER Award (2024) and Siebel Scholar recognition (2018). His research centers on advancing secure computing through innovations like zero-knowledge proof accelerators (e.g., zkSpeed), fully homomorphic encryption frameworks (Orion), and entropy-guided privacy techniques for large language models. He leads interdisciplinary efforts at CATT and CCS to bridge hardware design and cybersecurity challenges. Reagen's contributions include over 50 publications in top-tier conferences (e.g., ISCA, ASPLOS, MLSys) and industry collaborations at Facebook AI. His work emphasizes practical solutions for encrypted computation efficiency, privacy-preserving inference, and scalable secure systems.
Prof. Dr. Tobias Gemmeke is a University Professor at RWTH Aachen University's Faculty of Electrical Engineering and Information Technology, leading the Chair of Integrated Digital Systems and Circuit Design. His work focuses on neuromorphic computing, hardware accelerators, and energy-efficient electronics. He has pioneered advancements in FPGA-based computational neuroscience simulators, neuromorphic processor architectures, and sensor integration for industrial and medical applications. Research interests include time-domain computing, ReRAM reliability, and co-optimization of neural networks with hardware. Notable contributions include the neuroAIx framework for accelerated neuroscience simulations and energy-efficient ASIC designs for post-quantum cryptography. He actively explores memristive devices and domain generalization techniques for edge computing. Recent publications highlight innovations in spiking neural networks, sensor systems for plain bearings, and time-domain compute-in-memory engines. His work bridges theoretical neuroscience with practical hardware implementations, emphasizing scalability and real-time performance.
Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.
Dr. Ameer Abdelhadi is an Assistant Professor in the Department of Electrical and Computer Engineering at McMaster University. His research focuses on application-specific custom-tailored computer architectures, hardware-efficient deep learning, neurotechnology, and reconfigurable computing. He holds a PhD from the University of British Columbia and has held academic positions at the University of Toronto, Imperial College London, and Simon Fraser University, alongside industry experience in semiconductor design. Education: PhD in Computer Engineering (University of British Columbia, 2016). Research Interests: Hardware acceleration for machine learning and neurotechnology Reconfigurable computing and FPGAs/ASICs Asynchronous circuits and synchronization protocols VLSI physical design and CAD algorithms Publications span high-impact venues such as IEEE Journal of Solid-State Circuits, IEEE Hot Chips, and IEEE Micro. Notable achievements include the 2017 Best Paper Award at ASYNC for work on synchronization FIFOs. Teaching includes COMPENG 4DV4 (VLSI System Design) and ELECENG 4OI6B (Engineering Design). His lab focuses on advancing hardware systems for next-generation applications in AI and biomedical engineering.
Lisa Wills serves as Assistant Professor of Computer Science at Duke University's Trinity College of Arts & Sciences and holds a joint appointment in Electrical and Computer Engineering at the Pratt School of Engineering since 2019. Her research bridges computer architecture and domain-specific applications, with a focus on hardware acceleration for computationally intensive fields. Dr. Wills earned her Ph.D. from Columbia University in 2014. Her academic journey reflects a deep commitment to advancing hardware-software co-design methodologies for real-world computational challenges. Her research centers on developing efficient hardware accelerators for big data analytics, particularly in genomics, graph processing, and database systems. She pioneers frameworks that simplify accelerator deployment while tackling critical bottlenecks in genomic data analysis, protein structure prediction, and privacy-preserving computing. Current work focuses on hardware-aware machine learning systems and energy-efficient architectures for emerging AI applications. Analysis of her publication record reveals a clear trajectory: from foundational work in database processing units (2014-2016) to specialized genomic accelerators (2019-2021), then evolving toward ML-enhanced design automation (2022-2023) and cutting-edge architectural abstractions (2024-2025). Her research consistently targets the intersection of hardware efficiency and domain-specific computational demands, with increasing emphasis on AI/ML workloads. Google ML and Systems Junior Faculty Award (2025) Dr. Wills actively mentors doctoral students including Chris Kjellqvist (lead architect of Beethoven accelerator framework), Mason Ma (PyTFHE FHE framework), and Mansi Choudhary (COCOSSim accelerator simulator). Her research is supported by significant grants including the NSF AI Institute: Athena ($20M, 2021-2027), Meta-funded ProSE accelerator project (2023-2026), and NSF CAREER award (2021-2026), totaling over $25M in active funding. She directs the APEX Lab (Application-driven Programmable Efficient Accelerated Systems), which develops open-source frameworks like Beethoven for FPGA/ASIC accelerator deployment and focuses on lowering barriers for non-hardware researchers to leverage custom acceleration in genomics, AI, and big data applications.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Giovanni De Micheli is a Professor of Electrical Engineering and Computer Science at EPF Lausanne, Switzerland. He also serves as Director of the Integrated Systems Centre and the Institute of Electrical Engineering at EPFL, and chairs the Scientific Committee of CSEM in Neuchatel. Previously, he held academic roles at Stanford University for 18 years, including Full Professor, Associate Professor, and Assistant Professor in the Department of Electrical Engineering. His research spans synthesis of digital circuits, hardware/software co-design, low-power design, and Networks on Chip (NoC) technology. 2003: IEEE Emanuel Piore Award 2000: Golden Jubilee Medal of the IEEE CAS Society 2000: ACM Fellow 1994: IEEE Fellow 1990: IEEE/CS Distinguished Service Award 1988: NSF Presidential Young Investigator Award His seminal contributions include pioneering C-based synthesis and Boolean matching algorithms for digital circuits, foundational work in dynamic power management using stochastic control, and the development of Network-on-Chip (NoC) technology. His publications, such as "Networks on Chips: A New SoC Paradigm" and "Dynamic Power Management for Portable Systems" , have shaped modern SoC design practices. With over 400 technical articles, 9 books, and an H-index of 56, his work remains highly influential.
Andrea Costamagna is a researcher affiliated with the École Polytechnique Fédérale de Lausanne (EPFL), working within the School of Computer and Communication Sciences and the Department of Communication Systems. His research focuses on logic synthesis, digital circuit design, and the intersection of machine learning with hardware implementation. His work includes optimizing digital circuits using techniques like resynthesis, resubstitution, and decomposition, with applications in FPGA design and low-power systems. Recent publications explore symmetry-based synthesis, glitch-aware power minimization, and the use of resistive switching devices in machine learning hardware. His research also extends to quantum physics modeling with deep learning.
Weiwen Jiang is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at George Mason University (GMU), affiliated with the College of Engineering and Computing (CEC). He leads the JQub lab, focusing on hardware/software co-design for computing systems, spanning classical (FPGAs, ASICs) and quantum computing applications in AI-driven fields like medical imaging and geophysics. Prior to GMU, he held a postdoctoral position at the University of Notre Dame and earned his PhD in Computer Science from Chongqing University with a joint PhD in Electrical and Computer Engineering from the University of Pittsburgh. His research emphasizes quantum computing, AI accelerators, and domain-specific computing. Notable achievements include the 2025 NSF CAREER Award, ACM Sigda Meritorious Service Award (2024), and IEEE QuantumWeek Best Paper Award (2023). His work is funded by NSF, DoE, ARO, Meta, and Leidos. He co-chaired IEEE QuantumWeek (2023–2025) and created workshops like StableQ at ESWEEK 2023. Key contributions include developing frameworks like QuPAD for quantum learning and JQub's AI-driven geophysical and medical imaging tools. His lab graduated Dr. Yi Sheng (now at University of South Florida) and Dr. Zhepeng Wang (Amazon Applied Scientist). Current research explores quantum machine learning, noise mitigation, and fairness in AI for edge devices.
Thuy T. Le is a Professor of Electrical Engineering at San Jose State University's College of Engineering. With a distinguished career spanning several decades, he teaches graduate and undergraduate courses in digital system design, computer architecture, microprocessor systems, and related fields. His academic journey began with earning B.S., M.S., and Ph.D. degrees from the University of California, Berkeley. Professor Le's research interests encompass a broad spectrum of cutting-edge technological domains. His primary focus areas include System-on-Chip (SoC) and Embedded System Design, Hardware Accelerators for complex algorithms, Quantum Computing, implementation of Probability theory and Monte Carlo simulation, and radiation effects on electronic devices and systems. His work bridges traditional electrical engineering with emerging computational paradigms, demonstrating a consistent ability to adapt to evolving technological landscapes while maintaining strong foundations in core engineering principles. Analysis of Professor Le's publication record reveals a consistent trajectory from nuclear reactor physics and computational methods toward modern hardware acceleration and quantum computing. His early work focused on nuclear reactor simulation and radiation shielding, then evolved to parallel computing and distributed systems, and has recently centered on hardware acceleration for complex algorithms, quantum computing applications, and AI hardware. This progression demonstrates his ability to transition between major technological paradigms while maintaining expertise in computational methods and hardware implementation. Professor Le has demonstrated significant leadership in professional service, having served as keynote speaker, general chair, technical program chair, session chair, reviewer, and committee member for numerous international conferences. His service extends beyond academia through his role as Co-Founder and Advisor of the Vietnamese Strategic Ventures Network and Chairman of the Board of the United States–Vietnam Foundation. In his educational role, Professor Le has made substantial contributions to engineering curriculum development and assessment. He has taught a wide range of courses including EE271 (Advanced Digital System Design), EE210, EE250, and various project/thesis courses. His research advising spans digital system design, ASIC, SOC, and hardware accelerators. He has also collaborated with local companies on projects related to high-performance system architectures, parallel algorithms, digital arithmetic, and System-on-Chip verification.
Professor Ahmet Bindal is a faculty member in the Department of Computer Engineering at San José State University . He earned his B.S. in Electrical Engineering from Bogazici University, Turkey, followed by M.S. and Ph.D. degrees from the University of California, Los Angeles. Industry Experience : 20 years at IBM, Intel, Philips, and Cadence Design Systems. Current Research : Nano-scale electron devices, silicon nanowire transistors, robotics, and VLSI architecture. Research Trends : His work focuses on silicon nanowire transistors for VLSI, FPGA, and robotics. Key themes include low-power/high-speed integrated circuits , dynamic logic design , neuromorphic engineering , and advanced semiconductor processing . Patents and Publications : He holds four U.S. patents (three with IBM, one with Intel). His 30+ journal and conference publications span nanowire transistors, FPGA architecture, robotics, and semiconductor process modeling. Teaching Contributions : Developed an undergraduate System-on-Chip (SoC) course and a MOSFET design laboratory at SJSU. Books Authored : Fundamentals of Computer Architecture and Design (Springer, 2017). Electronics for Embedded Systems (Springer, 2017). Silicon Nanowire Transistors (Springer, 2017).
Kia Bazargan is an Associate Professor and the Leroy and Ruth Fingerson Co-op Professor at the University of Minnesota, College of Science and Engineering. He currently serves as Director of the Co-op Program and focuses on VLSI-CAD, FPGA physical design, and hybrid binary-unary computing. University: University of Minnesota School: College of Science and Engineering Department: Electrical and Computer Engineering His research emphasizes stochastic computing and unary computing, where numbers are encoded as streams of bits. He explores techniques to reduce hardware costs while maintaining efficiency, particularly for edge computing and neural network applications. Recent publications highlight his work on hybrid binary-unary computing, FPGA-based inference acceleration, and lossless compression of lookup tables. Grants from Cisco Systems and the National Science Foundation support his projects. Scientific Awards: PFI-TT Grant (2020-2024): Commercializing hybrid computing for modern applications Uniqomp NSF Grant (2020-2021) EAGER Grant (2015): Studying complex dynamical systems His lab (4-162 EE/CSci) investigates scalable computing paradigms to bridge the gap between ASICs and FPGAs in performance and energy efficiency.
Prof. Dr.-Ing. Marc Reichenbach serves as the Chair of Integrated Systems at the Institute for Applied Microelectronics and Data Technology at the University of Rostock. His office is located at Albert-Einstein-Straße 26, 18059 Rostock, Room 102 (1st floor), with contact information including telephone (0381) 498 7270 and email marc.reichenbach@uni-rostock.de. Professor Reichenbach's research focuses on the intersection of hardware design and artificial intelligence, with particular expertise in memory technologies and computing architectures. His work spans several key areas: Development of specialized computer architectures for deep learning applications Advanced VLSI design and CPU architecture Emerging memory technologies, particularly RRAM (Resistive Random-Access Memory) FPGA-based acceleration systems Hardware implementations for neural networks and AI applications Analysis of Professor Reichenbach's recent publications (2023-2025) reveals a strong focus on memory computing technologies, particularly RRAM-based systems. His work demonstrates expertise across multiple dimensions of computer architecture including ASIC design, FPGA acceleration, and novel memory systems. The publications show a clear trajectory toward implementing AI and machine learning capabilities directly in hardware, with applications ranging from edge computing to satellite systems. A significant portion of his recent work addresses the challenges of implementing neural networks using emerging memory technologies, focusing on efficiency, reliability, and performance optimization. Professor Reichenbach teaches several advanced courses including: Computer architectures for deep learning applications Project seminar Embedded Systems Advanced VLSI Design (Advanced CPU Design) His research group appears to be actively engaged in several cutting-edge projects related to hardware acceleration for AI applications, memory computing, and embedded systems design. The group collaborates on projects involving digital twins for hardware systems, real-time operating systems for heterogeneous architectures, and specialized computing systems for various applications from medical devices to drone technology.
