Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.
Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.
Prof. Dan Jiao is the Synopsys Professor of Electrical and Computer Engineering at Purdue University's Elmore Family School. She leads the Rapid-Heterogeneous Integration (Rapid-HI) Design Institute and serves as Editor-in-Chief of the IEEE Journal on Multiscale and Multiphysics Computational Techniques. Her research focuses on computational electromagnetics, multiphysics modeling, and AI-driven design automation for advanced integrated circuits and quantum systems. She has held academic positions since 2005, progressing from Assistant to Full Professor, and has extensive industry experience at Intel Corporation (2001–2005). Education: PhD in Electrical Engineering, University of Illinois at Urbana-Champaign (2001) Senior Staff Engineer at Intel Corporation (2001–2005) Research Interests: Fast numerical methods for large-scale electromagnetic analysis AI/ML integration in design automation (EDA/MDA) Quantum circuits and spin qubit systems Heterogeneous integration and advanced packaging Multiphysics co-simulation for nano-scale devices Signal/power integrity in high-speed systems Key Projects: Leads the NSTC AIDRFIC program (first NSTC R&D Jump Start project), the DARPA NGMM Rapid-HI Design Institute, and the GENIE-RFIC generative design tool initiative. Also directs the Consortium for Electromagnetic Science and Technology. Awards & Honors: 2022 ACES Computational Electromagnetics Award IEEE Fellow (2016) Intel Outstanding Researcher Award (2019) MTT-S Distinguished Microwave Lecturer (2020–2023) 2013 Schelkunoff Prize Paper Award Advising & Grants: Advised over 30 PhD/master's students and led projects funded by NSF, DARPA, Intel, SRC, and industry partnerships. Key grants include NSF CAREER (2008), ONR Young Investigator (2006), and multiple industry-sponsored initiatives. Labs & Teams: Rapid-HI Design Institute (DARPA NGMM) Quantum device co-design group Multiphysics modeling team
Aman Arora is an Assistant Professor at Arizona State University's Ira A. Fulton Schools of Engineering, specializing in the School of Computing and Augmented Intelligence. His research focuses on reconfigurable computing, hardware acceleration of machine learning, and non-traditional computing paradigms like Processing-In-Memory. With over a decade of semiconductor industry experience, he bridges academic research and industrial applications. PhD in Computer Science from The University of Texas at Austin Research interests emphasize domain-specific acceleration through FPGA optimization , compute-in-memory architectures , and machine learning for CAD/EDA . His work addresses critical challenges in energy efficiency and throughput for AI workloads. Recent publications demonstrate trends toward compute-in-memory systems , FPGA-based deep learning acceleration , and sustainable hardware design . Key contributions include frameworks like SAF, CSR, and GAMA for dynamic hardware optimization. Laboratory Website: ADVENT Lab Teaching includes courses on digital hardware design (CSE 320) and advanced topics in machine learning acceleration (CEN 524/CSE 524). Industry experience informs his practical approach to research and education.
Ningyuan Cao is an Assistant Professor in the Department of Electrical Engineering at the University of Notre Dame, College of Engineering. He leads the Circuit and System Intelligence Research Lab , focusing on the intersection of advanced hardware design and real-time/low-power machine learning applications. Education : Ph.D., Electrical and Electronics Engineering, Georgia Institute of Technology (2020) M.S., Electrical Engineering, Columbia University (2015) B.S., Electrical and Electronics Engineering, Shanghai Jiao Tong University (2013) His research investigates custom analog/mixed-signal circuits , digital architecture , and micro-system design for machine learning acceleration, distributed intelligence, and data-driven IC design automation. Key application domains include Internet-of-Everything, tactile internet, and mixed reality systems. Recent publications highlight work on Bayesian neural networks , privacy-preserving bio-signal encoders , transformer-based surrogate models , and compute-in-memory architectures . Technical themes span neuromorphic computing, uncertainty quantification, and hardware security.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Lisa Wu Wills is an Assistant Professor in the Department of Computer Science and Electrical and Computer Engineering at Duke University, leading the APEX Lab (Application-driven Programmable Efficient Accelerated Systems Lab). Her research focuses on hardware acceleration for big data analytics in genomics, graphs, and databases to advance healthcare and natural sciences. Education: Ph.D. in Computer Science, Columbia University, 2014 Research Interests: Dr. Wills pioneers computer architecture and hardware-software co-design to create efficient accelerators for emerging applications. Her work targets genomics , graph analytics , and database systems , emphasizing simplified hardware deployment and energy efficiency for scientific breakthroughs in healthcare and AI. Publication Trends: Her 2022-2025 publications reveal a strong focus on open-source frameworks (Beethoven, PyTFHE) for accelerator development, hardware acceleration in privacy-preserving computing, and optimization for large language models. Key themes include transfer learning for EDA, domain-specific architectures for genomics, and energy-efficient image processing. Scientific Awards: Google ML and Systems Junior Faculty Award (2025) Advising and Grants: Dr. Wills mentors three PhD students: Chris Kjellqvist (Beethoven framework architect), Mason Ma (PyTFHE lead for FHE applications), and Mansi Choudhary (COCOSSim simulator creator). Her 2025 Google award funds research on accelerating vector databases and retrieval-augmented generation for LLMs. Labs and Teams: She directs the APEX Lab at Duke, developing tools like Beethoven (open-source accelerator composer) and PyTFHE for hardware-software integration, enabling domain scientists to leverage custom acceleration with minimal hardware expertise.
Dr. Yiran Chen is the John Cocke Distinguished Professor at Duke University's Department of Electrical and Computer Engineering, leading the NSF AI Institute for Edge Computing (Athena) and the Duke Center for Computational Evolutionary Intelligence (DCEI). A global leader in neuromorphic computing, emerging memory systems, and edge AI, he holds prestigious roles including IEEE Fellow and Editor-in-Chief of IEEE Transactions on Circuits and Systems for AI. His research spans machine learning accelerators, security-hardened hardware, and co-design of EDA tools with LLMs. With over 700 publications and 96 patents, he has been awarded 15 paper awards and 17 nominations, including rare Technical Achievement Awards from IEEE societies. He advises over 60 PhD students and 4 postdocs, many of whom hold academic positions worldwide. His work bridges academia and industry, contributing to startups and venture capital through his board roles. Education: B.S. (Tsinghua, 1998) → M.S. (Tsinghua, 2001) → Ph.D. (Purdue, 2005). Career path: Assistant/Associate Professor at University of Pittsburgh (2010–2014) → Duke since 2014. Awards include the ACM SIGDA Outstanding New Faculty Award (2014), NSF CAREER Award (2013), and the Stansell Family Distinguished Research Award (2022). Research focuses on innovations in: (1) Non-volatile memory architectures for AI acceleration, (2) Hardware-software co-design for edge computing, (3) Security in neuromorphic systems, and (4) Large-scale ML for EDA. His group pioneered ReRAM-based accelerators like ReBNN and MARC, and introduced novel edge AI frameworks like Ecco and Prosperity. These works address scalability, energy efficiency, and real-time performance challenges. Key initiatives include the NSF IUCRC for Alternative Sustainable & Intelligent Computing (ASIC), advancing sustainable computing through novel materials and architectures. His leadership in standard-setting bodies like the IEEE Circuits and Systems Society ensures cutting-edge research translates into industry practices. Grants: Lead PIs for multiple NSF AI Institutes and industry partnerships. Labs: Directs the Athena Institute and DCEI, fostering collaboration between academia and industry. Current projects include quantum computing placement algorithms (QPlacer), federated learning frameworks (FedGPT), and neuro-symbolic architectures.
Georges Gielen is Full Professor in the Department of Electrical Engineering (ESAT) at KU Leuven, Belgium, and part-time Research Director at imec. He has held multiple leadership roles including Chair of ESAT Department (2012-2013, 2020-2024) and Vice-Rector for Science, Engineering & Technology (2013-2017). His academic career spans over 30 years at KU Leuven, progressing from Assistant to Full Professor. His research focuses on analog and mixed-signal integrated circuit design automation , with expertise in CAD tools, design optimization, sensor interfaces, and neuromorphic systems. His work bridges hardware design with machine learning, particularly in hardware-efficient AI implementations and biomedical applications. He has pioneered techniques for automated analog circuit sizing, topology synthesis, and reliability-aware design in nanometer CMOS. Gielen has received numerous accolades including the IEEE CAS Mac Van Valkenburg Award (2015), IEEE CAS Charles Desoer Award (2020), and EDAA Achievement Award (2021). He holds an ERC Advanced Grant AnalogCreate and is an IEEE Fellow since 2002. As a prolific scholar, he has chaired major conferences including DATE (2006), ICCAD (2007), and ESSCIRC (2017). He has graduated over 55 PhD students through the MICAS research group at KU Leuven, currently supervising 13 doctoral candidates. His research team collaborates extensively with imec and industry partners on cutting-edge projects in carbon-aware AI accelerators, uncertainty-aware design, and neuromorphic sensor interfaces.
Siddharth Garg is the Institute Associate Professor of Electrical and Computer Engineering at NYU Tandon School of Engineering, leading the EnSuRe Research Group. He holds a Ph.D. from Carnegie Mellon University (2009) and a B.Tech. from IIT Madras. His research focuses on secure and energy-efficient computing systems, integrating machine learning, cybersecurity, and hardware design. He previously held roles as Assistant Professor at NYU Tandon (2014-2020) and the University of Waterloo (2010-2014). Key affiliations include NYU Center for Cybersecurity (CCS), NYU Wireless, and the Center for Advanced Technology in Telecommunications. His work has been recognized with prestigious awards like the NSF CAREER Award (2015) and inclusion in Popular Science’s 'Brilliant 10' (2016). Notable research includes private inference optimization, secure hardware IP protection, and adversarial machine learning defenses. Publications highlight advancements in zero-knowledge proofs, AI-driven chip design, and mitigating backdoor attacks in neural networks. His grants include funding from NYU Wireless and NSF initiatives like the Chips4All project. The EnSuRe group emphasizes bridging software and hardware design gaps using AI and fostering cybersecurity education.
Shakil Mahmud is a Visiting Assistant Professor in the Department of Electrical and Computer Engineering at the University of Mississippi. His research focuses on medical device security, embedded systems, and hardware security for cyber-physical systems. He holds a B.S. in Electrical Engineering from Ahsanullah University of Science and Technology (2015) and a Ph.D. in Computer Science and Engineering from the University of South Florida (2023). His recent work emphasizes enhancing safety and reliability in closed-loop medical systems through biosignal modeling, hardware emulation platforms (PEP), and trojan resilience strategies. He explores design trade-offs in bioimplantable devices and efficient implementations of AI architectures on constrained platforms. Key research themes include FPGA security, IoT medical device reliability, and false alarm mitigation in IoMT systems. His publications span topics like hardware obfuscation, real-time biomedical signal processing, and neural network optimization for embedded systems.
Mehdi Sadi is an Assistant Professor of Electrical and Computer Engineering at Auburn University's College of Engineering. He holds a Ph.D. from the University of Florida, an M.S. from the University of California-Riverside, and a B.S. from Bangladesh University of Engineering and Technology. His research focuses on secure and reliable system-on-chip design, AI/ML-driven VLSI CAD/EDA, neuromorphic hardware, and emerging post-CMOS computing technologies. Notable achievements include earning the NSF CAREER Award for chiplet-based design optimization and a $175k NSF grant for magnetic RAM research. His work integrates machine learning with hardware co-design to enhance AI accelerators' performance, energy efficiency, and security. Recent projects include adversarial attack mitigation on AI hardware and reliability analysis of neuromorphic systems. Dr. Sadi's contributions span chiplet architecture, memory systems (e.g., STT-MRAM/SOT-MRAM), and fault-tolerant computing. He actively publishes on topics like skyrmion logic gates and TRNG implementations using MRAM. His work bridges theoretical machine learning advancements with practical hardware implementations, addressing critical challenges in next-generation computing systems.
University of Maryland, Baltimore CountyUnited States
Riadul Islam serves as an Assistant Professor in the Department of Computer Science and Electrical Engineering at the University of Maryland, Baltimore County (UMBC), maintaining his primary office in room 316 of the Information Technology and Engineering (ITE) Building. His academic appointment focuses on hardware design and verification within the institution's engineering framework. His educational qualifications include: Ph.D. in Computer Engineering from UCSC (2017) M.A.Sc. in Electrical and Computer Engineering from Concordia University, Montreal (2011) B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (2007) Professor Islam's research centers on VLSI CAD tools and low-power digital/mixed-signal IC design , with significant contributions to current-mode clock networks, vehicular security systems, and error-robust circuit architectures. His work increasingly integrates machine learning for design automation while exploring neuromorphic computing applications and secure hardware implementations. This multidisciplinary approach bridges traditional IC design with modern AI-driven optimization techniques. Analysis of his 2023-2025 publications reveals three dominant research thrusts: (1) Machine learning applications in early-stage Design Rule Checking (DRC) prediction and clock network optimization, (2) Graph-based intrusion detection systems for automotive networks (particularly CAN bus security), and (3) Event-based vision systems and neuromorphic computing architectures. These areas demonstrate consistent innovation in merging hardware design with AI/ML methodologies for enhanced system reliability and efficiency. He directs the UMBC VLSI and SoC Research Group , which develops energy-efficient clocking networks, secure vehicular communication protocols, and compute-in-memory architectures. The lab maintains active collaboration with industry partners on hardware security and neuromorphic computing initiatives while supporting graduate student research in cutting-edge IC design methodologies.
Patanjali Sristi is an Assistant Professor at Augusta University's School of Computer and Cyber Sciences, specifically within the Department of Cybersecurity Engineering. Located at 100 Grace Hopper Lane in Augusta, Georgia, Dr. Sristi joined the university in January 2025 after previously working as a Postdoctoral Researcher at the University of Florida with Dr. Swarup Bhunia. Their academic journey began with a B.Tech in Electrical and Electronics Engineering from Pondicherry University in 2011, followed by both MS and Ph.D. in Computer Engineering from the Indian Institute of Technology (IIT Madras). Dr. Sristi's educational background demonstrates a strong foundation in electrical engineering and computer science, with advanced specialization in hardware security. Their Ph.D. research at IIT Madras was supervised by Dr. Kamakoti Veezhinathan, focusing on critical aspects of hardware security that would form the basis of their future research career. Dr. Sristi's research program centers on addressing one fundamental question: "How can we design, measure and build efficient and affordable security assurances for a given hardware design in the context of an untrusted supply chain while respecting the design constraints at each level of abstraction?" This research vision spans three interconnected domains: AI for System Design: Developing data models and AI techniques for next-generation hardware systems AI for Hardware Security: Creating AI models for vulnerability detection, countermeasure evaluation, and mitigation of supply chain threats Cybersecurity for AI: Establishing metrics and algorithms for secure development, deployment, and operation of AI systems Dr. Sristi's scholarly output reveals a consistent focus on hardware security challenges within the modern distributed electronics supply chain. Their work demonstrates a progression from foundational research on hardware trojans and side-channel attacks toward comprehensive frameworks addressing the emerging "zero trust" paradigm in hardware security. A notable trend is the integration of AI/ML techniques with traditional hardware security approaches, reflecting the evolving nature of security threats and countermeasures. Their publications span prestigious venues including IEEE Transactions on VLSI Systems, IEEE Transactions on Computers, and various IEEE conferences, indicating strong recognition within the hardware security community. While specific awards aren't detailed in the available information, Dr. Sristi's research impact is evident through multiple US patents (including US Patent 11,899,827 and US Patent App. 17/392,376) and invitations to deliver talks at prominent organizations including Sony Finishing School, Northrop Grumman, and IEEE events. Their work on Netflix Privacy Analysis was featured in Wired, demonstrating real-world relevance and impact. Dr. Sristi actively engages with students through courses including CSCI 8940 (Dissertation Research), CSCI 8720 (Problems in Computer & Cyber), and CSCI 7900 (Research Colloquium). Their research program appears well-supported through collaborations with major institutions and industry partners, as evidenced by workshops conducted for the Indian Army in conjunction with Pravartak and IIT Madras. These partnerships suggest substantial research funding and collaborative opportunities that enhance the educational experience for students. Though specific lab information isn't provided in the available text, Dr. Sristi's research scope suggests involvement with hardware security laboratories equipped for VLSI design, testing, and security evaluation. Their work on IoT security, hardware trojans, and supply chain security would require facilities for physical device testing, side-channel analysis, and hardware emulation. The focus on "zero trust" implementation for hardware security indicates a research environment that bridges theoretical security models with practical implementation challenges.
Xuan Zhang serves as Associate Professor in Electrical and Computer Engineering at Northeastern University, leading the Sensory AI Lab since joining in January 2024. Her research bridges computer architecture, integrated circuits, and artificial intelligence to develop miniaturized AI systems for autonomous physical platforms. She earned her PhD in Electrical and Computer Engineering from Cornell University in 2012. Her educational background forms the foundation for her interdisciplinary work spanning hardware and software co-design. Dr. Zhang's research focuses on artificial intelligence hardware, machine vision sensors, and security for autonomous systems. She pioneers techniques for efficient in-sensor computing, analog circuit optimization via machine learning, and hardware-level privacy preservation. Her work addresses critical challenges in energy efficiency, robustness, and security for edge AI deployment, particularly in resource-constrained environments like medical devices and autonomous vehicles. Analysis of her 2023-2025 publications reveals three dominant trends: (1) hardware-accelerated privacy mechanisms for sensors, (2) machine learning-driven analog circuit design automation, and (3) energy-efficient architectures for neural network inference. These works consistently target real-world applications in healthcare, autonomous systems, and semiconductor design. Her accolades include the prestigious NSF CAREER Award (2020) and leadership in a $10 million federal semiconductor initiative. She contributes to national efforts in AI-powered chip design through the National Center for the Advancement of Semiconductor Technology. Dr. Zhang advises graduate researchers in the Sensory AI Lab, securing significant funding for projects spanning hardware security, in-sensor computing, and autonomous system assurance. Her lab collaborates with federal agencies and industry partners on cutting-edge semiconductor research. The Sensory AI Lab operates at the hardware-software interface, developing novel architectures for intelligent edge devices. Current projects include optical privacy preservation, robust analog design tools, and energy modeling frameworks for in-sensor visual computing systems.
