معرفی
Yuanji Ye is a researcher at the Technical University of Munich (TUM), affiliated with the TUM School of Computation, Information and Technology and the Chair of Integrated Systems. His work focuses on advanced prefetching techniques and memory hierarchy optimization in modern processors.
- Education: PhD student at LIS (since 2024), M.Sc. in Communications and Electronics Engineering (TUM, 2021–2024), B.Sc. in Electronic Information and Science Technology (UESTC, 2017–2021).
Research interests include cache optimization, DRAM bandwidth management, and machine learning applications in prefetching mechanisms. He is actively involved in the CeCaS Project focusing on prefetcher design and has contributed to improving memory access latency through profiling-based policies.
In teaching, he supervises the Project Laboratory IC Design (since SS 2025) and guides student research projects such as Prefetching Techniques Based on Machine Learning and Profiling-based Prefetcher Design. His expertise bridges theoretical advancements with practical implementations in digital systems.
