Ramesh Harjani

Ramesh Harjani is the Edgar F. Johnson Professor in the Department of Electrical and Computer Engineering at the University of Minnesota. He maintains an active research program with numerous ongoing projects and publications, and is currently accepting PhD students. His office is located in Kenneth H. Keller Hall on the University of Minnesota campus in Minneapolis.

Dr. Harjani received his educational training at prestigious institutions globally:

• B.Tech in Electrical and Electronics Engineering from Birla Institute of Technology, Pilani, India (1982)
• MTech in Electrical Engineering from Indian Institute of Technology, New Delhi (1984)
• PhD in Electrical and Computer Engineering from Carnegie Mellon University (1989)

Professor Harjani's research focuses on analog and RF circuit design for communication systems with particular emphasis on CMOS technologies. His work spans both wireless and wired communication domains, with current efforts directed toward high-performance front-end components for broadband and multi-standard wireless systems, as well as next-generation high-speed wired communication systems. His research group also investigates specialized areas including data converters, sensor interface circuits, analog circuit synthesis, and micro-power analog design.

Recent publication trends show continued innovation in analog circuit design methodologies, with emphasis on improving performance metrics while addressing modern semiconductor challenges like FinFET self-heating effects. His work bridges theoretical circuit design with practical implementation challenges in advanced technology nodes, particularly 65nm CMOS processes. The research demonstrates strong industry relevance with applications in wireless communications, signal processing, and high-speed data conversion.

Professor Harjani leads multiple significant research projects:

• Scalable Ultra-Low Variation Analog-Time Neural Network (S-UATN) Accelerator (2025-2025)
• Passive Tile Architecture for MAX (2023-2024)
• ALIGN Analog Layout Design Suite (2023-2024)
• Automated Layout Of Analog Arrays In Advanced Technology Nodes (2022-2024)
• ALIGN: Analog Layout, Intelligently Generated from Netlists (2018-2023)

He maintains the Harjani Research Group, which collaborates extensively with industry partners including BAE SYSTEMS, NORTHWESTERN UNIVERSITY, SPAWAR, and THE NATIONAL SCIENCE FOUNDATION, demonstrating strong connections between academic research and practical engineering applications.