Luca Cassano

Luca Cassano is an Associate Professor at the Department of Electronics, Informatics and Bioengineering (DEIB) at Politecnico di Milano, Italy. He leads the Hardware Forge research group, focusing on hardware security, RISC-V processors, and reliability of deep learning systems. He earned his Ph.D. in Information Engineering from the University of Pisa (2013), with prior postdoctoral research at CNR and Politecnico di Milano. His research spans hardware Trojans, microarchitectural attacks (e.g., Spectre/Meltdown), fault-tolerant design, and radiation-hardened systems. Notable achievements include winning the TTTC's E. J. McCluskey Doctoral Thesis Award (2014) and multiple best paper awards at IEEE conferences. He teaches courses on hardware accelerators and computer fundamentals, and collaborates with industry partners like TDS-Space and ESA on satellite systems and secure RISC-V cores.

Research interests include:

• Hardware Security (Trojans, Side-Channel Attacks)
• Secure RISC-V Processor Design
• Deep Learning Reliability
• Fault-Tolerant Systems

Selected articles highlight work on benchmarking deep learning resilience, transient execution attacks on RISC-V, and radiation effects mitigation. His work bridges theory and practice, addressing challenges in embedded systems, space computing, and cybersecurity. Grants and collaborations emphasize applied research in dependable and secure embedded systems.