Christine Rochange

Christine Rochange is a Professor at the University of Toulouse, affiliated with the IRIT research lab and the TRACES research group. Her work focuses on worst-case execution time (WCET) analysis for hard real-time systems, timing predictability in parallel architectures, and time-aware hardware design. She coordinates major projects such as TOAST (a French initiative for time-oriented critical systems) and leads the TACLe project's Working Group 1 on timing models. Her research addresses challenges in multi-core WCET analysis, synchronization overhead reduction, and mixed-critical systems.

Key contributions include the OTAWA static WCET analysis toolset and foundational work on time-predictable architectures. She has supervised PhD students in areas like parallel real-time task scheduling and bus arbitration schemes. Rochange actively participates in program committees for conferences like ECRTS and RTAS, and teaches courses on computer architecture, parallel programming, and real-time systems at Université Paul Sabatier.

Her recent articles explore formal verification of processor pipelines, timing predictability in GPUs, and hardware-software co-design for embedded AI applications. She has coordinated international collaborations through projects like parMERASA (EU FP7) and W-SEPT (ANR), advancing the state-of-the-art in real-time systems predictability.