Andrew Reynolds

Andrew Reynolds is a Researcher at the University of Iowa and a core developer of the SMT solver CVC5. He is affiliated with the Computational Logic Center (CLC) at the University of Iowa.

• Research Focus: SMT solvers, unbounded strings, regular expressions, proof generation, quantified formulas, and synthesis conjectures.

Scientific Awards and Achievements:

• Best tool paper award at TACAS 2022
• Best paper award at FMCAD 2016
• First-place wins in multiple SMT and SyGuS competitions (2023, 2022, 2019, 2018, 2017)

Service and Leadership:

• Co-chair of VSTTE 2023 and SYNT 2023
• PC Member of FMCAD, IJCAR, CAV, TACAS, and others
• Board of Trustees member at CADE (2017–2023)

Labs and Teams: Active in the Computational Logic Center (CLC) at the University of Iowa, contributing to automated reasoning and verification tools.