معرفی
Andrew Joseph Reynolds is a Research Scientist at the University of Iowa, actively contributing to the development of the SMT solver cvc5. He is a core developer in the Computational Logic Center (CLC) and focuses on improving SMT solvers for unbounded strings, regular expressions, proofs, quantified formulas, and synthesis conjectures.
- Research Interests: Satisfiability Modulo Theories (SMT), Formal Verification, Automated Reasoning, Quantifier Instantiation, String Constraints, Synthesis Algorithms
Scientific Contributions include groundbreaking work in distributed SMT solving, proof reconstruction, and nonlinear arithmetic handling. His publications span premier conferences like FMCAD, CAV, IJCAR, and TACAS, with multiple best paper awards and competition wins.
- Major Competitions won: SMT Comp (multiple years), SyGuS Comp (General track, Conditional Linear Integer Arithmetic), CASC (typed first-order divisions)
He serves on program committees for conferences like FroCoS, LPAR, FMCAD, and SMT, and has organized workshops including the SyGuS Comp 2019 and 2018 FMCAD Student Forum. His work is funded by NSF grants and involves collaboration with leading institutions.
