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Sobhan BabuView profile

Associate Professor

• Big Data Analytics
• Graph Theory
• Algorithms
• +4 more

Dr. Sobhan Babu is an Associate Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology Hyderabad (IIT Hyderabad). His research focuses on Big Data Analytics, Graph Theory, Algorithms, and Applied Machine Learning. He obtained his Ph.D. and MTech from IIT Bombay, and his BE from the University of Madras. Education Ph.D. in Computer Science, IIT Bombay MTech in Computer Science, IIT Bombay BE in Computer Science, University of Madras Diploma in Computer Engineering, AANM&VVRSR Polytechnic Research Interests His work bridges theoretical and applied Computer Science. In Graph Theory, he investigates structural graph properties, subdivisions, and directed graph algorithms. In AI/ML, he explores optimization techniques for VLSI design and power-efficient testing. His Big Data Analytics focus includes developing algorithms for efficient data processing and modeling. Publications His publications span VLSI optimization, algorithmic game theory, and graph theory. Key themes include power minimization in scan testing, market equilibrium algorithms, and graph structural conditions. Recent accepted works extend existing research on cycles and unicyclic graphs, indicating sustained theoretical contributions. Contact Email: sobhan@iith.ac.in Office: Room CS-307, Computer Science Building, IIT Hyderabad, Telangana, India.

• Life and Health Informatics
• Computer Systems
• Control and System Engineering
• +5 more

Masao Yanagisawa is a Professor at Waseda University's School of Fundamental Science and Engineering, with over 25 years of academic experience since 1998. An IEEE and ACM member, he holds a Doctor of Engineering degree from Waseda University.

Alex OrailogluView profile

Professor

• Electronic Design Automation
• VLSI Test
• Fault-Tolerant ICs
• +3 more

Alex Orailoglu is a Professor at the Department of Computer Science and Engineering (CSE) at the University of California, San Diego (UCSD), since 1987. He leads the Reliable System Synthesis Group and specializes in Electronic Design Automation, VLSI Test, and Synthesis of Fault-Tolerant ICs. His work has produced over 80 publications and has advised 6 Ph.D. and 2 M.S. students. Education: S.B. in Applied Mathematics (Harvard University, 1977) M.S. in Computer Science (University of Illinois, Urbana, 1979) Ph.D. in Computer Science (University of Illinois, Urbana, 1983) Research focuses on hardware security, VLSI testing, and neural network robustness. His recent work includes logic obfuscation techniques to counter reverse engineering and methods for enhancing DNN fault tolerance. Professional involvement includes roles as General Chair, Program Chair, and Steering Committee member for conferences like IEEE VLSI Test Symposium and High-Level Design Validation Workshops. He has secured funding from the National Science Foundation, Intel, and other industry partners. Advising & Grants: Current advising includes 6 Ph.D. and 2 M.S. students. Notable sponsored research includes collaborations with NASA, NATO, and major tech firms like Agilent and Hewlett-Packard. Labs: Directs the Reliable System Synthesis Group (RSS Group) at UCSD, focusing on secure hardware design and embedded systems.

Jien-Chung LoView profile

Professor

• Digital Circuit Designs
• FPGA
• VLSI Testing and Reliability
• +4 more

Professor Jien-Chung Lo is a faculty member in the Department of Electrical, Computer, and Biomedical Engineering at the University of Rhode Island (URI), where he holds the rank of Professor. His research focuses on Digital Circuit Designs on FPGA, VLSI Testing and Reliability, and System-on-Chip and Hardware Accelerators. He has contributed to advancements in circuit reliability, testing methodologies, and error detection techniques, with notable work on concurrent error detection in arithmetic operations and built-in current sensors. Education: Ph.D., Computer Engineering, University of Southwestern Louisiana (1989) M.S., Computer Engineering, University of Southwestern Louisiana (1987) B.S., Electronics Engineering, Taipei University of Technology (1981) Research Interests: Lo’s work emphasizes practical applications of circuit design and testing, including FPGA-based systems, VLSI reliability, and fault-tolerant hardware. His patented innovations include methods for on-chip power management and programmable jitter generation, reflecting his expertise in bridging theoretical research with real-world engineering challenges. Patents and Contributions: Three key patents highlight his impact: Systems and Methods for On-Chip Power Management (US Patent 7902802, 2011) Programmable Jitter Signal Generator (LinkedIn Corp., 2006) Check Bit Code Circuit for Error Correction (US Secretary of Navy, 1995) Advising and Grants: While no formal advisees are listed, Lo’s research projects likely involve collaborative efforts with graduate students and industry partners. His work aligns with URI’s engineering initiatives, focusing on advancing hardware reliability and system design. Labs and Teams: Affiliated with URI’s Engineering department, his research leverages interdisciplinary collaborations to address challenges in embedded systems, signal processing, and fault-tolerant computing.

Sybille HellebrandView profile

Professor

• Testing and Diagnosis of Electronic Systems
• Fault Tolerance
• VLSI Design and Testing
• +3 more

Sybille Hellebrand is a Professor and Head of the Data Technology (DATE) department at the University of Paderborn, within the Faculty of Electrical Engineering, Computer Science and Mathematics. She leads research in testing methodologies, fault tolerance, and reliability engineering. Her work focuses on advanced testing techniques for nanoelectronic systems, including BIST (Built-In Self-Test), delay fault analysis, and interconnect reliability under process variations. Key research areas include: Testing and diagnosis of electronic systems Robust testing under PVT (Process-Voltage-Temperature) variability Functional safety of interconnects Approximate communication for error-tolerant systems Hardware fault modeling and simulation Recent publications emphasize advancements in storage-based BIST optimization, defect vs. fault coverage analysis, and cross-talk delay modeling using polynomial regression. She has contributed to international conferences such as European Test Symposium (ETS), IEEE Latin American Test Symposium (LATS), and International Symposium of EDA (ISEDA). Teaching responsibilities include courses on systems engineering, quality assurance in microelectronics, and algorithms for test and diagnosis of systems-on-chip. Her work aligns with emerging challenges in nanoelectronics, including reliability under variations and fault-tolerant communication. No specific awards or grants are listed in the provided texts, but her extensive publication record underscores her leadership in testing and reliability research. The DATE lab at Paderborn University serves as a core research hub for her activities.

Priyank KallaView profile

Professor

• Formal Verification
• Computer Algebra
• Algebraic Geometry
• +6 more

Priyank Kalla is a Professor at the University of Utah in the Department of Electrical and Computer Engineering. His research focuses on formal verification , arithmetic datapath optimization , and Silicon Photonics . PhD from University of Massachusetts at Amherst (2002) MS from University of Massachusetts at Amherst (1998) B.E. from Birla Vishvakarma Mahavidyala (1993) His research integrates computer algebra and algebraic geometry with design automation for verifying complex digital circuits. Recent work includes thermal-aware synthesis of photonic components and formal verification of post-quantum cryptographic implementations. Publications span IEEE Transactions on CAD , VLSI-SoC , and SAT conferences , with 2025 publications on Boolean function analysis and photonic test-point selection . His ACM TODAES 2007 paper on finite ring algebra optimization received the best paper award. Awards include: Outstanding Presentation Award at ETS 2025 Best Paper at VDAT 2024 Honourable Mention at ITC India 2022 Teaching includes ECE/CS 5745/6745 on Hardware Verification and ECE/CS 3700 on Digital System Design. His research group has secured multiple NSF grants (2005-2019) and University of Utah SEED grants.

William EisenstadtView profile

Professor

• Electronics
• IoT
• RF/Microwave Circuits
• +4 more

William Eisenstadt is a Professor in the Department of Electrical and Computer Engineering at the University of Florida. His research encompasses electronics, IoT applications for agriculture and public health, RF/microwave circuit design, and semiconductor testing. He holds a Ph.D., M.S., and B.S. in Electrical Engineering from Stanford University. Dr. Eisenstadt's research focuses on integrating IoT technologies with agricultural pest control, developing advanced testing methodologies for semiconductor devices, and designing RF/microwave systems. His work bridges hardware innovation with real-world applications in health, safety, and environmental monitoring. Recent publications demonstrate strong emphasis on semiconductor testing (BGA sockets, LDO regulators), 3D IC signal integrity, smart IoT devices for mosquito control, and biomedical ICs for drug delivery. Trends indicate cross-disciplinary convergence of microelectronics with biomedical and agricultural applications.

• Digital Circuit Design
• Integrated Circuit Testing
• Hardware Design
• +3 more

Xrysovalantis Kavousianos is a Professor at the Department of Computer Science & Engineering, University of Ioannina, Greece, affiliated with the School of Engineering. He holds a BSc (1996) and PhD (2000) in Computer Engineering from the University of Patras. His research focuses on digital circuit design, integrated circuit testing techniques, and fault-tolerant systems, with expertise in 3D-SoC testing, test access mechanisms, and low-power testing methodologies. Teaching responsibilities include courses such as Digital Design I (MYY305), Digital Design II (MYY406), and H3 - 3D Systems on Chip. His work emphasizes optimizing testing infrastructure for multi-Vdd, DVFS-based, and multi-core systems, addressing challenges in thermal-aware testing, defect coverage, and energy efficiency. Recent research highlights include time-division multiplexing for 3D-SoCs, X-filling techniques for unmodeled defects, and BIST frameworks for power switches. Publications (2013–2019) concentrate on testing optimization, statistical compression, and hardware reliability in complex systems. Collaborations involve advanced SoC architectures and reconfigurable power management solutions.

Yusuf LeblebiciView profile

Professor

• High-speed CMOS Integrated Circuits
• VLSI Systems Design
• Semiconductor Device Modeling
• +5 more

Prof. Dr. Yusuf Leblebici is the Rector of Sabancı University (since 2018) and a renowned academic in microelectronics and integrated circuits. He holds a BS/MS from Istanbul Technical University (1984/1986) and a PhD from the University of Illinois at Urbana-Champaign (UIUC, 1990). Prior roles include faculty positions at UIUC, Istanbul Technical University, Worcester Polytechnic Institute (WPI), and Sabancı University, where he established the microelectronics program. From 2002 to 2018, he led the Microelectronic Systems Laboratory at EPFL as Chair Professor. His research focuses on high-speed CMOS ICs, VLSI design, smart sensors, semiconductor modeling, and reliability. He has authored/co-authored 9 textbooks, including the seminal CMOS Digital Integrated Circuits: Analysis and Design , with 250,000+ copies sold globally. His work spans 350+ scientific publications. Notable awards include IEEE Fellow (2009), UIUC ECE Distinguished Alumni (2020), and membership in Academia Europaea (2023). He has advised 58 PhD and over 100 MSc students. His labs and collaborations have driven innovations in nanoelectromechanical systems, biomedical SoCs, and high-speed communication circuits.

Michael MascagniView profile

Professor

• Computational Science
• Monte Carlo Methods
• Numerical Analysis
• +5 more

Michael Mascagni is a Professor at Florida State University with joint appointments in the Department of Computer Science, Department of Mathematics, Department of Scientific Computing, and the Graduate Program in Molecular Biophysics. He holds courtesy affiliations with the Department of Chemical and Biomedical Engineering, and maintains collaborative roles as a Guest Researcher at NIH's Laboratory for Biological Modeling and Faculty Appointee at NIST's Applied and Computational Mathematics Division. His academic credentials include a Ph.D. in Mathematics from NYU (1987), and dual B.S. degrees in Mathematics and Biomedical Engineering from the University of Iowa. His research integrates computational science, Monte Carlo methods, and parallel computing to solve complex problems in biophysics, materials science, and numerical analysis. Key interests include scalable random number generation, stochastic PDE solvers for electrostatics (Poisson-Boltzmann), computational neuroscience, and high-performance algorithm design. His work emphasizes applications in molecular biophysics, financial modeling, and fault-tolerant computing. Recent publications demonstrate a strong focus on advancing Monte Carlo techniques, including novel algorithms for matrix computations, discrepancy estimation, and biomolecular electrostatics. His articles frequently intersect computational mathematics, parallel architectures, and biological applications, with emerging themes in randomized linear algebra, quasirandom methods, and neural network reproducibility. Scientific Awards & Honors: Fulbright Senior Specialist Roster (2008) FSU Developing Scholar Award (2001) NAS/NRC Postdoctoral Fellowship (1988-1989) ACM Distinguished Scientist (2011-Present) ACM Senior Member (2009-Present) He directs research in scalable algorithms and collaborates with national labs including NIH and NIST. His computational infrastructure contributions include the SPRNG library and ZENO software for biomolecular properties. Current projects explore Grid-based Monte Carlo, randomized linear solvers, and actomyosin ring modeling in cellular division.

Kaushik PatraView profile

Lecturer

• Computer Engineering
• VLSI Design
• Circuit Analysis
• +3 more

Kaushik Patra is a Lecturer in the Department of Computer Science at San José State University (SJSU). He holds a Master of Science in Computer Engineering from CSU-San Jose (2013). His research interests focus on VLSI design, circuit analysis, parallel computing, and software testing methodologies. Key publications include work on parallel flip-flop timing analysis (2014), resource estimation for computational jobs (2011), transistor-level device identification algorithms (2008), and software test coverage frameworks using BIT (2008). Dr. Patra's academic profile emphasizes practical applications in hardware design optimization and computational resource management. He can be reached at kaushik.patra@sjsu.edu .

TOK Eng SoonView profile

Associate Professor

• Materials Science
• Surface Science
• Thin Film Growth
• +10 more

TOK Eng Soon is an Associate Professor at the National University of Singapore (NUS), specializing in electronic materials growth and interface characterization. His research spans fundamental and applied surface science, focusing on low-dimensional structures at the atomic scale and non-destructive materials analysis for quality control in consumer products. Education: PhD, Imperial College London, UK (1998) BSc (Hons. Physics and Chemistry), NUS, SG (1993) Research Interests: Electronic Materials Growth and Interface Characterisation (eMaGIC): Growth kinetics, dynamics, and self-assembly in thin films on semiconductors Materials Analysis and Reliability Science (MARS): Non-destructive testing for industrial applications Spintronics: Electronic states in silicene and transition metal silicides Advanced Characterization Techniques: XPS, UPS, AFM, TEM, XRD, and more Research Trends: His recent publications highlight interdisciplinary work in semiconductor manufacturing (e.g., VLSI interconnects), atomic-scale material behavior (e.g., CoSi2 nanowires), and emerging areas like GeSn alloys and silicene for spintronics.

• Parallel Computing
• Distributed Systems
• Electronic Design Automation
• +6 more

Lorenzo Cardone is a PhD student (38th cycle, 2022-2025) in Computer and Systems Engineering and serves as an External Lecturer at Politecnico di Torino's Department of Control and Computer Engineering (DAUIN). His academic appointments include: Part-time Teaching Assistant for Operating Systems courses (2023-2026) Research collaboration with the Formal Methods (FM) research group Education background includes: Bachelor's in Computer Science (2019) Master's in Computer Graphics and Multimedia (2021) Research focuses on parallel computing infrastructures, software optimization for complex graph problems, and Electronic Design Automation (EDA) applications. Specific interests span: Parallel/distributed systems architecture Quantum computing implementations Circuit simulation techniques Fault tolerance in digital systems Automotive SoC testing methodologies Recent publications (2024-2025) demonstrate specialization in test program optimization, SoC validation, and heuristic approaches for large-scale circuit analysis, primarily published in IEEE Transactions on Computers and major test engineering conferences. No awards or student advisement mentioned. Research conducted within DAUIN's Formal Methods group under supervisors Stefano Quer and Paolo Bernardi.

Georg SiglView profile

Professor

• Hardware Security
• Cryptography
• Embedded Systems Security
• +6 more

Prof. Dr.-Ing. Georg Sigl is a Professor of Information Technology Security at the Technical University of Munich (TUM) and Director of the Fraunhofer Institute for Applied and Integrated Security (AISEC). His research focuses on hardware security, including secure embedded systems design and hardware attack analysis. He holds a doctorate in design automation from TUM (1992) and has extensive industry experience at Siemens and Infineon, where he led chip card platform development. Notable achievements include award-winning chip card controllers (SLE88/SLE78) and foundational contributions to tamper-resistant hardware. Education: Doctorate in Design Automation, Technical University of Munich (1992) Diploma in Electrical Engineering, Technical University of Munich Research interests include hardware security, cryptographic implementations, physical unclonable functions (PUFs), post-quantum cryptography, and defense against invasive/side-channel attacks. His work bridges academic research and industrial applications, emphasizing practical security solutions for embedded systems and IoT. Awards: Best Paper Award at IEEE HOST 2018 Sesames Award 2008 (SLE78 chip card) Sesames Award 2001 (SLE88 chip card) Rohde & Schwarz Prize 1993 (Dissertation) Leadership: Founded TUM's Chair of Information Security (2010) Director of Fraunhofer AISEC Labs/Teams: Chair of Information Security at TUM collaborating closely with Fraunhofer AISEC, focusing on advanced security research and industry partnerships.

• Digital Circuits
• VLSI Design
• Signal Processing
• +4 more

Paulo Flores holds the position of Associate Professor at the Department of Electrical and Computer Engineering within the Instituto Superior Técnico of the University of Lisbon. His academic career is deeply rooted in Electronics and Digital Systems, with a focus on VLSI design, FPGA optimization, and hardware acceleration for bioinformatics applications. He has contributed extensively to research in multiplierless constant multiplication algorithms, low-power circuit design, and quaternary logic implementations. Notable achievements include the SAT Competition 2014 and 2013 Bronze Medals for innovative contributions in formal methods and algorithmic efficiency. His teaching responsibilities include advanced courses in digital systems design, electronic engineering projects, and laboratory guidance in topics like operational amplifiers and FIR filters. Flores actively collaborates with research units like INESC-ID and has supervised multiple academic projects in electronic engineering and digital signal processing. Research interests span across circuit testing, embedded systems optimization, and multi-valued logic architectures. His work frequently explores trade-offs between computational efficiency and energy consumption in hardware implementations.