Minah Lee is a Postdoctoral Fellow at Georgia Tech's Electrical and Computer Engineering department. Her research integrates edge intelligence, energy-efficient computing, and reliable sensor platforms. Publications feature cross-layer hardware designs (AFE-CIM macro), cryogenic computing efficiency (Cool-CIM), and uncertainty estimation for neural accelerators. Recent work explores multi-agent dynamics and analog computing robustness.
Gülay YALÇIN is an Assistant Professor at Abdullah Gul University since 2016. She holds a Ph.D. in Computer Architecture from Universitat Politècnica de Catalunya (2014), an MS in Computer Engineering from TOBB University (2007), and a BS in Computer Engineering from Hacettepe University (2003). Her research focuses on reliable computer design, fault detection, parallel architectures, and low-power systems. She has led projects like ParaDIME (2012-2015) and Velox (2008-2011), advancing energy-efficient computing and transactional memory. Education: Ph.D., Universitat Politècnica de Catalunya, Department of Computer Architecture (2008-2014) M.S., TOBB University of Economics and Technology, Computer Engineering (2007) B.S., Hacettepe University, Computer Engineering (2003) Research Interests: Her work spans fault-tolerant computing, energy-efficient designs, hardware transactional memory, and parallel architectures. She has contributed to error detection techniques leveraging comparators, voltage scaling for reliability, and novel cache designs like Flexicache. Key Projects: ParaDIME (2012-2015): Energy minimization in data centers. Shortlisted for the 2016 Innovation Radar Prize. Velox (2008-2011): Transactional memory for multi-core systems. Reliable Embedded Processors (2007-2008): Fault mitigation in embedded systems. Teaching: She teaches undergraduate courses on 'Exploring Profession' and graduate courses on 'Computer Architecture.' Advising: Currently advising M.S. student Albert Njoroge Kahira on reliable microarchitecture design. Labs/Teams: Active in the Barcelona Supercomputing Center (BSC) during her postdoc (2014-2015) and as a graduate researcher (2009-2014).
Jim Plusquellic is a Professor in the Department of Electrical and Computer Engineering at the University of New Mexico. He holds leadership roles including Director of the Integrated Circuit Hardware Analysis Laboratory (IC-HAL) and President/CEO of IC-Safety, LLC. His research focuses on hardware security, trust, and IoT systems, with contributions to PUF-based authentication and Trojan detection. He has authored/co-authored over 100 refereed publications and holds multiple patents. Plusquellic has been honored with awards such as the IEEE Computer Society's Outstanding Contribution Award and induction into the HOST Hall-of-Fame. Education: Ph.D., Computer Science, University of Pittsburgh, 1997 M.S., Computer Science, University of Pittsburgh, 1995 B.S., Biology, Indiana University of Pennsylvania, 1983 Research & Grants: Lead PI for the "Trusted and Assured Microelectronics Theme" under ASU's SWAP Hub ($2.5M, 2024-2028) NSF-funded projects on hardware security primitives and DFM (e.g., $300K for regional process variation analysis) Industry collaborations with Sandia National Labs, IBM, NASA, and commercial entities Key Contributions: Co-founder of the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Developed PUF-based authentication protocols (e.g., PUF-Cash for digital currency) Authored book chapters on hardware security and Trojan detection Labs & Teams: Integrated Circuit Hardware Analysis Laboratory (IC-HAL) Collaboration with Enthentica Inc. and IC-Safety for hardware security commercialization
Selahattin Sayil is a Professor at the Philip M. Drayer Department of Electrical and Computer Engineering at Lamar University. His research focuses on radiation effects in integrated circuits, low power design, crosstalk noise mitigation, and contactless VLSI testing. He earned his Ph.D. in Electrical and Computer Engineering from Vanderbilt University, M.Sc. from Pennsylvania State University, and B.Sc. in Electronics Education from Gazi University, Turkey. His research explores soft error mechanisms in nanoscale CMOS, thermal-aware radiation hardening , and asynchronous circuit design for robustness in harsh environments. Funded by NSF and NASA, he developed online engineering labs and Hardware-in-Homework concepts to enhance student learning. Scientific awards include the Distinguished Faculty Teaching Fellow, Lamar University (2018-2021) . He has mentored over 35 master's theses and 3 doctoral students, with many advisees pursuing careers at Intel, NVIDIA, and academia. He serves as Graduate Advisor for the ECE Program and has held editorial roles for the International Journal of Electronics and IEEE Potentials .
Adit Singh is the Godbold Endowed Chair Professor in the Department of Electrical and Computer Engineering at Auburn University's College of Engineering. He holds a Ph.D. and M.S. in Electrical Engineering from Virginia Tech and a B.S. (B.Tech.) from IIT Kanpur. He previously served on the faculty at the University of Massachusetts and Virginia Tech, and has held visiting professorships at the University of Freiburg (2012), University of Tokyo (2018), and is scheduled to be a Guest Professor at the University of Stuttgart in Fall 2025. His research centers on VLSI design, integrated circuit testing, reliability, and design for testability. He is renowned for pioneering statistical and adaptive testing methods in semiconductor validation. His work spans digital systems, computer architecture, and electronic design automation (EDA), with strong industrial impact through licensed patents and consulting for major semiconductor and EDA firms. Professor Singh has authored over 300 research papers and holds international patents. He has led numerous IEEE conferences as General or Program Chair and served on editorial boards, including IEEE Design and Test. He chaired the IEEE Test Technology Technical Council (2007–2011) and was on the Board of Governors of the IEEE Council on Design Automation (2011–2015). His scientific honors include IEEE Life Fellowship, IEEE Computer Society Golden Core Membership, and the 2021 Auburn University Award for Excellence in Faculty Outreach. He actively mentors students and collaborates globally, with ongoing research projects in resilient computing and transistor-level reliability. Ph.D., Electrical Engineering, Virginia Tech M.S., Electrical Engineering, Virginia Tech B.S. (B.Tech.), Electrical Engineering, Indian Institute of Technology-Kanpur Scientific Awards: IEEE Life Fellow Golden Core Member, IEEE Computer Society Auburn University 2021 Award for Excellence in Faculty Outreach Professor Singh has led major research initiatives, including one of only five resilient computing projects funded by the Open Compute Project. His work bridges academia and industry, serving as an expert witness in patent litigation and advising semiconductor leaders worldwide. He leads a dynamic research group at Auburn focused on next-generation VLSI test methodologies.
Adit D. Singh is a Professor and the Godbold Endowed Chair in the Department of Electrical and Computer Engineering at Auburn University's College of Engineering. He has previously served on the faculty at the University of Massachusetts, Amherst, and Virginia Tech, and has held visiting professorships at the University of Freiburg (2012), the University of Tokyo (2018), and will be a Guest Professor at the University of Stuttgart in Fall 2025. His educational background includes a B.Tech. from IIT Kanpur and M.S. and Ph.D. degrees from Virginia Tech, all in Electrical Engineering. Dr. Singh's research focuses on VLSI technology, particularly integrated circuit test, reliability, design for testability, and statistical and adaptive testing methodologies. His work bridges theoretical innovation and industrial application, with over 300 research papers and licensed international patents. His expertise has been recognized through extensive service in leadership roles in IEEE conferences and technical councils. The trends in his research, reflected across his publications, emphasize robust testing frameworks for digital systems, reliability enhancement in nanoscale circuits, and the development of adaptive and statistical test solutions for modern semiconductor devices. His work intersects computer architecture, electronic design automation (EDA), and fault tolerance in digital systems. IEEE Fellow (2002) IEEE Life Fellow Golden Core Member, IEEE Computer Society Godbold Endowed Chair Professor Dr. Singh has been actively involved in academic leadership and professional service, having served as General Chair, Co-Chair, and Program Chair for numerous international VLSI design and test conferences. He has served two elected terms as Chair of the IEEE Test Technology Technical Council (2007–2011) and on the Board of Governors of the IEEE Council on Design Automation (2011–2015). He has also served on the editorial boards of journals including IEEE Design and Test and on steering committees of major IEEE conferences. As a consultant, he has advised major semiconductor, test, and EDA companies and served as an expert witness in patent litigation cases, demonstrating strong industry engagement. He is associated with research initiatives in integrated circuit testing and reliability at Auburn University, where his lab focuses on developing advanced transistor testing methods and design-for-test solutions. His team contributes to improving the reliability and yield of modern integrated circuits, with ongoing projects likely supported through industry collaboration and federal funding, though specific grants are not listed.
Masao Yanagisawa is a Professor at Waseda University's School of Fundamental Science and Engineering, with over 25 years of academic experience since 1998. An IEEE and ACM member, he holds a Doctor of Engineering degree from Waseda University.
Alex Orailoglu is a Professor at the Department of Computer Science and Engineering (CSE) at the University of California, San Diego (UCSD), since 1987. He leads the Reliable System Synthesis Group and specializes in Electronic Design Automation, VLSI Test, and Synthesis of Fault-Tolerant ICs. His work has produced over 80 publications and has advised 6 Ph.D. and 2 M.S. students. Education: S.B. in Applied Mathematics (Harvard University, 1977) M.S. in Computer Science (University of Illinois, Urbana, 1979) Ph.D. in Computer Science (University of Illinois, Urbana, 1983) Research focuses on hardware security, VLSI testing, and neural network robustness. His recent work includes logic obfuscation techniques to counter reverse engineering and methods for enhancing DNN fault tolerance. Professional involvement includes roles as General Chair, Program Chair, and Steering Committee member for conferences like IEEE VLSI Test Symposium and High-Level Design Validation Workshops. He has secured funding from the National Science Foundation, Intel, and other industry partners. Advising & Grants: Current advising includes 6 Ph.D. and 2 M.S. students. Notable sponsored research includes collaborations with NASA, NATO, and major tech firms like Agilent and Hewlett-Packard. Labs: Directs the Reliable System Synthesis Group (RSS Group) at UCSD, focusing on secure hardware design and embedded systems.
Professor Jien-Chung Lo is a faculty member in the Department of Electrical, Computer, and Biomedical Engineering at the University of Rhode Island (URI), where he holds the rank of Professor. His research focuses on Digital Circuit Designs on FPGA, VLSI Testing and Reliability, and System-on-Chip and Hardware Accelerators. He has contributed to advancements in circuit reliability, testing methodologies, and error detection techniques, with notable work on concurrent error detection in arithmetic operations and built-in current sensors. Education: Ph.D., Computer Engineering, University of Southwestern Louisiana (1989) M.S., Computer Engineering, University of Southwestern Louisiana (1987) B.S., Electronics Engineering, Taipei University of Technology (1981) Research Interests: Lo’s work emphasizes practical applications of circuit design and testing, including FPGA-based systems, VLSI reliability, and fault-tolerant hardware. His patented innovations include methods for on-chip power management and programmable jitter generation, reflecting his expertise in bridging theoretical research with real-world engineering challenges. Patents and Contributions: Three key patents highlight his impact: Systems and Methods for On-Chip Power Management (US Patent 7902802, 2011) Programmable Jitter Signal Generator (LinkedIn Corp., 2006) Check Bit Code Circuit for Error Correction (US Secretary of Navy, 1995) Advising and Grants: While no formal advisees are listed, Lo’s research projects likely involve collaborative efforts with graduate students and industry partners. His work aligns with URI’s engineering initiatives, focusing on advancing hardware reliability and system design. Labs and Teams: Affiliated with URI’s Engineering department, his research leverages interdisciplinary collaborations to address challenges in embedded systems, signal processing, and fault-tolerant computing.
Sybille Hellebrand is a Professor and Head of the Data Technology (DATE) department at the University of Paderborn, within the Faculty of Electrical Engineering, Computer Science and Mathematics. She leads research in testing methodologies, fault tolerance, and reliability engineering. Her work focuses on advanced testing techniques for nanoelectronic systems, including BIST (Built-In Self-Test), delay fault analysis, and interconnect reliability under process variations. Key research areas include: Testing and diagnosis of electronic systems Robust testing under PVT (Process-Voltage-Temperature) variability Functional safety of interconnects Approximate communication for error-tolerant systems Hardware fault modeling and simulation Recent publications emphasize advancements in storage-based BIST optimization, defect vs. fault coverage analysis, and cross-talk delay modeling using polynomial regression. She has contributed to international conferences such as European Test Symposium (ETS), IEEE Latin American Test Symposium (LATS), and International Symposium of EDA (ISEDA). Teaching responsibilities include courses on systems engineering, quality assurance in microelectronics, and algorithms for test and diagnosis of systems-on-chip. Her work aligns with emerging challenges in nanoelectronics, including reliability under variations and fault-tolerant communication. No specific awards or grants are listed in the provided texts, but her extensive publication record underscores her leadership in testing and reliability research. The DATE lab at Paderborn University serves as a core research hub for her activities.
William Eisenstadt is a Professor in the Department of Electrical and Computer Engineering at the University of Florida. His research encompasses electronics, IoT applications for agriculture and public health, RF/microwave circuit design, and semiconductor testing. He holds a Ph.D., M.S., and B.S. in Electrical Engineering from Stanford University. Dr. Eisenstadt's research focuses on integrating IoT technologies with agricultural pest control, developing advanced testing methodologies for semiconductor devices, and designing RF/microwave systems. His work bridges hardware innovation with real-world applications in health, safety, and environmental monitoring. Recent publications demonstrate strong emphasis on semiconductor testing (BGA sockets, LDO regulators), 3D IC signal integrity, smart IoT devices for mosquito control, and biomedical ICs for drug delivery. Trends indicate cross-disciplinary convergence of microelectronics with biomedical and agricultural applications.
Xrysovalantis Kavousianos is a Professor at the Department of Computer Science & Engineering, University of Ioannina, Greece, affiliated with the School of Engineering. He holds a BSc (1996) and PhD (2000) in Computer Engineering from the University of Patras. His research focuses on digital circuit design, integrated circuit testing techniques, and fault-tolerant systems, with expertise in 3D-SoC testing, test access mechanisms, and low-power testing methodologies. Teaching responsibilities include courses such as Digital Design I (MYY305), Digital Design II (MYY406), and H3 - 3D Systems on Chip. His work emphasizes optimizing testing infrastructure for multi-Vdd, DVFS-based, and multi-core systems, addressing challenges in thermal-aware testing, defect coverage, and energy efficiency. Recent research highlights include time-division multiplexing for 3D-SoCs, X-filling techniques for unmodeled defects, and BIST frameworks for power switches. Publications (2013–2019) concentrate on testing optimization, statistical compression, and hardware reliability in complex systems. Collaborations involve advanced SoC architectures and reconfigurable power management solutions.
Prof. Dr. Yusuf Leblebici is the Rector of Sabancı University (since 2018) and a renowned academic in microelectronics and integrated circuits. He holds a BS/MS from Istanbul Technical University (1984/1986) and a PhD from the University of Illinois at Urbana-Champaign (UIUC, 1990). Prior roles include faculty positions at UIUC, Istanbul Technical University, Worcester Polytechnic Institute (WPI), and Sabancı University, where he established the microelectronics program. From 2002 to 2018, he led the Microelectronic Systems Laboratory at EPFL as Chair Professor. His research focuses on high-speed CMOS ICs, VLSI design, smart sensors, semiconductor modeling, and reliability. He has authored/co-authored 9 textbooks, including the seminal CMOS Digital Integrated Circuits: Analysis and Design , with 250,000+ copies sold globally. His work spans 350+ scientific publications. Notable awards include IEEE Fellow (2009), UIUC ECE Distinguished Alumni (2020), and membership in Academia Europaea (2023). He has advised 58 PhD and over 100 MSc students. His labs and collaborations have driven innovations in nanoelectromechanical systems, biomedical SoCs, and high-speed communication circuits.
Michael Mascagni is a Professor at Florida State University with joint appointments in the Department of Computer Science, Department of Mathematics, Department of Scientific Computing, and the Graduate Program in Molecular Biophysics. He holds courtesy affiliations with the Department of Chemical and Biomedical Engineering, and maintains collaborative roles as a Guest Researcher at NIH's Laboratory for Biological Modeling and Faculty Appointee at NIST's Applied and Computational Mathematics Division. His academic credentials include a Ph.D. in Mathematics from NYU (1987), and dual B.S. degrees in Mathematics and Biomedical Engineering from the University of Iowa. His research integrates computational science, Monte Carlo methods, and parallel computing to solve complex problems in biophysics, materials science, and numerical analysis. Key interests include scalable random number generation, stochastic PDE solvers for electrostatics (Poisson-Boltzmann), computational neuroscience, and high-performance algorithm design. His work emphasizes applications in molecular biophysics, financial modeling, and fault-tolerant computing. Recent publications demonstrate a strong focus on advancing Monte Carlo techniques, including novel algorithms for matrix computations, discrepancy estimation, and biomolecular electrostatics. His articles frequently intersect computational mathematics, parallel architectures, and biological applications, with emerging themes in randomized linear algebra, quasirandom methods, and neural network reproducibility. Scientific Awards & Honors: Fulbright Senior Specialist Roster (2008) FSU Developing Scholar Award (2001) NAS/NRC Postdoctoral Fellowship (1988-1989) ACM Distinguished Scientist (2011-Present) ACM Senior Member (2009-Present) He directs research in scalable algorithms and collaborates with national labs including NIH and NIST. His computational infrastructure contributions include the SPRNG library and ZENO software for biomolecular properties. Current projects explore Grid-based Monte Carlo, randomized linear solvers, and actomyosin ring modeling in cellular division.
TOK Eng Soon is an Associate Professor at the National University of Singapore (NUS), specializing in electronic materials growth and interface characterization. His research spans fundamental and applied surface science, focusing on low-dimensional structures at the atomic scale and non-destructive materials analysis for quality control in consumer products. Education: PhD, Imperial College London, UK (1998) BSc (Hons. Physics and Chemistry), NUS, SG (1993) Research Interests: Electronic Materials Growth and Interface Characterisation (eMaGIC): Growth kinetics, dynamics, and self-assembly in thin films on semiconductors Materials Analysis and Reliability Science (MARS): Non-destructive testing for industrial applications Spintronics: Electronic states in silicene and transition metal silicides Advanced Characterization Techniques: XPS, UPS, AFM, TEM, XRD, and more Research Trends: His recent publications highlight interdisciplinary work in semiconductor manufacturing (e.g., VLSI interconnects), atomic-scale material behavior (e.g., CoSi2 nanowires), and emerging areas like GeSn alloys and silicene for spintronics.
