Johannes Geier is a Researcher at the Chair of Design Automation at the Technical University of Munich (TUM). His work focuses on electronic design automation, fault injection simulations, and security countermeasures for RISC-V processors. University: Technical University of Munich Department: Chair of Design Automation Email: johannes.geier@tum.de Research Interests Electronic Design Automation (EDA) for analog and digital circuits Fault tolerance and reliability in RISC-V architectures Security analysis of post-quantum cryptographic systems Timing analysis and microfabrication techniques Optical Networks-on-Chip (NoC) and emerging technologies Compiler-assisted hardware security implementations Recent Research Trends Specializes in fault injection methodologies for hardware security validation Develops open-source tools like vRTLmod for RTL simulation acceleration Explores RISC-V vector extensions for post-quantum cryptography Investigates differential fault effect equivalence checks for efficiency Designs compiler-based security countermeasures against instruction skip attacks Works on concurrent multi-node XCP proxy server architectures
Anton Cervin is a Senior Lecturer at the Department of Automatic Control, Faculty of Engineering, Lund University. He is currently on leave of duty but remains actively involved in research and supervision. His work spans real-time systems, event-based control, cloud computing, and embedded systems, with strong ties to industrial applications and sustainable technologies. His research interests include: Event-Based and Stochastic Control Networked and Embedded Control Systems Cloud-Based Control and Resource Management Real-Time Scheduling and Performance Analysis Digital Twins and Fluid Modeling in Cloud Environments He has led major research projects funded by the Swedish Research Council, WASP, and ELLIIT, focusing on robust and secure cloud control, self-adaptive systems, and distributed learning. His software tools—TrueTime, Jitterbug, and TinyRealTime—are widely used in academia and industry for simulating and analyzing real-time control systems. The most recent publications highlight a shift toward intelligent, adaptive control using reinforcement learning, fluid modeling for microservices, and timing-robust cloud control—indicating a strong trend in merging traditional control theory with modern computing paradigms. His scientific contributions have been recognized with multiple Best Paper Awards: Best Paper Award - ECRTS 2021 Best Paper Award - RTNS 2016 Best Paper Award - RTCSA 2004 Best Paper Award - ECRTS 2003 Best Student Paper Award - RTCSA 1999 Anton Cervin has supervised numerous PhD students, including Max Nyberg Carlsson, Nils Vreman, and Claudio Mandrioli, and has served in key academic roles such as Director of PhD Studies and Deputy Head of Department. He has also led educational initiatives like doctoral study circles on programming languages and the history of control. He is affiliated with research environments such as WASP and ELLIIT and contributes to UN Sustainable Development Goals through advancements in smart systems and sustainable automation.
Dr. Lixin Tao is a tenured Professor and Chairperson of the Computer Science Department at Pace University's Seidenberg School of CSIS. He earned his PhD in Computer Science from the University of Pennsylvania in 1988 and has conducted research and teaching at Concordia University (1988-2001) before joining Pace University. Research Interests: Dr. Tao's work spans Internet Computing , Server Scalability , Component Technologies , Parallel Computing , Functional Simulation , and Combinatorial Optimization , with recent focus on Knowledge Graphs , Semantic Web , and Secure Mobile Cloud Systems . He has pioneered cloud computing research since the 1990s and developed industry standards like OWL extensions. Over 300 peer-reviewed publications Director of Pace University's PhD Computer Science Program (2013-2017) Developed MS in Enterprise Analytics (2015) and BS in Computer Engineering (2017) Scientific Awards: Recognized as IEEE Senior Member (2020), ABET Evaluator (2001-2012), and recipient of multiple research grants including a $12M NSERC Strategic Technology Program and NSF awards for server infrastructure. He received Pace University's Presidential Research Grant and collaborated with institutions like Stanford University on knowledge engineering projects. Professional Contributions: Directed ABET accreditation for Pace's BS-CS program (2010-2012), served as Editor-in-Chief for the Journal of Computer Science Research (2018-present), and supervised dozens of PhD/DPS students in areas ranging from Mobile Payment Protocols to Drug Side Effect Knowledge Graphs . His lab focuses on Knowledge-Empowered AI and Secure Software Development .
Martin Karsten is a Professor at the David R. Cheriton School of Computer Science, University of Waterloo, where he leads research in software systems and networking. His work focuses on finding simple approaches to building robust and efficient systems infrastructure. He teaches courses including Real-time Programming, Operating Systems, Distributed Systems, and Computer Networks. His research explores fundamental patterns for software infrastructure design and redesigning systems using modular building blocks. Primary interests include system-level runtime systems (OS kernels, hypervisors), performance optimization through simplicity, and structural commonalities across software layers. Key research areas encompass system software, network architecture, network services, and network software. Karsten holds a Diplom-Wirtschaftsinformatiker from Universität Mannheim and Dr.-Ing. from TU Darmstadt. His career includes positions as Assistant Professor (2002-2007), Associate Professor (2007-2020), and Professor (2021-present) at Waterloo, with administrative roles including Associate Director of the School since 2020. He maintains active collaborations through sabbaticals at SAP and visiting positions at TU Kaiserslautern. He currently advises multiple graduate students in the MMath program and has contributed to open-source projects like libfibre (user-level threading) and KOS (experimental OS kernel). His professional service includes roles in academic integrity initiatives and conference organization.
Karakostas Vasileios is an Assistant Professor at the Department of Informatics and Telecommunications of the National and Kapodistrian University of Athens. His research focuses on computer architecture, cloud computing, and energy-efficient hardware systems. He specializes in areas such as RISC-V processors, virtual memory systems, and hardware security. Vasileios leads projects like NEUROPULS (neuromorphic secure accelerators) and Vitamin-V (RISC-V-based cloud infrastructure validation). His work emphasizes resilience analysis, performance optimization, and trustworthy development frameworks. Education and employment details are not explicitly provided in the source text, but his extensive publication record since 2011 demonstrates continuous academic engagement. Key research trends include: Memory systems optimization (e.g., TLB hierarchies, elastic translations) GPU and SoC fault tolerance analysis Cloud resource management (ACTiCLOUD, DAPHNE runtime) Open-source hardware validation (Vitamin-V project) Notable contributions include the Gem5-marvel simulator for heterogeneous architectures and BypassD for SSD access acceleration. His work bridges theoretical computer architecture with practical cloud and embedded system applications.
Douglas E. Comer is a Distinguished Professor of Computer Science at Purdue University, where he has made significant contributions to the fields of computer networking, operating systems, and distributed computing. He is renowned for his foundational work on TCP/IP protocols and for authoring influential textbooks that have shaped academic and professional understanding of computer science concepts. Comer's research interests focus on networking fundamentals, operating system design (particularly the XINU OS), and cloud computing architectures. His professional activities include consulting for industries, delivering seminars on TCP/IP, DNSSEC, and network processor design, and advising on large-scale web systems. He has authored over 20 books translated into multiple languages, including Computer Networks and Internets , Internetworking with TCP/IP , and Operating System Design . His work emphasizes practical education through experimental projects and lab guides, such as Hands-on Networking with Internet Applications . He is also known for his guidance on Ph.D. programs and academic careers in computer science, advocating for rigorous research and mastery of domain knowledge. Comer's contributions extend to open-source software implementations, including protocol stacks and educational tools. His consulting practice focuses on network security, distributed systems design, and emerging technologies like edge computing and software-defined networking.
Michael Huang is a Professor in the Department of Electrical and Computer Engineering and Computer Science at the University of Rochester's Hajim School of Engineering & Applied Sciences. He holds a PhD from the University of Illinois at Urbana-Champaign (2002) and has been faculty since 2002. His research focuses on high-performance computing, including processor microarchitecture, energy-efficient design, and non-von Neumann systems like Ising machines. He has received the NSF CAREER Award and is a member of ISCA/HPCA Hall of Fame. Education: BS (Tsinghua University, 1994), MS/PhD (UIUC, 1999/2002). Research emphasizes co-design of device, circuit, and system technologies. Notable projects include multi-chip Ising machine architectures and optical interconnects. Collaborates with IBM Research on future processor concepts. Active in top conferences like ISCA, HPCA, and ICLR. Key achievements include pioneering work on Ising machines for combinatorial optimization, energy-efficient architectures, and secure branch predictors. His work bridges traditional computer architecture with emerging technologies like optics and mixed-signal circuits.
Christopher Crispin-Bailey is a Senior Lecturer in the Department of Computer Science at the University of York. He holds a BEng and PhD from Teesside University. His research focuses on VHDL hardware synthesis, novel microprocessor architectures, stack-based processors, optimization of stack-oriented object code, multimedia server architectures, and bus arbitration methods. Career highlights include roles as a Teaching Research Fellow (1996–1997), Senior Lecturer at the University of Teesside (1997–1999), and Lecturer at the University of York since 1999. He currently holds the title of Senior Lecturer and is part of the Real-Time and Distributed Systems research group. His contributions span hardware design, embedded systems, and biomedical signal processing. He contributes to departmental roles as an Exam Paper Checker and Union Rep. His work emphasizes practical applications in both academic and industry contexts, with a focus on optimizing hardware and software systems for efficiency and scalability.
Abhishek Bhattacharjee is the A. Bartlett Giamatti Professor of Computer Science at Yale University. His work spans computer architecture, operating systems, and brain-computer interfaces (BCIs), with groundbreaking contributions to memory address translation and neurotechnology. He leads a research group developing full-stack systems like HALO and SCALO for brain-machine integration. Education : Ph.D., Princeton University; B.Eng., McGill University His research focuses on: Memory address translation optimizations Brain-computer interface architectures Virtual memory systems Heterogeneous memory management Low-power accelerators for neural interfaces Recent publications emphasize scalable memory systems for BCIs, TLB behavior analysis, and fiduciary AI integration with neurotechnology. His work has been adopted by AMD, NVIDIA, RISC-V, and Linux kernel. Scientific Awards & Honors : ACM SIGARCH Maurice Wilkes Award, 2023 Best Paper Award, ISCA '23 Distinguished Paper Award, ASPLOS '23 NSF CAREER Award, 2013 Yale Dylan Hixon Prize for Teaching, 2025 He has advised students now at NVIDIA, AMD, and Huawei, and teaches courses like Computer Architecture and Systems Programming . His group collaborates with Princeton Neuroscience Institute and industry leaders in AI/memory systems.
Rakesh Kumar is an Associate Professor in the Department of Computer Science at NTNU, affiliated with the Computer Architecture Lab (CAL). He received his PhD from UPC Barcelona in 2014 and previously worked at Uppsala University, the University of Edinburgh, and Intel Barcelona Research Center. His research focuses on improving datacenter efficiency through microarchitecture and memory systems, hardware/software co-design, and dynamic code translation. Education: PhD in Computer Architecture, UPC Barcelona (2014) MEng in Microelectronics, BITS Pilani (2008) BTech in Electronics and Communications, Kurukshetra University (2005) Research Interests: His work emphasizes processor microarchitecture, memory systems, and energy-efficient designs. Key areas include hardware/software co-design (e.g., Nvidia Denver alternatives), dynamic vectorization, and server optimization. Recent projects target server front-end bottlenecks, address translation efficiency, and BTB organization for data centers. Publications: Recent work includes contributions to IEEE/ACM MICRO, HPCA, and ISCA, focusing on topics like uneven block size instruction caches, address translation optimizations, and server architecture improvements. Awards: Intel Spontaneous Level II/Excellence Award (2014) Distinguished Artifact Award at IEEE/ACM MICRO 2023 Teaching & Advising: Teaches courses like TDT4258 Low Level Programming and advises students on projects such as vector unit design and microarchitecture optimization. Active in mentoring PhD candidates and leading the Computer Architecture Lab. Labs/Teams: Affiliated with the Computer Architecture Lab (CAL) and collaborates on projects like DARCO, an infrastructure for HW/SW co-designed virtual machines.
Adam Chlipala is the Arthur J. Conner (1888) Professor of Computer Science at the Massachusetts Institute of Technology (MIT), where he is a faculty member in the Department of Electrical Engineering and Computer Science (EECS), the Computer Science and Artificial Intelligence Laboratory (CSAIL), and leads the Programming Languages & Verification Group. He has been a faculty member at MIT since 2011, following a postdoctoral position at Harvard University. PhD in Computer Science, UC Berkeley (2007) BS in Computer Science, Carnegie Mellon University (2003) His research lies at the intersection of programming languages and formal methods, with a strong emphasis on using the Coq proof assistant to build verified compilers, cryptographic systems, and hardware-software stacks. His work spans from high-level language design to gate-level hardware verification, aiming for end-to-end correctness proofs. Recent efforts focus on high-performance parallel computing systems with full formal assurance. The 15 most recent publications highlight a consistent trend in verified compilation, cryptographic security, hardware verification, and tensor/ML program optimization. His work increasingly integrates software and hardware verification, emphasizing modular, extensible frameworks and end-to-end correctness. Key themes include side-channel resistance, automated proof techniques, and practical deployment of formally verified systems. Advisory Board Member, BlueRock Systems (formerly BedRock Systems) Member, DARPA Information Science and Technology (ISAT) Study Group (2018–2022) Advisory Board Member, SiFive Former Advisor, krypt.co (acquired by Akamai) Chlipala has advised numerous PhD and Master’s students and regularly teaches core MIT courses such as 6.009 (Fundamentals of Programming), 6.042 (Mathematics for Computer Science), and 6.822/6.5120 (Formal Reasoning About Programs). He is the author of the widely used textbook Certified Programming with Dependent Types and co-developer of the FRAP (Formal Reasoning About Programs) educational materials. He is also the founder of Nectry, a startup based on Ur/Web and UPO, aiming to democratize enterprise application development through AI-assisted, type-safe programming. His research group develops tools and frameworks for modular verification, verified compilation, and formal analysis of complex digital systems. The work is deeply collaborative, involving students, industry partners, and open-source contributions via GitHub. Projects like Fiat Cryptography have been deployed in major web browsers, demonstrating real-world impact.
Dr. Chenxi Wang is an Assistant Professor at the University of Texas at Arlington's College of Engineering, Department of Computer Science and Engineering. Her research focuses on deep learning, computer vision, and wireless sensor networks. She has received multiple scientific awards including the UTA CARES Grant and Chancellor’s Medal from University of Massachusetts Lowell. PhD in Computer Engineering from University of Massachusetts Lowell (2022) MS in Computer Engineering from University of Massachusetts Lowell (2018) BS in Software Engineering from Zhengzhou University of Light Industry (2014) Dr. Wang teaches courses in computer architecture, software engineering, microprocessor systems, and artificial intelligence. Her research interests span a wide range of topics in artificial intelligence including: Computer Vision and Human Pose Estimation Transformer-based neural architectures Model optimization and large-scale dataset construction Wireless sensor network applications Her recent publications demonstrate expertise in human pose estimation, neural architecture design, and hardware acceleration. She has served as a reviewer for multiple prestigious conferences and journals in computer science and engineering. Dr. Wang has received numerous scientific awards including: UTA CARES Grant for OER Creation (2024) Chancellor’s Medal from University of Massachusetts Lowell (2023) MIPR Registration Scholarship (2022) Runner-Up Award at Harvard-MIT-Stanford Future Tech Startup Competition (2022)
Vladimir Kolesnikov is a Professor and Senior Associate Chair at the Georgia Institute of Technology, jointly affiliated with the School of Computer Science and the School of Cybersecurity and Privacy. He holds a Ph.D. in Computer Science from the University of Toronto (2006) and previously worked at Bell Labs. His research focuses on cryptography and secure computation, with a particular emphasis on practical and foundational aspects of two-party computation, garbled circuits, homomorphic encryption, and secure systems. He has contributed to projects like SCALES (Secure Computation with Ephemeral Servers) and has authored numerous papers and patents. His work also spans Smart Grid security, wireless authentication, and standards development (e.g., WiMAX). He serves as a PI on grants from IARPA and the Office of Naval Research, and his research bridges theory and practical applications in privacy-preserving technologies. Education Ph.D. in Computer Science, University of Toronto, 2006 Research Interests Dr. Kolesnikov’s work revolves around advancing cryptographic techniques for secure computation, including optimizing garbled circuits, exploring zero-knowledge proofs, and developing frameworks for privacy-preserving systems. His interests also extend to key exchange protocols, biometric authentication, and secure network design. He emphasizes both theoretical underpinnings and practical implementations, often addressing scalability and real-world applicability. Grants & Projects Principal Investigator (PI) on IARPA and ONR projects focused on cryptographic systems and secure computation Contributions to SCALES, a framework enabling secure computation with small clients and ephemeral servers Labs & Teams His research is conducted in collaboration with interdisciplinary teams at Georgia Tech, focusing on cryptographic implementations, secure hardware-software co-design, and privacy-preserving technologies.
Marco Liess serves as a Scientific Staff Member and doctoral candidate at the Chair of Integrated Systems within the TUM School of Computation, Information and Technology. His work focuses on hardware aspects of network interfaces and processing resources, with particular emphasis on SmartNIC development for next-generation networking systems. The chair participates in multiple research initiatives including the 6G Future Lab Bavaria and 6G Life projects. Dr. Liess holds a Master of Science in Electrical Engineering and Information Technology from TUM (2019-2021), with specialization in Embedded and Control Systems. His master's thesis on 'Frame Synchronization for Satellite-based IoT Applications' was completed at the German Aerospace Center (DLR). Previously, he earned a Bachelor of Science in the same field (2016-2019), focusing on Communication Networks, Embedded Systems, and Security, with his bachelor's thesis on 'Efficient Key Establishment for IoT Applications' conducted at Fraunhofer AISEC. His research primarily investigates hardware acceleration of data paths between network interfaces and processors, memory bottleneck avoidance, dynamic power management, and efficient hash algorithms. These interests align with current 6G research directions focusing on deterministic real-time processing for mission-critical applications. His work bridges hardware design (particularly FPGA implementations), operating system interactions, and networking protocols to create energy-efficient, high-performance network processing solutions. Analysis of his publication record reveals strong focus on SmartNIC architectures, with consistent contributions to major conferences in networking and computer architecture. His work demonstrates progression from satellite IoT communications toward advanced packet processing pipelines and real-time networking solutions for 6G infrastructure. Key themes include hardware-software co-design, power efficiency, and deterministic performance guarantees for time-sensitive networking applications. As an academic supervisor, Dr. Liess actively mentors students through various thesis projects ranging from FPGA-based network testers to Linux scheduler optimizations. His teaching responsibilities include 'Chip Multicore Processors' since SS 2024 and previously supervised 'Seminar Integrierte Systeme' and 'Seminar on Topics in Integrated Systems' from WS 2022/23 to WS 2023/24. Current projects under his supervision address critical challenges in 100Gbps networking, hardware tracing mechanisms, and server state tracking using SmartNIC technology.
Saeid Moslehpour is Chair and Associate Professor in the Department of Electrical and Computer Engineering at the University of Hartford's College of Engineering, Technology, and Architecture. He holds a Ph.D. in Industrial Technology and Computer Engineering (1993) from Iowa State University, along with multiple degrees from the University of Central Missouri including an Ed.Sp in Industrial Technology. Ph.D., Industrial Technology and Computer Engineering - Iowa State University (1993) Ed.Sp, Industrial Technology - University of Central Missouri MS, Electronics - University of Central Missouri BS, Electronics - University of Central Missouri His research focuses on Soft Processors , Electronic Modeling , and Cyber Learning , with expertise in SPICE modeling, FPGA/VHDL/Verilog programming, microprocessor design, telecommunications, and digital signal processing. He has pioneered laboratory developments including wireless, telecommunications, and surface roughness analysis systems. Recent work includes publications on EEG signal analysis , space systems hazard analysis , and embedded electronics . He received academic honors from Phi Kappa Phi and Epsilon Pi societies and maintains certifications in telecommunications and Cisco networking systems. Phi Kappa Phi Academic Honor Society (1993) Epsilon Pi Industrial Technology Honor Society (1993) Excellent Student Scholarship (1992-94) As an ASEE editor and committee chair, he has shaped engineering education policy and assessment. His industry collaborations with Northern Net Technology and Pars Server Tehran demonstrate practical applications of his work.
