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• Computer Architecture
• Microarchitecture
• Memory Systems
• +4 more

Rakesh Kumar is an Associate Professor in the Department of Computer Science (IDI) at the Norwegian University of Science and Technology (NTNU) , affiliated with the Computer Architecture Lab (CAL) within the Faculty of Information Technology and Electrical Engineering . Prior to joining NTNU, he held postdoctoral and research associate positions at Uppsala University and the University of Edinburgh, and interned at Intel Barcelona Research Center. Research Interests include improving large-scale datacenter efficiency through microarchitecture and memory system optimizations, hardware/software co-designed processors, dynamic code translation, vectorization, and serverless function execution. His work explores ready-aware instruction scheduling, branch prediction organization, and address translation mechanisms. Scientific Contributions span publications at top-tier conferences like MICRO (2024, 2023, 2018, 2016) HPCA (2020, 2019, 2023, 2022) ASPLOS (2018) DATE (2019, 2021) Journal articles appear in ACM Transactions on Computer Systems and IEEE Computer Architecture Letters . Awards include Intel Spontaneous Level II/Excellence Award (2014) Best Presentation Award at HiPC-SS08 (2008) Best Paper Award at National Conference on High Computing Technologies (2008) Distinguished Artifact Award at MICRO 2023 PhD Supervision involves advising students like Roman Kaspar Brunner, Elias Orrem, and Truls Asheim on topics spanning microarchitecture, vector units, and runahead execution policies.

• Computer Architecture
• Processor Microarchitecture
• Memory Systems
• +4 more

Rakesh Kumar is an Associate Professor in the Department of Computer Science at NTNU, affiliated with the Computer Architecture Lab (CAL). He received his PhD from UPC Barcelona in 2014 and previously worked at Uppsala University, the University of Edinburgh, and Intel Barcelona Research Center. His research focuses on improving datacenter efficiency through microarchitecture and memory systems, hardware/software co-design, and dynamic code translation. Education: PhD in Computer Architecture, UPC Barcelona (2014) MEng in Microelectronics, BITS Pilani (2008) BTech in Electronics and Communications, Kurukshetra University (2005) Research Interests: His work emphasizes processor microarchitecture, memory systems, and energy-efficient designs. Key areas include hardware/software co-design (e.g., Nvidia Denver alternatives), dynamic vectorization, and server optimization. Recent projects target server front-end bottlenecks, address translation efficiency, and BTB organization for data centers. Publications: Recent work includes contributions to IEEE/ACM MICRO, HPCA, and ISCA, focusing on topics like uneven block size instruction caches, address translation optimizations, and server architecture improvements. Awards: Intel Spontaneous Level II/Excellence Award (2014) Distinguished Artifact Award at IEEE/ACM MICRO 2023 Teaching & Advising: Teaches courses like TDT4258 Low Level Programming and advises students on projects such as vector unit design and microarchitecture optimization. Active in mentoring PhD candidates and leading the Computer Architecture Lab. Labs/Teams: Affiliated with the Computer Architecture Lab (CAL) and collaborates on projects like DARCO, an infrastructure for HW/SW co-designed virtual machines.