Ramakrishna Upadrasta is an Associate Professor in the Department of Computer Science & Engineering and Heritage Science & Technology at Indian Institute of Technology Hyderabad. He earned his PhD from University of Paris-Sud and INRIA, Paris, with a focus on improving scalability in polyhedral compilation tools. His academic journey includes an M.S. from Colorado State University, M.Tech from Indian Institute of Science (IISc), and B.E. in Electrical and Electronics Engineering from Andhra University. His research expertise includes: Domain Specific Programming Languages for Parallelization LLVM Optimizations Polyhedral Compilation Abstract Interpretation Sub-polyhedral Approximations High-Performance Computing (HPC) He leads the IITH-LLVM group and collaborates with industries on compiler technologies. His work addresses scalability vs. precision trade-offs in static analysis tools and extends polyhedral compilation frameworks like Pluto and Polly. Scientific Recognition : HiPEAC paper award for his POPL-2013 publication As an educator, he has taught advanced compiler courses (e.g., CS6250, CS5260) and coordinated interdisciplinary initiatives, including Sanskrit language courses via Samskrita Bharati. His students span PhD, M.Tech, and B.Tech levels, focusing on compiler design and parallelization.
Jan Reineke is a Professor of Computer Science at Saarland University , where he leads research at the intersection of hardware and software. His work focuses on timing-predictable microarchitectures, real-time systems, and hardware-software security contracts. Affiliation: Saarland University (since 2012) Previous: Postdoctoral scholar at UC Berkeley (2009-2011) Research Interests include static program analysis, real-time systems, computer architecture, and hardware-related security issues. His group develops tools like LLVMTA , uops.info , and Spectector for cache analysis, microarchitectural profiling, and speculative execution security. Design of timing-predictable processors (RTSS 2018, RTSS 2019) Exact LRU cache analysis (CAV 2017, POPL 2019, RTSS 2019) Detection of speculative information flows (S&P 2020, S&P 2021) Quantitative cache analysis frameworks (RTAS 2025) Recent Articles span cache timing analysis, speculative execution vulnerabilities, and performance modeling. Keywords include Real-Time Systems , Security , Computer Architecture , and Static Analysis , with sub-fields covering cache persistence, hardware-software contracts, throughput prediction, and formal verification of side-channels. Scientific Awards include an ERC Advanced Grant (2021) , multiple best paper awards (RTAS 2025, DATE 2024, CCS 2023), and the Intel Early Career Faculty Honor Program (2012). Advising and Grants : He actively recruits PhD students and postdocs for hardware-software security research, supported by the ERC grant. His lab's alumni include Dr. Sebastian Hahn, and he has hosted numerous student assistants. Labs and Teams : He leads the Real-Time and Embedded Systems Lab at Saarland Informatics Campus, collaborating on projects like uops.info (Intel microarchitectural profiling) and chi (cache hierarchy inference).
Auguste Olivry is a researcher at the French Institute for Research in Computer Science and Automation (Inria), France, specializing in programming languages and compiler optimization with focus on data movement analysis for computational workloads. Research interests include: Data Movement Lower Bounds Derivation I/O Complexity Analysis for Affine Programs Polyhedral Model Applications Memory Hierarchy Optimization Compiler Techniques for Data Locality Olivry's work addresses fundamental challenges in optimizing memory access patterns in nested loop programs, with significant implications for high-performance computing and compiler design. The research develops formal methods to automatically derive bounds on data movement and I/O complexity, helping establish theoretical limits for program optimization. Recent publications demonstrate expertise in creating analytical frameworks that characterize data movement requirements in programs with affine loop structures and array accesses, contributing to the theoretical foundations of compiler optimization.
Fabrice Rastello is a leading researcher at Inria, France, where he serves as the leader of the CORSE (Compiler Optimization and Runtime SystEms) research team. His expertise spans automatic parallelization and compiler back-end optimization, with significant contributions to Static Single Assignment (SSA) form theory and register allocation techniques. Affiliated with University Grenoble Alpes - Inria - CNRS - Grenoble INP - LIG, he maintains an active research profile with continuous publications in top-tier conferences including PLDI, CGO, and PPoPP. His research interests focus on combining theoretical foundations with practical applications in compiler design. Key areas include automatic parallelization techniques (building on his PhD work on tiling as a loop transformation), compiler back-end optimization, and the emerging field of hybrid compilation that bridges static compilation with runtime techniques. He has made significant contributions to register allocation for JIT compilation in the context of SSA properties, advising three PhD students on related topics. Analysis of his recent publications reveals a strong trend toward data movement optimization, with numerous papers on I/O complexity bounds, cache modeling, and microarchitectural performance analysis. His work spans both theoretical computer science and practical applications, including contributions to healthcare technology during the pandemic with the eSpiro ventilator project. He has also explored intersections between compiler techniques and machine learning, particularly in using ML for performance modeling. Fabrice Rastello serves on program committees for major conferences in the field, including PLDI, CGO, and CC, demonstrating his standing in the research community. His 2022 book 'SSA-based Compiler Design' as editor further establishes his authority in compiler theory and practice. His recent work shows continued innovation in compiler techniques, with publications in 2024 demonstrating ongoing research activity across multiple domains including cache modeling, program analysis, and machine learning applications.
David Bremner is a Professor of Computer Science at the University of New Brunswick (UNB) with a cross-appointment to the Department of Mathematics and Statistics. He holds degrees from the University of Calgary (B.Sc. Hons., 1990), Simon Fraser University (M.Sc., 1993), and McGill University (Ph.D., 1997). After a postdoctoral fellowship at the University of Washington (1997-1999), he joined UNB in 2000. His research focuses on Programming Languages, Computational Geometry, and Mathematical Optimization. He teaches courses such as Programming Language Interpretation and contributes to software projects like inetools and Sparktope . Active in academic service, he organizes programming competitions and oversees graduate studies. His work emphasizes practical applications in memory management, JIT compilation, and algorithm design.
David Monniaux is a senior researcher (directeur de recherche) at CNRS, the largest French national scientific research agency. He works at VERIMAG, a computer science laboratory jointly operated by CNRS and the University of Grenoble. His research focuses on proving software correct, connecting to computability theory, complexity theory, and mathematical logic. Dr. Monniaux holds a PhD in Computer Science (2001, Université Paris Dauphine) and a habilitation in Computer Science (2009, Université Joseph Fourier, Grenoble), as well as an agrégation in mathematics. His research interests span programming languages, static analysis, model checking, compilers, and assisted proof. He has particular expertise in proving strong properties of critical software used in civil aviation, especially regarding numerical overflows and floating-point computations. He has also worked on cryptographic protocols and probabilistic systems. His approach combines abstract interpretation, formal verification, and mathematical logic to address software correctness problems. Dr. Monniaux's recent work shows a strong focus on static analysis techniques, program verification, and formal methods. His publications demonstrate expertise in polyhedral analysis, strategy iteration, and the application of SMT solving to program analysis problems. His research bridges theoretical computer science with practical applications in safety-critical systems. Among his notable scientific contributions are projects like VERASCO (integrating static analysis into the CompCert certified compiler), STATOR (exploring advanced techniques for automatic inference of program invariants), and ASOPT (developing new algorithms for static program analysis). Dr. Monniaux has advised several students who have gone on to successful careers, including Julien Henry (now at Grammatech), Alexis Fouilhé (now in industry), George (Egor) Karpenkov (now at Apple Inc.), and Alexandre Maréchal (post-doctoral researcher at LIP6). He currently advises Hang Yu and Valentin Touzeau. He is actively involved in the programming languages and formal methods research community, serving on program committees for major conferences including POPL, PLDI, and VMCAI.
Tobias Grosser is an Associate Professor in Compiler Design at the Department of Computer Science and Technology, University of Cambridge. His research spans compilation, programming language design, and performance programming with applications to climate science, quantum computing, and hardware design. He leads an active research group focusing on making compilers more modular, predictable, and trustworthy while bridging the gap between developers and compilers. His research interests include: Compilers and polyhedral compilation Static and dynamic program analysis High-performance computing and loop optimization Domain-specific compilation for accelerators (GPU, FPGA) Formal verification for compiler correctness Machine learning applications to compiler design His recent publications demonstrate significant contributions to multi-level intermediate representations (MLIR), compiler verification using Lean, and performance modeling. His work on xDSL provides a Python-native compiler framework that enables rapid prototyping of compiler infrastructure. His research group has developed tools like FPL (Fast Presburger Library) for loop optimization in deep learning and scientific computing. Scientific awards include two Amazon Research Awards (2023-2024) for work in automated reasoning, a Google PhD Fellowship, and an Ambizione Fellowship at ETH Zurich. He has advised numerous PhD students and researchers who have gone on to positions at Google, ETH Zurich, NVIDIA, and Intel. He actively collaborates with industry through the Amazon Scholars program and hosts regular Compiler Social events in Cambridge. His research vision emphasizes connecting compiler technology with societal challenges like climate change while maintaining a strong commitment to open-source development and diversity in computer science.
Dr. Zhiru Zhang is a Professor in the School of Electrical and Computer Engineering at Cornell University and a member of the Computer Systems Laboratory. His research focuses on new algorithms, methodologies, and design automation tools for heterogeneous computing systems, with recent publications centering on high-level synthesis (HLS), hardware specialization for machine learning, and programming models for software-defined FPGAs. Dr. Zhang earned his Ph.D. in Computer Science from UCLA, where he co-founded AutoESL based on his dissertation research on HLS. AutoESL was acquired by Xilinx (now AMD), and its HLS tool evolved into Vivado HLS (now Vitis HLS), which is widely used for designing FPGA-based hardware accelerators. He also holds a B.S. in Computer Science from Peking University and an M.S. in Computer Science from UCLA. Dr. Zhang's research interests span hardware design, high-level synthesis, FPGA acceleration, machine learning acceleration, heterogeneous computing systems, and computer architecture. His work bridges the gap between software algorithms and hardware implementation, focusing on creating efficient design automation tools that enable specialized hardware for emerging applications, particularly in AI and machine learning. His recent publications demonstrate strong trends in differentiable programming for hardware design, sparse computation optimization, and efficient implementation of large language models on FPGAs. Dr. Zhang has received numerous prestigious awards including being named an IEEE Fellow, the Intel Outstanding Researcher Award, AWS AI Amazon Research Award, Facebook Research Award, Google Faculty Research Award, DAC Under-40 Innovators Award, Rising Professional Achievement Award from UCLA, DARPA Young Faculty Award, IEEE CEDA Ernest S. Kuh Early Career Award, and NSF CAREER Award. His papers have won multiple Best Paper Awards from top conferences including ASPLOS (2025), ISPD (2025), FPGA (2024, 2022, 2021, 2019), AutoML (2024), FCCM (2018), ACM TODAES (2012), and Top Picks in Hardware and Embedded Security (2020). His papers on HLS scheduling and application-specific instruction-set processor (ASIP) compilation have been inducted into the ACM/SIGDA TCFPGA Hall of Fame for the classes of 2022 and 2023, respectively. On the teaching side, Dr. Zhang has received the Ruth and Joel Spira Award for Excellence in Teaching (2018) and twice the Michael Tien'72 Excellence in Teaching Award (2016, 2022), the highest recognition for teaching in the College of Engineering. He teaches courses including ECE 5775/6775: High-Level Digital Design Automation, ENGRD/ECE 2300: Digital Logic and Computer Organization, ECE 6980: Special Topics on Hardware Acceleration of Deep Learning, ENGRG 1050: Freshman Engineering Seminar, and ECE 5950: Special Topics on High-Level Digital Design Automation. Dr. Zhang leads an active research group with numerous PhD students and postdocs. His current students include Jordan Dotzel, Jie Liu, Zichao Yue, Yixiao Du, Yaohui Cai, Andrew Butt, Hongzheng Chen, Jiajie Li, Niansong Zhang, Matthew Hofmann, Zhanqiu Hu, Vesal Bakhtazad, and Grace Dinh. His alumni have gone on to successful careers at companies like NVIDIA, Google, AWS AI, Meta, Microsoft, and academic positions at universities including University of Illinois Chicago and Zhejiang University. The group has received multiple research grants from industry partners including AWS, Intel, and Google.
Martin Moreno is a tenure-track Assistant Professor in the Department of Computer Science and Engineering at The Ohio State University. His office is located in Dreese Laboratories at 2015 Neil Ave, Columbus, OH. His research focuses on the intersection of compilers, programming languages, high-performance computing, and quantum computing, with goals to enhance program execution speed, reliability, and portability across architectures. Research Interests: Dr. Moreno specializes in polyhedral compilation, GPU optimizations, quantum computing abstractions, distributed-memory algorithms, and energy-aware computing. His work bridges theoretical compiler design with practical performance improvements for modern hardware, including GPUs and quantum processors. Recent Research Trends: Analysis of his 15 most recent publications reveals strong emphasis on: 1) Automated code generation for distributed systems and tensor computations, 2) Quantum program optimization through affine transformations, 3) Energy-efficient GPU computing via polyhedral models, and 4) Novel compiler frameworks for task-based parallelism. His work consistently integrates formal methods (e.g., SMT solvers) with practical runtime systems. Student Advising: Actively seeks motivated students for research projects in compiler optimizations and quantum computing. Applicants to OSU are encouraged to list him as a potential advisor and mention PLSE/HPC interests in statements of purpose.
Oktay Gunluk is the Gary C. Butler Family Professor in the H. Milton Stewart School of Industrial and Systems Engineering at Georgia Institute of Technology (Georgia Tech). Prior to joining Georgia Tech, he was a professor of practice in the School of Operations Research and Information Engineering at Cornell University and the manager of the Mathematical Optimization and Algorithms group at IBM Research. He also spent three years as a researcher in the Operations Research group at AT&T Labs, where he worked on various large-scale applied optimization projects. His educational background includes: Ph.D. in Operations Research (1995) from Columbia University M.Phil. in Operations Research (1993) from Columbia University M.S. in Industrial Engineering (1989) from Boğaziçi University B.S. in Industrial Engineering (1987) from Boğaziçi University Professor Gunluk's research focuses on theoretical and computational aspects of discrete optimization problems, primarily in integer programming. His seminal work centers on cutting planes for mixed-integer sets, and more recently he has developed integer programming approaches to classification and clustering problems in machine learning with considerations for fairness and interpretability. His work bridges theoretical optimization with practical applications in areas such as quantum computing, fair machine learning, and supply chain optimization. The interdisciplinary nature of his research is reflected in his publications spanning operations research journals, computer science conferences, and machine learning venues. His notable recognition includes: Gary C. Butler Family Professorship at Georgia Tech Professor Gunluk has advised several PhD students including Reka Agnes Kovacs (Oxford, 2023), Connor Lawless (Cornell, 2024), and Ishan Bansal (Cornell, 2024). His research has been supported by collaborations with industry partners including IBM Research where he led the Mathematical Optimization and Algorithms group. His work has addressed optimization challenges in telecommunications, quantum computing, and machine learning with practical implementations. At IBM Research, Gunluk managed the Mathematical Optimization and Algorithms group, leading a team focused on developing advanced optimization techniques for both theoretical advancement and practical application. His work has bridged the gap between academic research and industrial implementation, particularly in the areas of network design, quantum computing algorithms, and fair machine learning systems, demonstrating the real-world impact of his optimization expertise.
James Emil Avery is an Associate Professor at the Department of Computer Science, Faculty of Science, University of Copenhagen. His research spans abstract interpretation, termination analysis, and quantum chemistry applications using Coulomb Sturmians. He actively contributes to program analysis, computational methods in physics, and discrete mathematics. Research areas: Formal languages, operator algebra, quantum theory, and computational nanoscience Academic activities: VILLUM Young Investigator Program (2017), Editor for IET Nanobiotechnology (2017-2021) Technical publications: 15+ works on quantum chemistry methods, graph theory, and parallel computing His recent work includes simulating fullerene formation, solving wave equations on non-Euclidean surfaces, and developing symmetry-adapted basis sets. He has presented at international conferences on topics ranging from wave equation modeling to carbon nanostructure analysis. Scientific Awards: VILLUM Young Investigator Program grant recipient As an active researcher, Avery has participated in collaborative projects like the ERC Starting Grant evaluation and contributed to programming language development through the Bohrium framework. His editorial work at IET Nanobiotechnology demonstrates commitment to scientific peer review.
Utpal Bora is a Researcher at the University of Cambridge's Department of Computer Science and Technology. His research focuses on Programming Languages, Semantics, Verification, and Computer Architecture with an emphasis on static analysis of parallel programs, compiler optimization techniques, and performance analysis. He has contributed to projects such as LLOR (automated OpenMP program repair) and Llov (static data-race detection for OpenMP). His work bridges compiler design, parallel computing, and formal methods to improve software reliability and hardware efficiency. Research Interests: Static Analysis of Parallel Programs Compiler Optimization (LLVM) Data-Race Detection in OpenMP Instruction-Level Parallelism (ILP) Performance Modeling (CPI Analysis) Formal Verification of Concurrent Systems Recent work trends show a focus on enhancing parallel programming correctness through automated repair and static analysis tools, alongside optimizing code execution via compiler-level transformations and hardware architecture improvements. His contributions address critical challenges in parallel computing scalability and compiler-driven performance enhancement.
Tina Jung is a Lecturer at Saarland University's Department of Computer Science. Her research focuses on Program Analysis, Memory Safety, and compiler optimizations, particularly through projects like MemInstrument (memory-safe C code compilation) and PICO (Presburger arithmetic-based compiler optimizations). She has taught multiple programming courses, including Programming 2 and seminars on Memory Safety and Compilers for Machine Learning. Her academic work includes contributions to compiler-based memory safety instrumentations and performance optimization techniques. She holds a B.Sc. in Computer Science from Saarland University (2015) and has been actively involved in teaching since 2011. Contact details include her office at Saarland Informatics Campus (Building E1 3, Room 403) and ORCID 0000-0001-8657-7190 .
Catherine Vigouroux is an Associate Professor at Université Grenoble Alpes, holding a dual role as Deputy Director of the Department of Science and Technology. She specializes in real-time systems, formal verification, and embedded systems. Her research focuses on worst-case execution time (WCET) analysis, timing models, and compiler optimization, with contributions to projects like W-SEPT. She has co-chaired the RTNS 2017 conference and actively contributes to academic workshops and publications in her field. Her work bridges theoretical formal methods (e.g., Coq, PVS) with practical applications in embedded and real-time systems. Her academic contributions include seminal work on linear relation analysis for WCET estimation and Cartesian factoring in polyhedral analysis. She has also published extensively on timing analysis for synchronous programs and schedulability in real-time systems. Her teaching and administrative roles reflect her commitment to advancing science and technology education at the university level.
Prof. Dr. Sergei Gorlatch is a full professor at the University of Münster, Germany, in the Department of Mathematics and Computer Science, where he holds the Chair of Practical Computer Science (Parallel and Distributed Systems) within the Institute of Computer Science. He has been a leading figure in high-performance and parallel computing since joining the university in 2003. University: University of Münster School: Department of Mathematics and Computer Science Department: Institute of Computer Science Academic Rank: Professor His research focuses on algorithm and software development for modern computer systems, particularly in parallel and distributed computing, high-performance computing (HPC), GPU-based systems, cloud and grid computing, and performance optimization. His work bridges theoretical formal methods and practical applications, especially in real-time online interactive systems such as online games and simulations. He has pioneered frameworks like SkelCL, dOpenCL, and the Real-Time Framework (RTF) to simplify parallel programming and improve performance portability. The recent publications (2020–2024) reflect a strong trend in GPU programming, performance optimization, formal verification, and distributed systems. Key themes include the development of safe and high-level GPU languages (e.g., Descend), autotuning and model checking for performance, multi-cloud orchestration, and performance modeling of legacy and real-time systems. His work often combines compiler techniques, functional programming, and systematic transformations to achieve efficient and portable code. Best Poster Award – PUMPS+AI, 2019 Best Paper Award – CGO, 2018 Alexander von Humboldt Research Fellowship, 1991 Prof. Gorlatch has supervised numerous students and researchers, many of whom are frequent co-authors on his publications. He has led multiple funded projects from DFG, EU (e.g., CoreGrid, MONICA), and industry (e.g., NVIDIA Graduate Fellowship). His work includes both theoretical contributions (e.g., algorithmic skeletons, formal verification) and applied systems development, demonstrating a strong record of advising, grant acquisition, and interdisciplinary collaboration. He is actively involved in several research labs and teams at the University of Münster, particularly those focused on parallel computing, GPU programming, and real-time systems. His group develops high-level programming models and tools to make parallel computing more accessible and efficient across diverse architectures.
