Sung-Kyu Lim is a Professor and the Motorola Solutions Foundation Professor in the School of Electrical and Computer Engineering at the Georgia Institute of Technology, where he serves as director of the GTCAD Laboratory. His educational background includes: B.S. in Computer Science from the University of California, Los Angeles (UCLA) in 1994 M.S. in Computer Science from UCLA in 1997 Ph.D. in Computer Science from UCLA in 2000 Professor Lim's research focuses on advancing VLSI design automation through physical design methodologies, 3D circuit integration, quantum circuit layout, micro-architecture exploration, and reconfigurable circuit optimization. His work bridges theoretical graph theory with practical electronic design automation challenges to improve circuit performance and scalability. His notable scientific distinctions include: NSF CAREER Award (2006) Advisory Board Member of ACM SIGDA (since 2003) Technical Program Committee roles for ICCD, ISPD, ISCAS, ASPDAC, and GLSVLSI conferences He leads the GTCAD Laboratory at Georgia Tech, driving innovation in computer-aided design tools for next-generation integrated circuits and systems.
Morteza Fayazi is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Utah, with an adjunct position in the Kahlert School of Computing. His research focuses on Electronic Design Automation (EDA), applying machine learning to automate analog and mixed-signal circuit design, and developing high-performance computing systems. He holds a B.Sc. from Sharif University of Technology, and M.S.E./Ph.D. degrees from the University of Michigan. His research interests include AI-driven EDA, RF/circuit automation, and energy-efficient processors. Key achievements include the MEDAL lab’s work on terahertz radars, systolic-array processors (e.g., DAP and Versa), and open-source frameworks like FASCINET and Tablext. He has received awards such as the 2024 College of Engineering Dean’s ETR Fund and the 2017 Outstanding Undergraduate Thesis Award. Teaching responsibilities include multiple iterations of the Digital System Design course (ECE/CS 3700). His work spans over 15 peer-reviewed articles in IEEE Transactions, ACM, and top conferences like ICCAD and VLSI-SOC, emphasizing automation, efficiency, and AI integration in hardware design.
Soheil Salehi is a tenure-track Assistant Professor in the Department of Electrical and Computer Engineering at the University of Arizona, with a joint appointment in Systems and Industrial Engineering. He is the Director of the Privacy-preserving, Intelligent, and Secure Computing (PRISM) Lab, established in August 2022. Prior to this, he was an NSF-Sponsored Computing Innovation Fellow and Postdoctoral Research Fellow at the University of California, Davis. Ph.D., Electrical and Computer Engineering, University of Central Florida, 2020 M.S., Electrical and Computer Engineering, University of Central Florida, 2016 B.S., Isfahan University of Technology, Iran, 2014 Dr. Salehi's research focuses on the intersection of hardware, AI, and security. His work spans hardware and AI-enabled security in IoT , Generative AI for hardware design and security , neuromorphic and biologically-inspired AI hardware , emerging spin-based devices , reconfigurable architectures , low-power VLSI circuits , and digital twins and mixed reality for semiconductor workforce development . He also explores the application of Generative AI in personalized education . His recent publications, spanning 2023–2025, reveal a strong trend toward integrating AI and machine learning into hardware security and design. Key themes include automated secure IC design flows , AI-driven hardware obfuscation , firmware and side-channel attack analysis , security in neuromorphic and spiking neural networks , and educational frameworks using digital twins and generative models . His work appears in top venues like DAC, ICCAD, USENIX Security, IEEE TCAS-I, and ISCAS. Outstanding Reviewer Award, IEEE/ACM Design Automation Conference (DAC), 2023 Best Presentation of the Symposium Award, UC Davis Postdoctoral Research Symposium, 2021 UCF Excellence by a Graduate Teaching Assistant (University-Level), 2016 Nominated for 30-under-30 Award, UCF, 2020 Nominated for Postdoctoral Research Excellence Award, UC Davis, 2022 Dr. Salehi has secured significant research funding as PI and Co-PI, including a $300K NSF SaTC EAGER grant on Generative AI-based Personalized Cybersecurity Tutor, a $174,000 University of Arizona PIF Award, and multiple RII grants totaling over $198K. He has also received industry funding from CHEST. He actively mentors students and leads the PRISM Lab, which focuses on privacy-preserving and intelligent secure computing. His service includes roles as Technical Program Committee (TPC) Member and Session Chair at premier conferences such as DAC, ICCAD, CCS, NDSS, and GLSVLSI. The PRISM Lab, under his direction, conducts cutting-edge research in secure and intelligent hardware systems, with applications in IoT, edge computing, and workforce development. The lab emphasizes interdisciplinary collaboration and innovation in both research and education.
Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.
University of California, Los AngelesUnited States
Jason Cong is the Volgenau Chair for Engineering Excellence and Distinguished Chancellor's Professor in the Computer Science Department at UCLA's Samueli School of Engineering. He directs the Center for Domain-Specific Computing (CDSC) and the VLSI Architecture, Synthesis, and Technology (VAST) Laboratory, and serves as Associate Vice Provost for Internationalization and Co-Director of UCLA/PKU Student and Scholar Program. Dr. Cong's research spans electronic design automation, customizable computing for machine learning and big-data applications, quantum computing, and highly scalable algorithms. His work has produced over 500 publications with more than 41,000 citations and an H-index of 106. His recent work focuses on quantum computing compilation, domain-specific acceleration for AI workloads, and high-level synthesis optimization techniques that leverage machine learning. His publication trend shows a strong emphasis on quantum computing and machine learning acceleration in recent years, with numerous papers on quantum layout synthesis, LLM acceleration, and high-performance FPGA implementations. His team has developed frameworks like TAPA for task-parallel dataflow programming and RapidStream for automated parallel implementation of FPGA designs. Member of National Academy of Engineering (2017) IEEE Robert N. Noyce Medal recipient (2022) Phil Kaufman Award recipient (2024) ACM Chuck Thacker Breakthrough Award recipient (2024) 18 Best Paper Awards across major conferences Multiple 10-Year Retrospective Most Influential Paper Awards Dr. Cong has graduated 50 PhD students, many of whom are now faculty at major research universities or hold key positions at leading tech companies. He has led over 100 research projects funded by DARPA, NSF, SRC, and industry sponsors. His entrepreneurial activities include founding three successful companies (Aplus Design Technologies, AutoESL, and Falcon Computing Solutions), all acquired by major EDA players. His VAST Laboratory continues to push boundaries in domain-specific computing, with active research in quantum computing, AI acceleration, and high-performance FPGA implementations.
University of Illinois Urbana-ChampaignUnited States
Martin D F Wong serves as the Edward C. Jordan Professor of Electrical and Computer Engineering and Executive Associate Dean for the College of Engineering at the University of Illinois at Urbana-Champaign. He is affiliated with the Coordinated Science Laboratory and has been instrumental in advancing electronic design automation research. His educational background includes: B.Sc. in Mathematics, University of Toronto (1979) MS in Mathematics, University of Illinois at Urbana-Champaign (1981) Ph.D. in Computer Science, University of Illinois at Urbana-Champaign (1987) Wong's research centers on combinatorial optimization and algorithm design for VLSI systems, with particular expertise in lithography-aware physical design, field-programmable systems, and electronic packaging. His work bridges theoretical algorithms with practical semiconductor manufacturing challenges as feature sizes shrink below 20 nanometers. Current research focuses on integrating chip design with next-generation lithography technologies including triple-patterning, self-aligned double patterning, directed self-assembly, and extreme ultraviolet processes. His publication record shows consistent contributions to electronic design automation, with emphasis on manufacturing-aware physical design algorithms and circuit optimization techniques. Recent work addresses the critical interface between circuit layout and lithography processes as semiconductor technology advances to 14nm and beyond. Scientific recognition includes: Fellow of IEEE and ACM 2000 IEEE Donald O. Peterson Best Paper Award Multiple Best Paper Awards at DAC, ICCD, and ICCAD conferences IBM Faculty Awards (2000, 2004) NSF Research Initiation Award Wong has secured significant research funding including a $450,000 NSF grant for lithography-aware physical design and has supervised over 49 PhD students. His work continues the legacy of integrated circuit innovation at Illinois, building on foundational contributions like Jack Kilby's integrated circuit invention. Current research initiatives focus on optimizing chip design for next-generation manufacturing processes where optical interference challenges require co-design of layout and fabrication. He leads research within the Coordinated Science Laboratory, focusing on electronic design automation algorithms that address the growing complexity of semiconductor manufacturing at nanometer scales.
Shantanu Dutt is a full Professor in the Department of Electrical and Computer Engineering at the University of Illinois at Chicago , located in Chicago, IL. His office is in 930 SEO at 851 S. Morgan St, and he can be reached at dutt@uic.edu . Education Ph.D. in Computer Science and Engineering, University of Michigan, Ann Arbor (1990) M.Tech. in Computer Engineering, Indian Institute of Technology Kharagpur (1984) B.E. in Electronics and Communication Engineering, Maharaja Sayajirao University of Baroda (1983) Research Interests Professor Dutt’s research agenda centers on VLSI Computer-Aided Design (CAD) , with particular emphasis on physical design and incremental synthesis targeting both ASICs and FPGAs. He explores discrete optimization techniques to solve placement, routing, and partitioning problems. Another major thrust is FPGA built-in self-test (BIST) and trusted design , ensuring provable diagnosability and security against hardware Trojans. He also investigates fault-tolerant computing at both chip and system levels, and develops parallel and distributed computing algorithms for scalable performance. Scientific Awards 1996 Best Paper Award , ACM/IEEE Design Automation Conference, for “A probability-based approach to VLSI circuit partitioning” 1995 Most Influential Paper Award , Fault-Tolerant Computing Symposium, for “Design and reconfiguration strategies for near-optimal k-fault-tolerant tree architectures” Research Impact and Funding Professor Dutt has published extensively in top-tier journals (IEEE TVLSI, ACM TRETS, IEEE TCAD) and premier conferences (ICCAD, DAC, DATE, FTCS). His work has shaped incremental placement, timing-driven routing, FPGA security, and fault-tolerant multiprocessor architectures. While specific grant numbers are not listed, the breadth and longevity of his publication record indicate sustained funding from NSF, industry, and other agencies. Laboratory and Collaborations Although no formal laboratory name is provided, Professor Dutt’s research is conducted within the ECE department’s VLSI CAD and Fault-Tolerance groups, collaborating with graduate students and colleagues across the US and internationally.
University of Illinois Urbana-ChampaignUnited States
Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She also serves as the Acting Associate Dean for Research at the Grainger College of Engineering. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a collaboration between the University of Illinois, North Carolina State University, and Penn State University. Education: Ph.D. in Electrical Engineering, University of California, Berkeley, 1992 M.S. in Electrical Engineering, Stanford University B.S. in Electrical Engineering, Cornell University (with distinction) Research Interests: Her research focuses on machine learning applications in electronics, ESD-robust high-speed I/O circuit design, compact modeling, behavioral modeling of circuits, and CDM-ESD protection for advanced packaging technologies. Scientific Awards: IEEE Fellow for contributions to electrostatic discharge reliability of integrated circuits Best Student Paper Award, IEDM Outstanding and Best Paper Awards, EOS/ESD Symposium Technical Excellence Award, SRC NSF CAREER Award IBM Faculty Award ESD Association’s Industry Pioneer Recognition Award Advising and Grants: She supervises graduate and undergraduate researchers, primarily focusing on those with strong academic records and relevant experience. Her work is supported by NSF and other prominent organizations. Labs and Teams: She leads the CAEML center, which aims to apply machine learning to optimize microelectronic circuits and systems, enhancing design automation and reliability.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Patrick H. Madden is an Associate Professor and Director of the MS Information Systems program at the School of Computing, Binghamton University. His research focuses on combinatorial optimization, VLSI physical design automation, and algorithmic solutions for NP-Hard problems. He is also involved in interdisciplinary work in cryptography and biology-related optimization. Education: BS and MS from New Mexico Institute of Mining and Technology PhD from University of California, Los Angeles (UCLA) Professional Roles: Chair of ACM/SIGDA (Design Automation Special Interest Group) Chair of Design Automation Conference (DAC) Sponsors Committee Advisor to Binghamton ACM Student Chapter Coach for ICPC Programming Contest Teams Member of Watson School Graduation Committee Research Contributions: Leads the Optimality Research Group, developing optimization algorithms for VLSI CAD and medical software applications. Notable contributions include the Feng Shui placement tool and medical reference apps for iOS/Android platforms. Awards: SUNY Chancellor's Award for Excellence in Professional Service (2015) Grants & Collaborations: Collaborates with Prof. Monte McCollum (Cinema Department) on hybrid cinema projects and Dr. Joshua Steinberg (Physician) on medical software. Active in ACM committees and EDA conferences (DAC, ICCAD, ISPD). Labs/Teams: Directs the Optimality Research Group and oversees medical software collaborations through CS441/580 projects.
University of California , Santa Barbara (UCSB)United States
Professor Forrest Brewer is a faculty member in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB), affiliated with the College of Engineering. His research spans VLSI design, computer-aided design tools, and low-power computing, with a focus on unconventional engineering solutions. Education: PhD in Computer Science, University of Illinois BS in Physics (with honors), California Institute of Technology His work includes CMOS pulse-gate asynchronous logic for high-performance systems, sigma-delta modulation for signal processing, and formal verification strategies for asynchronous circuits. Applications range from radiation-hardened communication links for the Large Hadron Collider (LHC) to spiking neural networks for low-power computing in LIDAR/RADAR systems. Affiliations: California Nanosystems Institute Allosphere Steering Committee (Media Technology) With over 100 publications and 40 years of systems design experience, Brewer has contributed to defense programs, founded UCSB's Computer Engineering program, and served as Intel Faculty Fellow (1997). His lab, the Systems Synthesis Lab, explores collective dynamics and high-resolution, low-latency computation.
Azadeh Davoodi is a Vilas Distinguished Achievement Professor and Associate Chair of Undergraduate Studies in the Department of Electrical and Computer Engineering at the University of Wisconsin-Madison. Her research focuses on Electronic Design Automation (EDA), integrated circuit debug, and machine learning applications in VLSI design. She holds editorial roles in journals like IEEE TCAD and ACM TRETS, and has chaired major conferences such as ISPD 2015 and served on technical program committees for DAC, ICCAD, and others. Education: PhD in Electrical Engineering, University of Maryland-College Park (2006) Research Interests: Machine learning for VLSI chip design VLSI design automation for machine learning IC-CAD for emerging nanotechnologies Hardware security Recent Research Trends: Her work bridges machine learning and hardware design, with publications on neural network optimization, distributed inference, and explainable AI for circuit design. She emphasizes energy-efficient CNNs, latency reduction in edge computing, and security in split manufacturing. Awards: 2025 DATE Best Paper Candidate 2024 Vilas Distinguished Achievement Professor 2015 ACM Best Paper Award 2011 NSF CAREER Award Service and Grants: Leads NSF-funded projects on explainable ML for CAD and holds grants for distributed neural network synthesis. Her service includes roles as IEEE HKN member and editorial board positions. Labs/Teams: Engages in interdisciplinary research teams at UW-Madison, focusing on EDA innovation and hardware-software co-design.
Pierre-Emmanuel Gaillardon is a Professor in the Department of Electrical & Computer Engineering and Adjunct Professor in the School of Computing at the University of Utah. He holds a joint appointment since July 2024, having previously served as Assistant Professor (2016–2019) and Adjunct Assistant Professor in Computing (2016–2019). His research focuses on FPGA design, VLSI systems, nanoelectronics, and hardware security. He leads projects in emerging devices like TIGFETs, compute-in-memory architectures, and radiation-hardened FPGA fabrics. Teaching includes courses on Digital VLSI Design, Embedded Systems Design, and thesis supervision. He has secured grants from NSF, DARPA, and industry partners totaling over $10M, addressing topics like FPGA redaction, neuromorphic systems, and environmental sensors. Notable awards include the NSF CAREER Award (2018) and IEEE Senior Member elevation (2016). He actively serves on IEEE committees for nanoelectronics and EDA tools, contributing to standards like OpenFPGA.
University of Maryland, Baltimore CountyUnited States
Riadul Islam serves as an Assistant Professor in the Department of Computer Science and Electrical Engineering at the University of Maryland, Baltimore County (UMBC), maintaining his primary office in room 316 of the Information Technology and Engineering (ITE) Building. His academic appointment focuses on hardware design and verification within the institution's engineering framework. His educational qualifications include: Ph.D. in Computer Engineering from UCSC (2017) M.A.Sc. in Electrical and Computer Engineering from Concordia University, Montreal (2011) B.Sc. in Electrical and Electronic Engineering from Bangladesh University of Engineering and Technology (2007) Professor Islam's research centers on VLSI CAD tools and low-power digital/mixed-signal IC design , with significant contributions to current-mode clock networks, vehicular security systems, and error-robust circuit architectures. His work increasingly integrates machine learning for design automation while exploring neuromorphic computing applications and secure hardware implementations. This multidisciplinary approach bridges traditional IC design with modern AI-driven optimization techniques. Analysis of his 2023-2025 publications reveals three dominant research thrusts: (1) Machine learning applications in early-stage Design Rule Checking (DRC) prediction and clock network optimization, (2) Graph-based intrusion detection systems for automotive networks (particularly CAN bus security), and (3) Event-based vision systems and neuromorphic computing architectures. These areas demonstrate consistent innovation in merging hardware design with AI/ML methodologies for enhanced system reliability and efficiency. He directs the UMBC VLSI and SoC Research Group , which develops energy-efficient clocking networks, secure vehicular communication protocols, and compute-in-memory architectures. The lab maintains active collaboration with industry partners on hardware security and neuromorphic computing initiatives while supporting graduate student research in cutting-edge IC design methodologies.
Yu Cao is an Adjunct Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). He holds a Ph.D. in Electrical Engineering from the University of California, Berkeley (2002), an M.A. in Biophysics (1999), and a B.S. in Physics from Peking University (1996). His research focuses on nanoscale technology modeling, variability and reliability in electronics, and hardware design for on-chip learning. Key interests include predictive technology modeling, post-silicon integration, and energy-efficient semiconductor devices. Dr. Cao has led multiple grants funded by NSF, Samsung, Semiconductor Research Corporation, and academic institutions. His work emphasizes bridging technology and design automation gaps in nanometer-scale integration. Courses taught include VLSI design, digital systems, and graduate research supervision. He has authored two books and numerous articles on nano-CMOS modeling and physical design. His recent research advances include stable, efficient organic light-emitting diodes (OLEDs) and electrochromic devices leveraging phosphorescent molecular aggregates. These innovations address challenges in color stability, energy efficiency, and device lifetime. Notable grants include NSF-funded projects on hardware and algorithms for on-chip learning (2015–2016) and low-power bio-signal processing (2015–2016). His contributions span semiconductor reliability, nanoelectronic device applications, and predictive circuit simulation techniques.
