Geoffrey Nelissen is an Assistant Professor in the Department of Mathematics and Computer Science at Eindhoven University of Technology. He holds additional roles as a Research Scientist and Investigador Auxiliar at INESC TEC (Portugal), contributing to interdisciplinary research in real-time systems. His work focuses on schedulability analysis, parallel task execution, and real-time communication protocols, with applications in embedded systems and multicore architectures. Research Interests: Real-Time Scheduling Response Time Analysis Multi-core and Parallel Systems Time-Sensitive Networking (TSN) Formal Verification Recent work emphasizes schedule abstraction frameworks, memory contention analysis, and deterministic communication protocols. His research has received recognition through multiple best paper awards including ICESS 2021 and RTAS 2022. He actively contributes to conferences like RTSS and ECRTS while teaching courses on Real-Time Systems and Operating Systems. Collaborations span European institutions with focus on embedded systems, autonomous driving, and safety-critical applications. Current projects explore holistic approaches to WCRT analysis and resilient real-time communication architectures.
Giovanni De Micheli is a Professor of Electrical Engineering and Computer Science at EPF Lausanne, Switzerland. He also serves as Director of the Integrated Systems Centre and the Institute of Electrical Engineering at EPFL, and chairs the Scientific Committee of CSEM in Neuchatel. Previously, he held academic roles at Stanford University for 18 years, including Full Professor, Associate Professor, and Assistant Professor in the Department of Electrical Engineering. His research spans synthesis of digital circuits, hardware/software co-design, low-power design, and Networks on Chip (NoC) technology. 2003: IEEE Emanuel Piore Award 2000: Golden Jubilee Medal of the IEEE CAS Society 2000: ACM Fellow 1994: IEEE Fellow 1990: IEEE/CS Distinguished Service Award 1988: NSF Presidential Young Investigator Award His seminal contributions include pioneering C-based synthesis and Boolean matching algorithms for digital circuits, foundational work in dynamic power management using stochastic control, and the development of Network-on-Chip (NoC) technology. His publications, such as "Networks on Chips: A New SoC Paradigm" and "Dynamic Power Management for Portable Systems" , have shaped modern SoC design practices. With over 400 technical articles, 9 books, and an H-index of 56, his work remains highly influential.
Reetuparna Das is an Associate Professor at the University of Michigan in the Department of Computer Science and Engineering, School of Electrical Engineering and Computer Science (EECS). She previously worked as a research scientist at Intel Labs and as researcher-in-residence for the Center for Future Architectures Research (C-FAR). She co-founded the precision medicine start-up Sequal Inc. and leads the M-Bits research group, which is part of the Computer Engineering Lab at Michigan. Her research focuses on computer architecture and its intersections with software systems and device/VLSI technologies . Key projects include in-memory computing for BigData and ML, fine-grain heterogeneous architectures for mobile systems, and energy-efficient network-on-chip (NoC) designs for many-core processors. Her work has been funded by the NSF, C-FAR, Semiconductor Research Corporation, and Intel. She has authored over 50 papers, filed 7 patents, and received numerous awards, including the Sloan Foundation Faculty Fellowship CRA-W Borg Early Career Award NSF CAREER IEEE Top Picks MICRO/ISCA Hall of Fame inductions Das has served on over 40 program committees, is associate editor for TACO, and co-founded initiatives like WiCArch (Women In Computer Architecture) to promote diversity. She mentors students through outreach programs like Girls Encoded and Ada Lovelace opera events.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and Deputy Director and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research & Technology - Hellas (FORTH). He co-founded the European Research Center on Computer Architecture (EuReCCA) and is a founding partner of the European Network of Excellence on High-Performance and Embedded Architecture and Compilation (HiPEAC). PhD in Computer Science from University of California, Berkeley (1983) Co-founder of EuReCCA (2011) Contributed to RISC architecture (1980-1983), interconnection networks (1985-2011), and parallel computing (1993-2010) His research spans Scalable Multicore Systems , Interconnection Network Architecture , Packet Switch Design , Computer Architecture , and VLSI Systems . He has made foundational contributions to per-flow queueing, backpressure mechanisms, and wormhole IP over ATM, with applications in internet routers, data centers, and supercomputers. His publications focus on high-radix crossbar switches, flow control algorithms, and explicit interprocessor communication. Notable scientific awards include: ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981-1983) Greek State Fellowship (1973-1978) He has supervised 40 graduate theses and participated in 22 R&D projects totaling €9M, including HiPEAC (coordinator of interconnection networks), SARC (FPGA prototype design), and ENCORE (cache-optimized remote DMA). His work has received over 2000 citations, with an h-index of 23.
Biresh Kumar Joardar is an Assistant Professor in the Electrical and Computer Engineering Department at the University of Houston's Cullen College of Engineering. He holds a BE from Jadavpur University (2016) and PhD from Washington State University (2020), with postdoctoral training at Duke University as a Computing Innovation Fellow. His research integrates machine learning with hardware design to develop efficient deep learning accelerators, ReRAM-based architectures, and heterogeneous manycore systems. Current projects focus on enhancing reliability, security, and performance of AI hardware through in-memory computing and 3D integration techniques. Research themes include hardware security (e.g., Rowhammer mitigation), fault-tolerant neural network training, and hardware-software co-design for bioinformatics. Recent articles explore energy-efficient architectures for graph neural networks and cross-layer optimization for AI workloads. Awards: Best Paper Award, International Symposium on Networks-on-Chip (NOCS 2019) Joardar leads the Heterogeneous and In-Memory Computing Lab, seeking PhD students with backgrounds in VLSI, computer architecture, or machine learning. His work has been supported by NSF and industry partnerships.
Daniel Müller-Gritschneder is an Adjunct Teaching Professor (Privatdozent) at the Technical University of Munich (TUM), affiliated with the Chair of Electronic Design Automation. He leads the 'Electronic System Level' research group, focusing on embedded systems, TinyML, virtual prototyping, and hardware resilience. He temporarily served as head of the Chair of Real-Time Systems (2019–2020) and holds a senior membership in IEEE. His research spans: TinyML : Optimizing neural network inference for microcontrollers. Virtual Prototyping : Fast simulation for embedded software development (e.g., ETISS simulator). Runtime Verification : Hardware monitoring for safety-critical systems. Fault Tolerance : Cross-layer resilience against soft errors. Design Automation : NoC synthesis and RISC-V toolchain optimization. His publications emphasize RISC-V-based systems, TinyML deployment, fault injection, and embedded AI. Recent works show trends toward compiler-assisted security, thermal management, and automated design-space exploration for edge devices. Awards: Best Paper Award (SiPS 2019) Habilitation Award (Bund der Freunde der TUM, 2019) 2nd Best Paper (SMACD'15) Best Paper nominations at DAC'07, DATE'10, Analog'10, NOCS'13 He advises researchers in the Electronic System Level group and contributes to EU projects (e.g., Scale4Edge). His lab develops tools like ETISS, MLonMCU, and Seal5 for RISC-V and TinyML ecosystems.
Associate Professor Joshua San Miguel leads research in computer architecture and systems at the University of Wisconsin-Madison, with an affiliate role in Computer Sciences. His work focuses on energy-efficient computing for IoT devices, microarchitecture innovations, and networks-on-chip. He holds a PhD (2017) and BASc (2012) from the University of Toronto. Education: PhD in Electrical & Computer Engineering, University of Toronto (2017) BASc in Engineering Science (ECE), University of Toronto (2012) Research Interests: Approximate computing for energy harvesting systems Branch prediction and value prediction in processors Cache architectures and networks-on-chip for many-core processors Intermittent computing resilience His recent work emphasizes value-level parallelism (Carat/uSystolic), RTL simulation acceleration (TaroRTL), and personalized neural network inference (CAP’NN). His research has been recognized with the NSF CAREER Award (2021) and multiple IEEE Micro Top Picks. Grants & Advising: Active in supervising advanced independent studies and master’s/dissertation research. Extensive grant funding includes the NSF CAREER Award and the Grainger Faculty Scholarship. Labs & Teams: Leads research groups focused on approximate computing and energy-efficient architectures within the Electrical & Computer Engineering department.
Ioannis Sourdis is a Full Professor at the Department of Computer Engineering, Chalmers University of Technology, Sweden. His research focuses on computer architecture, reconfigurable computing, network-on-chip (NoC) design, memory systems, and fault-tolerant embedded systems, with applications in biomedical informatics and hardware security. Current projects include EUMMSS (Efficient Uncore Mechanisms for Multicore Space Systems, funded by the Swedish National Space Board) and eProcessor (European Processor Ecosystem, funded by the European Commission). Past initiatives include the DeSyRe project (on-demand system reliability), ECOSCALE (exascale reconfigurable computing), and SHARCS (secure hardware-software architectures). His work spans NoC router design (e.g., FastTrackNoC, DDRNoC), memory compression (MemSZ, L2C), and biomedical security applications (heartbeat-based protocols). He has published extensively in venues like DATE, ICS, PACT, and IEEE Transactions on Networking. Key research areas: Chiplet-based systems , hybrid memory architectures , FPGA acceleration , and real-time stream aggregation .
Brian Towles is an Adjunct Assistant Professor in the Department of Electrical and Computer Engineering at Duke University. He earned his D.Phil. from Stanford University in 2005 and has contributed extensively to computer architecture and machine learning systems through research and publications. His work focuses on specialized hardware for molecular dynamics simulations and network-on-chip design. Research Interests: Dr. Towles specializes in computer architecture, particularly in network-on-chip design, event-driven computation, and low-latency interconnects for scientific computing. His research enables high-performance simulations in molecular dynamics and machine learning, with notable collaborations on Anton/TPU series supercomputers. Publication Trends: His publications span from 2001 to 2024, emphasizing Custom ASICs for scientific computing (Anton 2/3, TPUv4) Optimized interconnects and routing algorithms Event-driven and cycle-accurate simulation frameworks Resilient systems for large-scale machine learning
Sergi Abadal Cavalle is a distinguished Professor in the Department of Computer Architecture at the Universitat Politècnica de Catalunya (UPC), affiliated with the Escola Tècnica Superior d'Enginyeria de Telecomunicació de Barcelona (ETSETB). He leads a dynamic research group focused on revolutionary computing architectures through wireless chip-scale networks and quantum interconnects. His work is supported by prestigious grants including an ERC Starting Grant and an ERC Proof of Concept Grant. Education: PhD in Computer Architecture, Universitat Politècnica de Catalunya (2016) MSc in Telecommunication Engineering, UPC (2011) BSc in Telecommunication Engineering, UPC (2010) Sergi's research focuses on overcoming the limitations of traditional wired interconnects in computing systems by pioneering wireless communication at the chip and package level. His work spans terahertz communications, graphene-based antennas, reconfigurable metasurfaces, and quantum-coherent networks. He has led major EU projects such as WINC, EWiC, QUADRATURE, and WiPLASH, aiming to revolutionize classical and quantum computing architectures. His research integrates electromagnetics, materials science, and computer architecture to enable ultra-fast, scalable, and energy-efficient systems. His recent publications demonstrate a strong trend toward integrating wireless technologies within computing systems, particularly using novel materials like graphene and software-defined metasurfaces. The articles highlight advancements in on-chip wireless communication, channel modeling, and the application of these technologies in 6G and quantum computing. His work bridges theoretical modeling with experimental validation and practical emulation. Scientific Awards: ERC Starting Grant (2022) ERC Proof of Concept Grant (2024) ACM NanoCom Outstanding Milestone Award (2022) NanoComNet Young Investigator Award (2019) UPC Outstanding Thesis Award (2016) IN-NOVA Award to Best Master Thesis (2021) IBM Award to Best Academic Record (2021) Medal from Real Academia de la Ingeniería (2024) IEEE Senior Member (2025) Sergi actively mentors a large group of PhD and Master's students, many of whom have received awards for their thesis work. He leads the N3Cat research group and collaborates with institutions such as IBM Research, NEC Labs Europe, RWTH Aachen, EPFL, University of Nottingham, and Intel Labs. His lab is at the forefront of experimental validation of wireless interconnects and quantum architectures, with ongoing projects focusing on emulation and commercialization of chiplet communication technologies.
Kanad Basu is an Associate Professor in the Department of Electrical, Computer, and Systems Engineering at The University of Texas at Dallas, Jonsson School of Engineering and Computer Science. He leads the Trustworthy and Intelligent Embedded Systems (TIES) lab, focusing on hardware security, reliability, and emerging computing paradigms. His research spans AI hardware, quantum computing, functional safety, and hardware-based security validation. Research Interests: His work emphasizes improving the trustworthiness of modern hardware systems. Key areas include hardware security (e.g., side-channel analysis, hardware trojans), functional safety in AI accelerators, quantum computing security and verification, and post-silicon validation techniques. He combines formal methods, machine learning, and hardware design to address vulnerabilities in SoCs, DNN accelerators, and quantum systems. Publication Trends: Recent publications (2023–2025) show a strong focus on interdisciplinary research, integrating AI/ML with hardware security, quantum computing, and functional safety. There is a growing emphasis on using large language models for assertion generation, symbolic execution for hardware fuzzing, and graph neural networks for quantum circuit analysis. His work frequently appears in top venues like DAC, DATE, HOST, ISVLSI, and IEEE journals. Scientific Awards: NSF CAREER Award, 2025 IEEE Top Picks in Test and Reliability, 2024 and 2023 Multiple Hack@DAC Prizes (2nd and 3rd) Best Paper Award at VLSI Design 2011 Assistant Professor Award at UTD Jonsson School, 2024 Nominated for Blavatnik Awards for Young Scientists, 2019 Advising and Grants: Dr. Basu has mentored numerous PhD, MS, and undergraduate students, many of whom have published in top-tier venues. He leads the TIES lab, which has received significant recognition, including the NSF CAREER Award. He actively collaborates across disciplines, advising students on topics ranging from quantum computing to AI hardware and functional safety. His lab produces high-impact research with real-world applications in automotive, cloud, and embedded systems. Labs and Teams: He leads the Trustworthy and Intelligent Embedded Systems (TIES) lab at UT Dallas, which fosters innovation in hardware security and reliability. The lab has produced award-winning work, including second prize at HACK@DAC 2025. He also serves on technical committees for IEEE DATE and HOST, and acts as Hardware Hacking Chair for IEEE HOST, indicating strong leadership in the hardware security community.
Sandra M. Đosić is an Associate Professor at the Faculty of Electronics in Niš, University of Niš, Serbia, specializing in Electronics and Embedded Systems. She has been actively contributing to research in real-time systems, fault tolerance, wireless sensor networks, and indoor localization technologies. Research Interests: Her work spans fault-tolerant real-time systems, energy-efficient computing, UWB-based indoor localization, and communication protocols for wireless sensor networks. She explores techniques such as dynamic voltage and frequency scaling (DVFS), tone-based contention resolution, and deflection routing in networks-on-chip to enhance system reliability and efficiency. Publication Trends: Her recent publications (2009–2022) demonstrate a strong focus on improving robustness and performance in embedded and distributed systems. The research integrates signal processing, network optimization, and energy-aware design, primarily applied in industrial and indoor environments. Scientific Awards: No awards are mentioned in the provided text. Advising and Grants: While no specific students are listed, she is currently participating in two national research projects, indicating active involvement in funded research. Her collaborations with researchers such as Igor Stojanovic and Milica Jovanovic suggest a strong team-based research approach. Labs and Research Teams: Although no formal lab or team name is specified, her repeated co-authorship with colleagues from the Faculty of Electronics implies active participation in a research group focused on electronics, communications, and real-time systems.
Swiss Federal Institute of Technology in LausanneSwitzerland
Pejman Lotfi-Kamran is an Associate Professor at the School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, where he also serves as the head of the school and director of Turin Cloud Services. His research focuses on computer architecture, systems, approximate computing, and cloud computing, with an emphasis on performance and energy efficiency for big-data applications. His educational background includes: Ph.D. in Computer Science, EPFL (2013) M.Sc. in Electrical and Computer Engineering, University of Tehran (2005) B.Sc. in Electrical and Computer Engineering, University of Tehran (2002) Lotfi-Kamran's research spans computer architecture innovations, including data and instruction prefetching, networks-on-chip, coherence protocols, and many-core processor design. He has pioneered work on scale-out processors, neural acceleration for GPUs, and approximate computing frameworks. His publications appear in top venues such as ISCA, HPCA, MICRO, and IEEE/ACM journals. His recent articles reflect a strong trend in improving system performance through intelligent prefetching, efficient NoC designs, and energy-aware architectures. Key themes include reducing frontend bottlenecks, optimizing cache behavior, and enhancing data delivery in large-scale systems. His work often combines cross-stack insights with hardware-software co-design for real-world impact. Scientific awards and recognitions include: 2017 CADS Best Paper Award 2016 Young Faculty Award from Iran's National Elites Foundation 2012-2013 Intel Ph.D. Fellowship 2012 and 2011 HiPEAC Paper Awards 2011 HPCA Best Student Paper Finalist Multiple academic honors from University of Tehran He has advised several graduate students including Paria Darbani, Ali Ansari, Mohammad Bakhshalipour, and Farid Samandi, many of whom have co-authored significant papers. His teaching spans institutions like Sharif University of Technology, Iran University of Science and Technology, and EPFL, covering advanced computer architecture and multiprocessor systems. He has led research projects such as AxBench and CloudSuite on Simics, and contributed to national initiatives like Iran’s National Grid. He is actively involved in tool development and continues to shape research in next-generation computing systems. He leads the Turin Cloud Services initiative at IPM and is deeply engaged in both theoretical and applied aspects of computer systems research, with ongoing work in neural acceleration, approximate computing, and scalable architectures.
Prof. Dr. Andreas Herkersdorf is a Full Professor and Chair of Integrated Systems at the Technical University of Munich (TUM) School of Computation, Information and Technology. His research focuses on application-specific multicore processors (MPSoC), FPGA-based prototyping, fault-tolerant systems, and energy-efficient architectures, with applications in IP packet processing, automotive systems, and visual computing. He has received multiple IBM innovation awards and serves on editorial boards including the DFG Review Board for computer architecture. Education: Dipl.-Ing. Electrical Engineering (TUM, 1987), Dr. techn. Electrical Engineering (ETH Zurich, 1991) Research: MPSoC architectures, autonomic computing, NoC resilience, FPGA acceleration, and self-optimizing systems. Awards: IBM Master Inventor (1998), IBM Outstanding Technical Achievement Award (2001), multiple IBM Innovation Achievement Awards (1996-2003) His recent publications emphasize hardware/software co-design, machine learning integration for runtime optimization, and network-on-chip innovations. He collaborates on projects involving 6G systems, smartNICs, and automotive communication protocols.
Zebo Peng is a Professor and Deputy Head of Department at Linköping University's Department of Computer and Information Science (IDA), leading the Software and Systems (SAS) division. His research focuses on embedded systems design, electronic design automation, SoC testing, and real-time systems with emphasis on fault tolerance and hardware/software co-design. He has contributed to projects like the ASTECC initiative, funded by the Swedish Foundation for Strategic Research, addressing adaptive software in edge-cloud continuum systems. Key research interests include cyber-physical systems security, time-sensitive networking (TSN), and optimization techniques using genetic algorithms. Recent work explores thermal-aware design for reliability, security-aware scheduling, and stability guarantees in control systems. His publications span journals like IEEE TPDS and ACM TECS, alongside conference contributions on topics like resource management and fault detection in distributed systems. Prof. Peng collaborates extensively within the SAS division, which bridges academic and industrial research in software engineering and computer systems. His team's projects address challenges in real-time systems, embedded security, and parallel computing architectures.
