Find Academic Supervisors

Benjamin Carrison-SchaferView profile

Associate Professor

• Reconfigurable Computing
• FPGAs
• Electronic Design Automation
• +7 more

Benjamin Carrison-Schafer is an Associate Professor and Assistant Dean for Graduate Student Success at the Department of Electrical and Computer Engineering, Erik Jonsson School of Engineering and Computer Science, University of Texas at Dallas. He leads the Design Automation and Reconfigurable Computing Laboratory (DARClab), focusing on systems, high-level design, and programming methodologies for VLSI computing systems and FPGAs. Education: MBA from McGill University, Canada (2012) PhD in Electrical and Electronic Engineering from University of Birmingham, UK (2003) Research Interests: His work spans modeling, analysis, synthesis, optimization, and implementation of VLSI systems. Current projects include: Approximate Computing, High-Level Synthesis Design Space Exploration, Hardware Security, Behavioral MPSoC Optimization, and Automatic Fault-Tolerant System Generation. His research blends theory and practice, using analytical and experimental techniques to solve real-world problems. Publication Trends: Recent publications demonstrate strong focus on hardware security, FPGA optimization, and automated design methodologies. Key themes include High-Level Synthesis innovations, hardware acceleration techniques, and cross-disciplinary applications of reconfigurable computing. His work frequently addresses challenges in hardware trustworthiness, energy efficiency, and design automation scalability. Professional Activities: Associate Editor: IEEE Transactions on Sustainable Computing (2022-present) Conference Chair: ICCD 2024, DCAS 2024 Program Committee: ASP-DAC, DATE, FCCM, GLSVLSI Advising & Labs: Supervises multiple PhD and Master's students at DARClab. Current research includes domain-specific architecture design, hardware security, sustainable computing, and ML for VLSI design. The lab collaborates with industry partners like Renesas Electronics and develops commercial tools through spin-off company highX Technologies.

Alessandro OttavianoView profile

Researcher

• Computer Architecture
• Embedded Systems
• Real-Time Systems
• +3 more

Dr. Alessandro Ottaviano is a Researcher affiliated with the Department of Digital Integrated Circuits and Systems at ETH Zürich. His work focuses on advanced computer architecture and embedded systems, particularly in the domains of RISC-V processors, real-time systems, and heterogeneous computing. He contributes to the design of time-predictable virtual memory solutions, mixed-criticality systems, and energy-efficient hardware-software interfaces. Key research areas include modular processor architectures, hardware monitoring for safety-critical applications, and power management in high-performance computing (HPC) systems. His recent projects involve developing controllers for 2.5D systems-in-package and creating open-source networking solutions for mixed-criticality environments. Ottaviano’s work often emphasizes open-source hardware design and scalable system-level approaches to address challenges in autonomous systems and edge computing. He collaborates on advancements in interrupt handling for virtualized systems, peripheral event linking for IoT devices, and FPGA-based thermal emulation for many-core processors. His research bridges theoretical computer architecture principles with practical implementations in embedded and real-time systems.

Thomas WildView profile

Professor

• Manycore system on chip (SoC) architectures
• Network processor (NPU) architectures
• On-chip communication architectures
• +3 more

Dr.-Ing. Thomas Wild serves as an Academic Director at the Technical University of Munich (TUM), working within the TUM School of Computation, Information and Technology at the Chair of Integrated Systems. He maintains an active research and teaching role at the institution, with his office located in Building N1 (Theresienstr. 90), Room N2136 in Munich, Germany. Dr. Wild's research focuses on advanced computing architectures, with particular emphasis on manycore system on chip (SoC) architectures, network processor (NPU) architectures, on-chip communication architectures including networks on chip (NoC), and system level design methodologies. His work bridges theoretical research with practical implementation, often exploring design space exploration techniques to optimize system performance. The evolution of his research over two decades demonstrates a consistent focus on improving communication architectures and system-level design for embedded and high-performance computing platforms. His recent publications (2023-2025) reveal a growing integration of machine learning techniques with traditional hardware design, particularly in optimizing power-performance tradeoffs in embedded systems. There's a clear trend toward hardware-software co-design approaches, with significant work on SmartNICs, Linux system optimization, and network processing acceleration. His research shows strong interdisciplinary connections between computer architecture, networking, and machine learning. EUROPRACTICE representative for TUM city campus, facilitating access to commercial EDA tools for academic purposes Active collaborator with Professor Andreas Herkersdorf and other researchers at TUM Focus on practical implementations with FPGA-based prototyping and real system modifications Dr. Wild teaches several hardware design courses including VHDL Lab, SystemC Lab, and HW/SW Codesign, contributing to the education of next-generation computer engineers. His teaching directly complements his research in system design and hardware acceleration, providing students with hands-on experience in cutting-edge technologies.

Jiafeng XieView profile

Assistant Professor

• Post-Quantum Cryptography
• Cryptographic Engineering
• Hardware Security
• +5 more

Jiafeng (Harvest) Xie is an Assistant Professor in the Department of Electrical and Computer Engineering at Villanova University, where he directs the Security and Cryptography (SAC) Lab. He holds a Ph.D. in Electrical Engineering from the University of Pittsburgh and has prior faculty experience at Wright State University. His research focuses on cryptographic engineering, post-quantum cryptography, hardware security, and digital design for telemetry systems. Education includes a Ph.D. from University of Pittsburgh (2013-2014), M.E. from Central South University (2007-2010), and B.E. from Yanshan University (2002-2006). He has received prestigious awards like the 2024 IEEE Philadelphia Engineer of the Year Award and the 2023 Art Ryan Award. His work spans over 66 peer-reviewed publications, with a focus on hardware acceleration for post-quantum cryptographic systems. Research interests include post-quantum cryptographic engineering, fully homomorphic encryption, fault detection methodologies, and digitalization of aeronautical telemetry systems. His grants include NSF SaTC and NIST-funded projects. Teaching includes courses like Embedded Systems and Post-Quantum Computing . Current advisees include Ph.D. students Pengzhou He, Tianyou Bao, and Yazheng Tu, along with several M.S. and undergraduate researchers. The SAC Lab collaborates with AFRL and explores novel cryptographic hardware designs, with recent breakthroughs in compact accelerators for lattice-based cryptography and approximate homomorphic encryption. His work emphasizes algorithm-architecture co-design for security and efficiency in emerging computing systems.

Kyriakos DeliparaschosView profile

Researcher

• Autonomous Vehicles
• Control Systems Design
• High Performance Computing
• +6 more

Kyriakos Deliparaschos is affiliated with the Cyprus University of Technology as a Researcher. His work focuses on cutting-edge technologies in autonomous systems, control systems design, and FPGA-based implementations. He collaborates actively with institutions like the Institute of Communications and has co-authored papers with experts such as Argyrios Zolotas and Themistoklis Charalambous. His research interests span autonomous robotics, medical robotics, and high-performance computing, with a strong emphasis on real-time systems and embedded hardware-software co-design. Notable contributions include advancements in Delaunay triangulation algorithms for multi-core architectures and fault-tolerant AI systems for autonomous vehicles. Deliparaschos has published widely in journals like IEEE Access and Electronics, focusing on topics such as computational resource management in cloud environments and FPGA-driven control system paradigms. His work bridges theoretical research with practical applications in both academia and industry.

Zahra EbrahimiView profile

Researcher

• Approximate Computing
• Reconfigurable Accelerator Design
• Embedded Systems
• +2 more

Zahra Ebrahimi is a researcher in the field of approximate computing, reconfigurable accelerator design, and embedded systems. She joined the Chair of Embedded Systems at Ruhr University Bochum in April 2024, following her PhD research associate role at the Center for Advancing Electronics Dresden (Cfaed) from 2018 to 2024. Her work focuses on energy-efficient hardware/software co-design for edge-to-cloud computing, with applications in neural networks and bio-signal processing. She leads the BMBF-funded project X-DNet , collaborating with Huawei Research Center Munich. Education : B.Sc. and M.Sc. in Electrical Engineering from Sharif University of Technology, Iran Key Projects : ReAp (DFG), Re-Learning (ESF), X-ReAp (DFG), X-DNet (BMBF) Research Interests : Approximate computing, reconfigurable accelerators, embedded systems, SW/HW co-design, energy-efficient edge/cloud computing. Recent Trends : Zahra’s research emphasizes applying approximation techniques to neural networks for 5G/6G applications and designing specialized hardware like CGRAs for bio-signal processing and distributed computing. Collaborations : Academic-industry partnership with Huawei Research Center Munich.

• Embedded Systems
• Hardware/Software Co-design
• Energy-efficient AI Accelerators
• +7 more

Oliver Bringmann is a full Professor and head of the Chair of Embedded Systems at the University of Tübingen, Germany, and a member of the board of directors at the FZI Research Center for Information Technology. His research integrates embedded-system design, energy-efficient AI accelerators, dependable automotive perception, and medical AI for capsule endoscopy. Education & Career Ph.D. in Computer Science, University of Tübingen, 2001 Diploma in Computer Science, University of Karlsruhe (KIT) Head, Chair of Embedded Systems, University of Tübingen (since 2012) Deputy spokesperson & spokesperson, Dept. of Computer Science, University of Tübingen (2014-2022) Board of Directors, FZI Research Center for Information Technology Research Interests Bringmann’s group pioneers hardware/software co-design for ultra-low-power Edge-AI , developing RISC-V based accelerators, compiler-aware neural-architecture search, and real-time perception systems for autonomous driving and medical devices. Key topics include: Energy-efficient AI architectures (“Edge AI”) and custom accelerator generation Robust collective perception under adverse weather (LiDAR, camera, V2X fusion) Timing/power-predictable embedded software and system-on-chip design automation Hardware-assisted security and safety for automotive & IoT systems AI-driven capsule endoscopy localization and anomaly detection Recent Publication Trends His 2024-2025 articles reveal a strong shift toward robust multimodal perception for automated driving (snow, fog, collective LiDAR fusion) and Edge-AI medical devices (capsule endoscopy with multi-task CNNs). Core contributions span dataset generation (SCOPE, SnowyLane), safety metrics (LSM), and fast performance modeling for DNN accelerators. Professional Service & Projects Executive/Steering Committees: IEEE/ACM DATE, CODES+ISSS, CASES, ITSS conferences EU CATRENE EDA roadmap chapter lead (Embedded Software & ESL-to-RTL) Principal investigator in Scale4Edge, OCEAN12, enerDAG and other national projects on energy-efficient sensorics and secure energy trading. His group maintains extensive collaborations with automotive and semiconductor industry, focusing on dependable, energy-aware embedded intelligence.

Imen BahriView profile

Researcher

• Control Systems
• Electrical Engineering
• Power Electronics
• +3 more

Imen Bahri is a researcher at the Laboratory of Electrical and Electronic Engineering of Paris (GeePs) , specializing in control systems for electromagnetic and power electronic devices. Her work focuses on vibration reduction, efficiency optimization, and sensorless control strategies for electric machines like switched reluctance machines (SRMs) and permanent magnet synchronous machines (PMSMs). Research Interests include: Robust control methods (H-infinity, RST controllers) Intermittent control for automotive applications Sensorless performance enhancement DC microgrid voltage regulation Recent publications address vibration suppression via HW/SW partitioning, torque pulsation in electric vehicles, and FPGA-based fault-tolerant systems. She collaborates with institutions like Université de Lorraine and IEEE on modeling, simulation, and industrial electronics.

Zahra Ebrahimi MamaghaniView profile

Researcher

• Approximate Computing
• Reconfigurable Accelerator Design
• In-Network Computing for 5G/6G
• +3 more

Zahra Ebrahimi Mamaghani is an academic researcher affiliated with the Embedded Systems team at the Faculty of Electrical Engineering and Information Technology, Ruhr University Bochum. Her work focuses on approximate computing, reconfigurable accelerators, and energy-efficient embedded systems. She completed her B.Sc. and M.Sc. at Sharif University of Technology (Iran) and is a PhD student at TU Dresden. She managed the X-DNet (BMBF-funded, collaborating with Huawei) and GREEN-DNN (acatech/BMDV-funded) projects, emphasizing distributed and in-network computing for 5G/6G applications. Education: B.Sc. and M.Sc. in Electrical Engineering, Sharif University of Technology, Iran PhD Candidate at TU Dresden (Cfaed Institute, 2018–2024) Research Projects: ReAp (DFG, 2018–2021) Relearning (ESF, 2021–2023) X-ReAp (DFG, 2023–2025) X-DNet (BMBF, with Huawei) GREEN-DNN (acatech/BMDV) Research Interests: Approximate computing, energy-efficient edge-to-cloud systems, SW/HW co-design, and reconfigurable architectures for 5G/6G. Her recent publications emphasize cross-layer approximation techniques, energy-efficient CGRAs, and distributed computing frameworks for multi-kernel applications. She advises students on topics like approximation of ML models for high-throughput systems, requiring expertise in FPGA programming (Verilog/VHDL), Python, and ML frameworks like TensorFlow/PyTorch. Her lab focuses on embedded systems and collaborates with industry partners like Huawei. She holds a notable position in managing interdisciplinary projects bridging academia and industry, particularly in sustainable computing for next-generation networks.

• Hardware Acceleration
• High-Level Synthesis
• Asynchronous Circuit Design
• +2 more

Sebastian Michael Wiedemann is a PreDoc Researcher at the Vienna University of Technology, affiliated with the Embedded Computing Systems group. His research focuses on hardware acceleration, asynchronous circuit design, and software-hardware integration techniques. He holds a Diplom-Ingenieur (Dipl.-Ing.) degree and a BSc in Electrical Engineering. His recent work includes publications at the Austrochip Workshop on Microelectronics and a diploma thesis on high-level synthesis tools for asynchronous circuits. His research interests span hardware modeling, GPU computing, and FPGA optimization. Publications highlight advancements in vendor-agnostic preemption mechanisms and asynchronous circuit synthesis methodologies. As a PreDoc Researcher, he contributes to academic projects and teaches courses such as Hardware Modeling and HW/SW Codesign .

• Real-Time Systems
• Embedded Systems
• Worst-Case Execution Time (WCET) Analysis
• +5 more

Overview Peter Puschner is a full Professor at the Faculty of Informatics at TU Wien, specializing in Computer Engineering and Real-Time Systems. He serves as Faculty Representative for Research and Infrastructure, overseeing strategic initiatives in informatics research and infrastructure development. His academic role also includes leading the Service Unit Infrastructure (E199-02) and heading the Cyber-Physical Systems department (E191-01). Education and Roles Puschner holds a Diplom-Ingenieur (Dipl.-Ing.) and a Dr.techn. from TU Wien, alongside the title Ao.Univ.Prof. His roles include teaching and supervising students in advanced topics such as Operating Systems, Real-Time Systems, and Scientific Research methodologies. He has been actively involved in curriculum design for Computer Science and Business Informatics programs. Research Interests His research focuses on: Timing Analysis: WCET analysis for real-time systems, especially in multi-core and mixed-criticality environments. Embedded Systems: Designing time-predictable architectures for safety-critical applications. Communication Networks: Time-triggered protocols for automotive and industrial systems. Publications and Tools Puschner has authored over 160 publications, including seminal work on the Platin WCET analysis tool and the T-CREST multi-core architecture. His recent work emphasizes compiler-driven timing predictability and dual-path code paradigms. Grants and Awards Recipient of the Marie-Curie Fellowship (2003) and a founding member of the IFIP 10.2 WG on Embedded Systems. His projects have been funded by the EU (e.g., T-CREST, Multicores Partitioning), FWF, and industry collaborations. Students and Supervision He has supervised numerous PhD and Master’s students, including Elias Maroun (2024), Matthias Platzer (2022), and Bledar Cilku (2018). Key topics include WCET analysis, memory hierarchy design, and secure communication protocols. Labs and Teams Puschner leads the Real-Time Systems Lab, collaborating with industry partners (e.g., automotive, aerospace) to develop safety-critical embedded systems. His team contributes to open-source tools like Platin and the Patmos processor.

Tirado FranciscoView profile

Professor

• Power Aware Computing
• Heterogeneous Computing
• Applications optimization
• +4 more

Francisco Tirado is a Full Professor of Computer Architecture at Complutense University of Madrid since 1986. He has held leadership roles including Vice-Chancellor for Research (2012-2015), Dean of the Faculty of Physics (1994-2002), and Director of the Complutense Supercomputing Center (2002-2007). He is a founding member of the Spanish Society for Computer Science (SCIE) and Spanish Society for Computer Architecture (SARTECO). His research focuses on power-aware computing, heterogeneous systems, bioinformatics, and hardware design automation. He has authored over 242 publications and supervised 15 PhD theses. His professional service includes chairing 138 international conferences and serving on numerous committees for EUROMICRO, IEEE, and national research agencies. Education: No explicit details provided, but has been active at Complutense University since 1978. Affiliations: Member of COSCE Executive Board (2012), IEEE Senior Member (2005), and EUROMICRO Board (1991-2004). Research Interests: - Optimizing energy efficiency in high-performance computing systems - Design of heterogeneous architectures and accelerators - Bioinformatics applications through hardware/software co-design - Parallel programming models for emerging architectures - Automation tools for FPGA and embedded systems development Conference Contributions: Played multiple roles (General Chair, Program Chair) for major events like ParCo, HPCA, and EUROMICRO PDP conferences. Delivered 64 keynote/plenary lectures globally. Scientific Awards: Doctor 'Honoris Causa' from universities in Spain, Paraguay, and Peru 2013 National Computer Science Award IEEE Senior Membership Advising: Supervised 15 PhD students. Active in technology transfer contracts with industry. Labs/Teams: Founder and leader of the ArTeCS research group at Complutense University, specializing in computer architecture and high-performance computing innovations.

• Highly Parallel Architectures
• Power Electronics
• Control Systems
• +5 more

Francesco Gregoretti was a former faculty member at the Polytechnic of Turin , affiliated with the Department of Electronics and Telecommunications (DET) . He contributed to teaching and academic leadership, including roles as Course Owner for Applied Electronics in recent academic years (2019/20, 2020/21) and as a collaborator in Computer Engineering courses. His doctoral program involvement spanned Electronics and Communications Engineering cycles from 2003/2004 (19th cycle) to 2012/2013 (28th cycle) . Research interests focused on highly parallel architectures , DC-DC switch-mode power conversion , and heterogeneous computing platforms . He led research groups like CodeSimulink (automatic synthesis of analog circuits) and projects addressing high-performance software acceleration. Key projects include: ASPIDA (2002–2005) – Asynchronous open-source processor development Sviluppo di un ambiente di coprogettazione hardware/software basato su Simulink (2001–2003) – EU-funded Design of HW and SW Platforms for Sensor Networks (2007–2008) – Commercially funded Publications emphasize power electronics and parallel computing, with recent works (2021, 2020) on real-time monitoring and digital control frameworks. Earlier contributions (1993–1994) explored SIMD array processors for high-performance computing. No scientific awards are listed. However, he co-invented a patent ( Magnetic application in cancer research and therapeutic aid ) with Romano Borchiellini, Maurizio Bressan, Umberto Lucia, Bartolomeo Montrucchio, and Emilio Paolucci, reflecting interdisciplinary engagement. His academic narrative includes decades of project management and teaching, with a focus on merging theoretical research (parallel architectures) with applied engineering (power systems and sensor networks). The listed doctoral cycles and teaching roles highlight sustained contributions to academic training in electronics and telecommunications.

Dirk PflügerView profile

Professor

• Scientific Computing
• High-Performance Computing (HPC)
• Parallel and Distributed Systems
• +3 more

Dirk Pflüger is a Professor at the University of Stuttgart's Institute of Parallel and Distributed Systems, within the Faculty of Computer Science, Electrical Engineering and Information Technology. His research focuses on high-performance computing (HPC), parallel and distributed systems, and sparse grids. He has led projects in astrophysical simulations, machine learning applications, and uncertainty quantification. Notable contributions include developing scalable algorithms for exascale computing using HPX, Kokkos, and SYCL frameworks. His expertise spans distributed computing architectures, task-based parallel programming, and interdisciplinary applications in astrophysics and medical AI. Recent work includes optimizing hyperparameter tuning, simulating stellar mergers, and enhancing blood glucose prediction models using deep reinforcement learning. Pflüger's research emphasizes performance portability, fault tolerance, and cross-platform collaboration. He has contributed to open-source tools like PLSSVM and hws, which address hardware monitoring and GPU acceleration challenges. His work bridges theoretical advancements with practical implementations for real-world computational problems.

Simon RokickiView profile

Assistant Professor

• Computer Architecture
• Hardware/Software Co-design
• Embedded Systems
• +6 more

Simon Rokicki is an Assistant Professor affiliated with IRISA (Rennes, France), where he works on Computer Aided Design, Compilation, and Micro-architecture within the Taran research group. His research bridges hardware and software for adaptive embedded systems. Education PhD in Computer Science from Université de Rennes 1 (supervised by Steven Derrien and Erven Rohou) Master in Computer Science from Université de Rennes 1 via ENS Rennes (2015) His research focuses on dynamic binary translation (Hybrid-DBT), hardware/software co-designed machines, and speculative execution. He explores adaptive architectures for energy efficiency and security, including ISA randomization to obfuscate code and mitigate attacks (e.g., Spectre via GhostBusters). His work leverages FPGAs and VLIW processors through High-Level Synthesis (HLS) tools. Recent publications emphasize speculative loop pipelining, memory speculation, runtime reconfigurable cores, and attack detection in real-time systems. Collaborations span Inria, Université de Rennes 1, Southeast University Nanjing, and Ruhr-Universität. Teaching includes courses on FPGA prototyping, VLIW architectures, and High-Level Synthesis (e.g., Xilinx SDSoC and Vivado HLS) at ENS Rennes, Université de Rennes 1, and Southeast University Nanjing. He also contributed to labs on dynamic binary translation and hardware/software co-design.