Find Academic Supervisors

Sandro BartoliniView profile

Associate Professor

• High-Performance Computing (HPC)
• Computer Architecture
• Embedded Systems
• +5 more

Sandro Bartolini serves as Associate Professor in the Department of Information Engineering and Mathematical Sciences at the University of Siena, Italy, where he teaches advanced courses in computer architecture and parallel programming while leading cutting-edge research in high-performance computing systems. His academic journey began with a cum laude Laurea in Computer Engineering followed by a PhD in Computer Science and Engineering from Università di Pisa. Education: PhD in Computer Science and Engineering, Università di Pisa Laurea in Computer Engineering (cum laude), Università di Pisa Research Focus: His work centers on photonic interconnects for chip multiprocessors , energy-efficient software optimization for multi-core/GPU architectures, and performance-portable parallel programming models . Current investigations span cryptographic acceleration, blockchain algorithms, and hardware/software co-design for emerging computing paradigms, with strong emphasis on practical implementations bridging theoretical advances and real-world applications. Publication Trends: Recent publications (2019-2023) reveal three dominant threads: (1) Photonic network innovations addressing energy bottlenecks in chip multiprocessors, (2) The PHAST library ecosystem enabling seamless CPU/GPU programming across domains from autonomous vehicles to UAV navigation, and (3) Hardware accelerator designs for convolutional networks and cryptographic workloads. These works consistently target performance-portability challenges in heterogeneous computing environments. Grants and Collaborations: As principal investigator for the Italian Ministry-funded PHOTONICA project, he established international research partnerships with Murcia University, Columbia University, and Hong Kong University of Science and Technology, while securing industry collaborations with STMicroelectronics, Intel Munich, IBM, and IMEC. He has also managed complex IT system deployments for Siemens Italy, RAI (Italian public broadcasting), and SpaceDys. Academic Leadership: Bartolini serves as Associate Editor for the Eurasip Journal of Embedded Computing and actively contributes to the European HiPEAC network. His research group at Siena maintains strong industry ties for technology transfer, particularly in photonic interconnect validation and parallel programming frameworks for next-generation computing systems.

• Computer Architecture
• Embedded Systems
• High-Performance Computing
• +9 more

Zapater Sancho Marina is an Associate Professor at the ReDS Institute (Institute of Reconfigurable and Embedded Digital Systems) within the School of Engineering and Management Vaud (HEIG-VD), part of the University of Applied Sciences and Arts Western Switzerland (HES-SO). She holds dual master's degrees in Electronic and Telecommunication Engineering from Universitat Politècnica de Catalunya (2010) and a PhD in Computer Science from Universidad Politécnica de Madrid (2015). Her career includes postdoctoral work at EPFL (2016-2020) and assistant professorship at Universidad Complutense de Madrid (2015-2016). Education BSc & MSc in Electronic Engineering (UPC 2010) PhD in Computer Science (UPM 2015) Research Focus spans cross-layer optimization of heterogeneous architectures for performance and energy efficiency, with emphasis on: Embedded systems (IoT/edge computing) High-performance compute architectures Analog in-memory computing for AI Thermal/power management in 3D chips Cloud-edge AI workload orchestration Publication Trends show expertise in RISC-V simulation frameworks, analog computing tiles for CNNs, virtual memory redesign, and AI-driven cloud performance prediction. Her recent work explores thermal-aware 3D chip management, hybrid-cache reliability optimization, and open-source teaching platforms for radio theory. Awards include a Spanish government PhD fellowship. She has led 4 European H2020 projects since 2016 and currently serves as PI for 4 industrial collaborations (Facebook/Intel/Huawei), Innosuisse projects, and HES-SO initiatives. Labs & Teams include the ReDS Institute, EPFL's Embedded Systems Laboratory, and collaborations with Yale/Edinburgh. She co-developed the ALPINE simulation framework and SO3 operating system modifications for Midgard project validation.

Antonia ZhaiView profile

Associate Professor

• Compiler Optimizations
• Computer Architecture
• Parallel Processing
• +4 more

Antonia Zhai is an Associate Professor in the Department of Computer Science and Engineering at the University of Minnesota. She holds a Ph.D. in Computer Science from Carnegie Mellon University (2005), an M.A.Sc. in Computer Engineering from the University of Toronto (1998), and a B.A.Sc. in Computer Engineering from the University of Toronto (1996). Her office is located at 6-205 Kenneth H. Keller Hall, Minneapolis, MN. Her research focuses on developing novel compiler optimizations and computer architecture features to enhance both performance and non-performance aspects of computing systems. Key interests include: Thread-level speculation for parallel processing Multicore architecture optimization Hardware/compiler co-design for security and reliability Dynamic performance tuning in heterogeneous systems High-speed network packet processing architectures Her publications demonstrate sustained focus on parallel computing, compiler optimizations, and hardware security, with recent work expanding into network function virtualization and cache-side channel attack detection. She leads the High-Performance Computing and Compilers (HPCC) group and organizes the weekly HPCC seminar series focused on architectures and compilers. She has advised 12+ graduate students including 8 PhD graduates now at companies like AMD, NVIDIA, and Oracle. Significant research grants include: NFLambda: NFV Framework (NSF 2021-2025) Dynamic Binary Translation (NSF 2015-2019) In Vivo Software Monitoring (NSF 2009-2014) Embedded Fault Detection (NSF 2009-2014)

Alexandre JoannouView profile

Researcher

• Computer Architecture
• Hardware Security
• Memory Safety
• +4 more

Dr. Alexandre Joannou is a Senior Research Software Engineer at the Department of Computer Science and Technology, University of Cambridge. His research focuses on secure hardware-software co-design, particularly in the CHERI (Capability Hardware Enhanced RISC Instructions) project. He specializes in computer architecture, memory safety, and RISC-V processors, with a focus on integrating security into low-level system components. His work spans theoretical contributions to capability-based systems and practical implementations in accelerators, GPUs, and embedded devices. Key areas include secure speculation, memory protection, and formal verification of hardware designs. Joannou's research has advanced temporal safety in heaps, compressed capabilities for efficiency, and architectural contracts to prevent vulnerabilities. His publications emphasize hardware security innovations, including CHERI-RISC-V integration, GPGPU memory protection, and randomized testing methodologies. Collaborations involve both academic and industry partners in secure computing ecosystems.

Utkarsh KapoorView profile

Assistant Professor

• Biophysics
• Biomolecular Engineering
• Self-Assembly
• +7 more

Utkarsh Kapoor is an Assistant Professor in the Department of Chemical and Biomedical Engineering at the University of Wyoming, affiliated with the College of Engineering and Physical Sciences and the Molecular and Cellular Life Sciences Program. He is also an Adjunct Professor in the School of Computing and holds the distinguished title of UW Derecho Professor. Education: Ph.D. in Chemical Engineering, Oklahoma State University, 2018 B.E. (Hons.) in Chemical Engineering, Birla Institute of Technology & Science (BITS)-Pilani, India, 2012 His research centers on computational biophysics and biomolecular engineering, with a focus on self-assembly, phase separation, and polymer nanocomposites. Using multiscale modeling, molecular dynamics, and machine learning, his lab investigates protein-nucleic acid interactions and designs novel biomaterials. His work is highly interdisciplinary, bridging chemical engineering, biophysics, and computational science. The recent publications reflect a strong trend in computational modeling of biomolecular systems, particularly in understanding phase separation phenomena and nanoparticle-polymer interactions. These studies employ advanced simulation techniques to probe molecular mechanisms underlying biological organization and material design. Scientific Awards and Honors: NIH Wyoming INBRE Pilot Project funding 2024 Spring Faculty Fellow Award, School of Computing UW Derecho Professor OSU Graduate Research Excellence Award (2019) OSU Foundation Distinguished Graduate Fellowship (2017) Robert L. Robinson Endowed Fellowship (2017) Halliburton Graduate Fellowship in Engineering (2015) Creativity, Innovation and Entrepreneurship Scholarship (2015) ISA Scholarship (2016–2019) Dr. Kapoor advises graduate students and leads the Kapoor Lab, which has secured competitive funding including NIH support. His collaborative research program integrates theory, simulation, and interdisciplinary science to advance bioengineering applications. He actively participates in academic service, including chairing sessions at AIChE and giving invited seminars. The Kapoor Lab is an active research group focused on computational biophysics, with ongoing projects in protein phase separation, chromatin organization, and polymer nanocomposites. The lab fosters a collaborative environment and is part of broader initiatives at the University of Wyoming, including the Molecular and Cellular Life Sciences Program and the School of Computing.

Jean-Charles StinvilleView profile

Assistant Professor

• Materials Informatics
• Cryogenic Materials
• Deformation Processes
• +3 more

Dr. Jean-Charles Stinville is an Assistant Professor in the Materials Science and Engineering Department at the University of Illinois at Urbana-Champaign (UIUC), where he also holds appointments in the Materials Research Laboratory. Previously, he served as a Specialist (2019-2021) and Associate Specialist (2015-2019) at the University of California Santa Barbara (UCSB). His research focuses on the mechanical and environmental performance of metallic materials for extreme applications, including cryogenic and high-temperature environments. He leads experimental developments in in-situ SEM mechanical characterization and materials informatics. Education: Ph.D., Solid Mechanics, Materials Science and Structures Mechanics (Ecole Nationale Supérieure de Mécanique et Aerotechnique / University of Poitiers, 2010) M.Sc., Materials Science and Mechanical Engineering (ISAE-ENSMA / University of Poitiers, 2006) M.Eng., Aeronautics, Computer Science, Materials Science, and Mechanics (ISAE-ENSMA, 2006) Research Interests: Materials Informatics Cryogenic Materials In-situ Characterization Deformation Processes High-/Low-Temperature Materials Sustainable Metallurgy Recent Research Trends: His work emphasizes high-throughput experimental methods and machine learning to predict material behavior. Recent studies focus on plastic localization in nickel-based superalloys, cryogenic performance, and microstructural heterogeneity analysis. Awards: 2024 National Science Foundation Career Award 2024 Kent D. Peaslee Junior Faculty Award 2024 Stanford/Elsevier World's Top 2% Scientists Teaching: Teaches courses including MSE 529 (Hard Materials), MSE 598 (Materials Informatics), and MSE 443 (Design of Engineering Alloys). Recognized with student excellence awards in 2023 and 2024. Labs/Teams: Leads the Stinville Research Group, focusing on experimental and computational approaches to materials design. Collaborates with UCSB and institutions globally via projects like AdvancedExperiment (YouTube) and ResearchGate.

• Computer Architecture
• Embedded Systems
• RISC-V
• +5 more

Prof. Daniel Müller-Gritschneder is a Full Professor of Computer Architecture at TU Wien's Institute of Computer Engineering (Faculty of Informatics) since 2024. Previously, he held roles as research group leader at TU Munich's Chair of Electronic Design Automation and acting professor for Real-Time Systems at TU Munich. He earned his Dipl.-Ing. (2003), Dr.-Ing. (2009), and Habilitation (2019) from TU Munich. His research focuses on Electronic System Level Design, RISC-V domain-specific architectures, embedded ML compiler toolchains, functional safety, and hardware security. He collaborates extensively with industry partners like Infineon, Bosch, BMW, and Mercedes. Active in the RISC-V community, he co-initiated the RISC-V Summit Europe and serves on steering committees for conferences such as DAC, ICCAD, and DATE. Key Research Themes: RISC-V ISA extensions and toolchain development Edge AI/ML on embedded systems Secure and safety-critical processor design High-level synthesis and performance simulation Awards: Best Student Paper Award (2024), IEEE Winter Conference on Computer Vision Habilitationspreis (2019), TU Munich Alumni Association Senior IEEE Member (2019) Teaching includes courses like 'High-Level Synthesis', 'Computer Organization', and 'Embedded Systems Design'. Current projects involve lightweight software for IoT devices and pre-silicon validation of safety-critical RISC-V systems. His work bridges academic research with industrial application through collaborative projects and open-source tool development.

Henri BauerView profile

Associate Professor

• Real-Time Systems
• Embedded Systems
• Avionics
• +3 more

Henri Bauer is an Associate Professor at ISAE-ENSMA in Poitiers, France, specializing in real-time systems and avionics networking. He is a core member of the Real Time Team within the Laboratory LIAS (Laboratoire d'Ingénierie des Systèmes Automatisés), a joint research unit between ISAE-ENSMA and ENSIP (University of Poitiers). His work bridges theoretical scheduling analysis with practical avionics applications, particularly in AFDX networks. Education: PhD in Computer Science from Institut National Polytechnique de Toulouse (INPT), 2011 (Thesis: "Analyse pire cas de flux hétérogènes dans un réseau embarqué avion") Bauer's research centers on real-time scheduling, deterministic networking, and embedded systems. He pioneered trajectory-based analysis for AFDX networks, evolving into buffer dimensioning and end-to-end delay optimization. His recent work integrates deep reinforcement learning for IEEE 802.1Qbv time-aware shapers, targeting avionics and industrial automation. Key contributions include formalizing forward end-to-end delay analysis and resolving serialization optimism in switched Ethernet networks. His publication trajectory (2010-2025) reveals three phases: foundational AFDX analysis (2010-2016), refinement of delay/buffer models (2016-2018), and AI-driven network configuration (2021-2025). Over 80% of his work focuses on avionics networking, with increasing emphasis on machine learning applications for time-sensitive systems. No scientific awards were documented in the source material. While student advisement details are absent, Bauer collaborates extensively with researchers like Frédéric Ridouard, Nassima Benammar, and Emmanuel Grolleau. His grant history isn't specified, but his publications indicate sustained funding for real-time systems research in aerospace contexts. As part of LIAS's Real Time Team, Bauer contributes to France's aerospace research ecosystem through the Téléport 2 campus. The team operates within ISAE-ENSMA's engineering framework, maintaining strong industry ties with Airbus and Thales for avionics validation.

• Electronic Design Automation (EDA)
• RISC-V Architecture
• TinyML (Tiny Machine Learning)
• +3 more

Philipp van Kempen is a researcher at the Chair of Design Automation (Prof. Schlichtmann) at the Technical University of Munich. His work focuses on electronic design automation, specifically targeting RISC-V architecture, TinyML optimization, and LLVM compiler infrastructure for custom hardware accelerators. Key Research Areas: RISC-V ISA extensions, autovectorization, neural network accelerators, and compiler toolchain automation. Collaborations: Works with Daniel Mueller-Gritschneder, Ulf Schlichtmann, and Jefferson Parker Jones. His recent publications highlight contributions to benchmarking TinyML CNN kernels on RISC-V vector hardware, developing semi-automated LLVM support for ISA extensions, and optimizing TinyML inference through frameworks like MLonMCU and muRISCV-NN.

Rolf DrechslerView profile

Professor

• Computer Science
• Formal Verification
• Circuit Design
• +3 more

Rolf Drechsler is a Full Professor and Head of the Group of Computer Architecture at the University of Bremen since 2001, with additional role as Director of the Cyber-Physical Systems Group at DFKI Bremen since 2011. He holds a Dr. phil. nat. in computer science from Johann Wolfgang Goethe University Frankfurt and has held academic positions at Albert-Ludwigs University Freiburg and Siemens AG. Education: Diploma and Dr. phil. nat. in Computer Science (Johann Wolfgang Goethe University Frankfurt, 1992-1995) Previous Roles: Albert-Ludwigs University Freiburg (1995-2000), Siemens AG Munich (2000-2001) His research focuses on formal verification , circuit/system design , and data structures for hardware validation . He has pioneered work on polynomial verification methods, BDD-based synthesis, and quantum computing verification frameworks. Recent publications analyze memristor-based in-memory computing, RISC-V security, and LLM-assisted hardware validation. Key awards include ACM Fellow IEEE Fellow Berninghausen Teaching Award (2018) Multiple best paper awards at ICCAD, DATE, DAC, and DDECS He serves as Associate Editor in journals like IEEE Transactions on CAD and ACM Journal on Emerging Technologies. He co-founded the Graduate School of Embedded Systems and Data Science Center at University of Bremen.

Elliott ForbesView profile

Assistant Professor

• Computer Architecture
• High-Performance Processors
• Energy Efficiency
• +3 more

Elliott Forbes is an Assistant Professor and Director of the Computer Engineering program at the University of Wisconsin-La Crosse's Computer Science & Computer Engineering Department. He holds a PhD in Computer Engineering from North Carolina State University (2016), with a focus on computer architecture. His research emphasizes heterogeneous multi-core processors, thread migration latency, and energy efficiency. He has developed tools like the RISC-V assembler 'dt' and the pipeline analysis tool 'dptv'. Education: BS (Michigan Tech, 2005), MS (NC State, 2008), PhD (NC State, 2016). Industry experience includes roles at Intel, Unisys, and Smiths Aerospace. Awards: IEEE Senior Member (2020), Best Paper Award at ICCD-34 (2016), MIT Lincoln Labs Fellowship (2007-2008). He teaches courses ranging from introductory computer systems to advanced topics in architecture and compiler design.

Bryan ParnoView profile

Professor

• Secure Systems
• Formal Verification
• Cryptography
• +3 more

Bryan Parno is a Professor at Carnegie Mellon University in the College of Engineering, holding the Kavčić-Moura Chair in Electrical & Computer Engineering and Computer Science. His research focuses on designing secure systems with formal verification to ensure rigorous security guarantees in practical implementations. Key Research Areas : Formal verification of distributed/concurrent systems, secure cryptographic protocols, blockchain applications, and hardware-assisted security mechanisms. Awards : Distinguished Artifact Awards at USENIX Security (2025), SOSP (2024), CAV (2024) Jay Lepreau Best Paper Award (OSDI 2025) IEEE Cybersecurity Award for Practice (2024) Sloan Research Fellowship (2018) ACM Doctoral Dissertation Award (2011) Notable Contributions : EverCrypt cryptographic provider (Linux kernel integration 2020) Project Everest (formal verification of HTTPS ecosystem) Verus verification framework IronFleet verified distributed systems Students : Yi Zhou (PhD 2025), Elisaweta Masserova (PhD 2024), Travis Hance (PhD 2024), Abhiram Kothapalli (PhD 2024), Jay Bosamiya (PhD 2024), James Larisch (2023), Antoine Delignat-Lavaud (2021), and others. Collaborations : Microsoft Research, Amazon Web Services (Amazon Scholar 2025), Algorand Foundation (Technical Advisory Committee 2019).

Pierre OlivierView profile

Senior Lecturer

• Computer Architecture
• Virtualization
• Hypervisors
• +4 more

Pierre Olivier is a Senior Lecturer in Computer Architecture specializing in virtualization, hypervisors, systems security, and unikernels. He is affiliated with the Advanced Processor Technology group and has contributed to 37 research outputs since 2017. His work spans embedded systems, cloud computing, and hardware-software co-design, with a focus on improving performance, security, and energy efficiency. Research Interests: Olivier's expertise includes virtual machine optimization, secure software compartmentalization, and cross-architecture execution. His projects, such as HermiTux (a binary-compatible unikernel) and HEXO (offloading compute workloads), highlight his commitment to advancing edge computing and heterogeneous architectures. He collaborates internationally on topics like memory protection and vulnerability mitigation. Key Achievements: He has received the Best Paper Award (2019) and Distinguished Artifact Award (2022) for contributions to unikernel and security research. His work on FlexOS and Secure Code for Capability Hardware (SCorCH) demonstrates his role in advancing secure operating system design. Grants and Projects: Olivier leads or participates in major initiatives like the Centre for Digital Trust and Society and SCorCH, focusing on interdisciplinary cybersecurity and hardware-aware software systems. His datasets, including HermiTux on GitHub, are widely referenced in academic research. Labs/Teams: He contributes to the SCorCH team and collaborates with institutions on projects like Multi-Variant Execution and Heterogeneous-ISA container migration, emphasizing practical applications of theoretical research.

Virendra SinghView profile

Professor

• Cyber Security
• Computer Architecture
• Compiler Support for Modern Architectures
• +6 more

Virendra Singh is a Professor at the Indian Institute of Technology Bombay , affiliated with both the Department of Electrical Engineering and Department of Computer Science & Engineering . He leads the Computer Architecture and Dependable Systems Lab (CADSL) and coordinates the Indo-Japanese Joint Laboratory for Intelligent Dependable Cyber Physical Systems and the Information Security Research and Development Centre (ISRDC). Ph.D. in Computer Science from Nara Institute of Science and Technology (NAIST), Japan (2002-2005) M.E. and B.E. in Electronics & Communication from Malaviya National Institute of Technology (MNIT), Jaipur (1994-1996 and 1990-1994) Research Interests : Virendra Singh focuses on Cyber Security , Computer Architecture , Fault-Tolerant Computing , Formal Verification , Trusted Computing , and Blockchain Technology . His work integrates security into hardware design, with a strong emphasis on Cyber Physical Cognitive Systems and Software Defined Networking . Recent Publications highlight advancements in cache security , quantum-resistant cryptography , malware detection , and heterogeneous computing , reflecting his interdisciplinary approach. Awards : SP Sukhatme Excellence in Teaching Award (2021) Students : He currently supervises 15 Ph.D. students, advancing cutting-edge research in security and architecture.

• Operating Systems
• Computer Architecture
• Virtualization
• +3 more

Prof. Redha Gouicem holds the Chair of Operating Systems at RWTH Aachen University. His research focuses on operating system design, virtualization, and multicore scheduling, with an emphasis on formal verification and performance optimization. Professorship: Operating Systems Location: RWTH Aachen University, Germany Research interests include: Multicore scheduling algorithms Binary translation and virtualization Formal verification of OS components CPU frequency scaling and performance optimization Comparison of scheduling models in Unix/Linux Domain-specific languages for scheduler development Recent work explores hypervisor-agnostic guest overlays, weak memory model translation, and provably correct multicore schedulers. His publications demonstrate technical depth in system software design and concurrency management. Current affiliations: RWTH Aachen University Chair of Operating Systems