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• Power Management IC Design
• Analog Integrated Circuits Design
• Integrated Power Electronics
• +4 more

Junmin Jiang serves as Associate Professor in the Department of Electronic and Electrical Engineering at Southern University of Science and Technology's College of Engineering since 2022, following promotion from Assistant Professor. He directs a research group focused on cutting-edge analog/power IC design with strong industry partnerships including Texas Instruments, Qualcomm, and Analog Devices. His educational background includes: Ph.D. in Electronic and Computer Engineering (2017), The Hong Kong University of Science and Technology Visiting Scholar (2015-2016), State Key Laboratory of AMSV, University of Macau B.Eng. in Electronic Information Engineering (2011), Zhejiang University Dr. Jiang's research centers on power management IC design with three interconnected thrusts: Power ICs for Specific Applications (e.g., audio/LiDAR drivers), Power ICs for AI systems, and AI-enhanced power IC design. His work achieves breakthroughs in switched-capacitor converters, delivering ultra-high efficiency (>97%), fast transient response ( His 15 most recent publications demonstrate consistent leadership in top venues (ISSCC/JSSC), showing accelerating impact in hybrid converter topologies, parasitic loss reduction, and AI-integrated power management. The trend reveals increasing industrial relevance with 8 U.S. patents and real-world implementations in audio/LiDAR systems. Scientific recognition includes: IEEE SSCS Pre-Doctoral Achievement Award (2017) National Overseas High-level Talent (Youth Project, 2022) SUSTech Outstanding Teaching Award (2024) Shenzhen Industrial Innovation Talent Award (2023) As an advisor, he mentors 8+ students including ISSCC awardees and competition winners. His group actively recruits undergraduates for chip design projects, with students winning top honors in National Electronic Design and Mathematical Modeling competitions. Current teaching includes graduate Nonlinear Circuits and undergraduate Microcomputer Principles. The Jiang Research Group maintains strong industry ties for student placements and collaborates with international institutions in the U.S., EU, and Macau. Lab capabilities focus on full-cycle IC design from simulation to tapeout, with recent 100V-output converters achieving 86.2% efficiency for acoustic applications.

• High-Performance Integrated Circuit Design
• Artificial Intelligence Accelerators
• Digital Signal Processing Chips
• +3 more

Dr. Fengwei An is an Associate Professor at the Shenzhen-Hong Kong Institute of Microelectronics , Southern University of Science and Technology (SUSTech). He earned his Ph.D. in Engineering from Hiroshima University (2013) , following a Master's (2010) and Bachelor's (2006) from Qingdao University of Science and Technology. Current Role : 2025-Present - Associate Dean and Associate Professor, SUSTech Shenzhen-Hong Kong Institute of Microelectronics Prior Academic Roles : 2017-2018 - Associate Professor, Hiroshima University; 2013-2017 - Assistant Professor, Hiroshima University Industry Experience : 2018-2019 - Chief Engineer, Panasonic Semiconductor Co., Ltd., Japan Research Interests focus on low-power edge artificial intelligence chip design for computer vision, including: Ultra-large-scale digital integrated circuit design System-on-Chip (SoC) integration Image processing and recognition Machine learning hardware Autonomous driving applications High-speed motion tracking systems Publications include over 80 top-tier journal/conference papers (e.g., TCAS-I/II, ESSCIRC, APCCAS) on AI accelerators, stereo vision processors, and sensor interfaces, with 15 recent articles highlighting advancements in stereo matching, video denoising, and reconfigurable coprocessors. Scientific Awards : 2023 - SUSTech Outstanding Teaching Award 2022 - APCCAS Best Paper Nomination 2022 - PrimeAsia Bronze Leaf Award 2020 - Wu Wenjun Artificial Intelligence Science and Technology Award (Second Prize) Patents : 9 Chinese and 3 Japanese inventions in AI chip design, stereo matching systems, and sensor interfaces.

• Ultra-low power digital circuit design
• Energy-efficient AI processor design
• Compute-in-memory
• +5 more

Dr. Longyang Lin is an Assistant Professor at the School of Microelectronics, Southern University of Science and Technology (SUSTech) in Shenzhen, China. He received his Ph.D. from the National University of Singapore in 2018 and has been with SUSTech since May 2021. His research focuses on cutting-edge integrated circuit design with emphasis on ultra-low power systems, hardware security, and cryogenic circuits. Education: Ph.D., National University of Singapore, 2018 M.Sc., Lund University, 2011-2013 B.Sc., Umeå University & B.Eng., Shenzhen University, 2007-2011 Dr. Lin's research spans ultra-low power digital circuit design , energy-efficient AI processor design , compute-in-memory , on-chip sensor fusion , and cryogenic CMOS circuit design . His work addresses critical challenges in battery-less systems, hardware security, and energy-efficient computing. He has developed innovative solutions for self-powered sensor nodes, widely energy-scalable VLSI systems, and secure integrated circuits that operate across extreme temperature ranges. His recent publications demonstrate a strong focus on hardware security, ultra-low power design, and biomedical applications. The research shows a clear progression toward more integrated systems that combine sensing, processing, and communication in highly energy-constrained environments. Many papers address the challenge of maintaining performance while drastically reducing power consumption, with several targeting sub-nanowatt operation. Scientific Awards: Takuo Sugano Award for Outstanding Far-East Paper, ISSCC 2022 ISSCC Demonstration Session Certificate of Recognition, 2022 ISSCC Demonstration Session Certificate of Recognition, 2020 IEEE SSCS Singapore Chapter Award, 2017 & 2018 ISSCC Student Travel Grant Award, 2017 Dr. Lin actively mentors students and researchers, with openings for Research Assistant Professors, Postdoctoral Fellows, Research Assistants, and Graduate Students. His research group benefits from ample funding and regular tape-out opportunities (3-5 per year across different process nodes). He serves as Associate Editor for IEEE Transactions on VLSI Systems and has authored or co-authored over 40 publications, including 10 in IEEE JSSC, 5 in ISSCC, and 12 in VLSI Circuits conference. His laboratory focuses on integrated circuit design for ultra-low power applications, with specialized expertise in hardware security, energy harvesting systems, and cryogenic electronics. The research environment supports tape-outs in advanced CMOS processes, enabling practical validation of theoretical designs.