Rakesh Kumar is a Professor and John Bardeen Faculty Scholar in the Electrical and Computer Engineering Department at the University of Illinois at Urbana-Champaign. His work focuses on computer architecture, system-level design automation, and low-power computing. PhD in Computer Engineering from University of California, San Diego BS in Electrical Engineering from IIT Kharagpur His research spans all layers of the computing stack, with key contributions to flexible computer systems , waferscale computing , error-resilient architectures , and approximate computing . He has pioneered work on voltage-reliability tradeoffs and peak power management techniques. Recent publications highlight trends in space microdatacenters , printed microprocessors , and neural graph accelerators . His work on plastic chips was recognized as one of the three biggest semiconductor headlines of 2022 by IEEE Spectrum. IEEE Fellow (2024) ISCA Influential Paper Award MICRO Test-of-Time Award ICCAD Ten Year Retrospective Most Influential Paper Award Best Paper Awards at CASES, SELSE, HPCA He has received teaching accolades including the Stanley H. Pierce Faculty Award and Ronald W. Pratt Outstanding Teaching Award . His research group explores hardware-software co-design for emerging applications in AI, IoT, and sustainable computing.
Jian Huang is an Associate Professor of Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign (UIUC), holding a 100% appointment since August 2024. He is also an affiliated Associate Professor in Computer Science and serves as the Y. T. Lo Faculty Fellow in ECE. Huang leads the Systems Platform Research Group and received his Ph.D. in Computer Science from Georgia Institute of Technology in August 2017, where his dissertation earned the College of Computing Dissertation Award. His research focuses on Computer Architecture, Memory and Storage Systems, AI Infrastructure, Distributed Systems, and Systems Security . Huang has pioneered work in sustainable AI infrastructures, modular data centers, neural processing unit virtualization, and ransomware-aware storage systems. His research has been featured in top-tier conferences including ISCA, MICRO, ASPLOS, OSDI, SOSP, and USENIX ATC, with over 50 publications and multiple patents issued worldwide. Huang's research has significant industry impact, with some work transferred into products and featured in popular media outlets including ACM CACM, TechXplore, and Science Daily. His work on non-volatile memory and storage systems has received extensive coverage, with some projects generating over 50 media reports. Among his notable achievements are the ACM SIGMICRO Early Career Award, NSF CAREER Award, IEEE Micro Top Picks (three times), USENIX Best Paper Award, and the MICRO Best Paper Runner Up in 2024. He has secured over $4.01M in grants ($11.12M with collaborators) from NSF, DARPA, Army Research Office, and industry partners. ACM SIGMICRO Early Career Award NSF CAREER Award IEEE Micro Top Picks (three times) USENIX Best Paper Award MICRO Best Paper Runner Up (2024) Google Faculty Research Award NetApp Faculty Fellowship Award Huang actively contributes to the academic community as program co-chair of NVMW'23 and organizer of HotInfra'23. He currently advises 12 Ph.D. students, 1 master student, and multiple undergraduates. His teaching innovations include developing ECE522: Emerging Memory/Storage System and revising ECE511: Computer Architecture with cutting-edge content.
Muhannad S. Bakir is the Dan Fielder Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology and serves as the Director of the 3D Systems Packaging Research Center. His research focuses on heterogeneous integration of microsystems, including 2.5D and 3D ICs and packaging technologies, with significant contributions to advanced cooling systems, electrical and photonic interconnects, and biosensor integration with CMOS. Dr. Bakir's research interests span heterogeneous microsystem design and integration, advanced cooling and power delivery for emerging architectures, electrical and photonic interconnect technologies, biosensor technologies, and nanofabrication. His work addresses critical challenges in next-generation electronics, enabling polylithic integration that concatenates heterogeneous ICs of various functionalities while mimicking monolithic-like densities. His research particularly focuses on co-design of thermal technologies, power delivery networks, and signaling networks for silicon nanoelectronic systems. His recent publications demonstrate strong trends in fused-silica stitch-chip technology for heterogeneous integration, with particular emphasis on RF and mm-wave applications, power delivery for AI accelerators, and thermal management solutions. His work bridges electrical engineering, materials science, and thermal management to solve critical bottlenecks in computing performance and efficiency. 2013 Intel Early Career Faculty Honor Award 2012 DARPA Young Faculty Award 2011 IEEE CPMT Society Outstanding Young Engineer Award 2012 National Academy of Engineering Frontiers of Engineering Symposium Invited Participant 2015 IEEE CPMT Society Distinguished Lecturer 2014 Best Paper of the IEEE Transactions on Components Packaging and Manufacturing Technology More than 25 conference and student paper awards Twelve issued US Patents Dr. Bakir leads the Integrated 3D Systems Lab (I3DS) at Georgia Tech, which is actively researching advanced packaging, interconnects, electrical and thermal design, and system integration. His team has received significant recognition for their work, including multiple best paper awards from major conferences like ECTC, IITC, and CICC. The lab is currently seeking postdoctoral researchers and research faculty to advance next-generation electronics through collaborative research. His lab focuses on enabling the next phase of Moore's Law through polylithic integration, which concatenates heterogeneous ICs of various functionalities (digital, analog, photonic, and mm-wave) using advanced off-chip '2.5D' and '3D' heterogeneous interconnects and packaging. This work impacts applications in high-performance computing, machine learning, edge intelligence, autonomous vehicles, augmented/virtual reality, and healthcare.
Sumeet Kumar Gupta is an Associate Professor in the Department of Electrical and Computer Engineering at Purdue University. His academic career spans from his current role to a prior Assistant Professorship at Pennsylvania State University (2014-2017) and an engineering position at Qualcomm Inc. (2012-2014). He holds a PhD in Electrical and Computer Engineering from Purdue University (2012), an M.S. from the same institution (2008), and a B.Tech in Electrical Engineering from IIT Delhi (2006). B.Tech, Electrical Engineering, IIT Delhi (2006) M.S., Electrical and Computer Engineering, Purdue University (2008) PhD, Electrical and Computer Engineering, Purdue University (2012) Dr. Gupta's research focuses on neuromorphic computing, low power variation-aware VLSI design in emerging nanotechnologies, device-circuit co-design, and nano-scale device modeling/simulations. His work addresses challenges in ferroelectric materials, crossbar arrays for deep neural networks, and energy-efficient AI hardware. Recent publications (2025-2024) highlight trends in: Ferroelectric HfO2/HZO thin films Compute-in-memory architectures Variability/stochasticity analysis Machine learning for device optimization Interconnect resistance/temperature effects AI hardware fault tolerance Scientific Awards & Recognitions: DARPA Young Faculty Award (2016) Early Career Professorship, Penn State (2014) 6th TSMC Outstanding Student Research Bronze Award (2012) Magoon Award (Purdue) Outstanding Teaching Assistant Award (Purdue, 2007) Intel PhD Fellowship (2009) His professional journey includes academic appointments at Purdue University (2020-present, Associate Professor) and Pennsylvania State University (2014-2017, Assistant Professor) after industry experience at Qualcomm Inc. (2012-2014). He maintains IEEE and EDS membership while publishing over 100 refereed works.
Matteo Sonza Reorda is a Full Professor at the Polytechnic University of Turin, affiliated with the Department of Automatic Control and Computer Science (DAUIN). He holds roles such as Partnership Agreement Coordinator with SMAT and has served as Vice-Rector for Research (2021–2024). His research focuses on fault tolerance, hardware reliability, and AI acceleration, with contributions to GPU/CNN reliability, self-test libraries, and defect-oriented testing. Education: M.S. in Electronics Engineering, Politecnico di Torino (1986) Ph.D. in Computer Engineering, Politecnico di Torino (1990) Research Interests: His work spans automatic test equipment, circuit reliability, GPU fault tolerance, neural network hardening, and embedded systems safety . He leads the Electronic CAD & Reliability Group and collaborates with institutions like the ISI Foundation and the National Research Council (CNR). Publications & Impact: With over 180 publications, his recent work emphasizes AI accelerator reliability, fault injection techniques, and safety-critical systems. Key trends include GPU resilience for CNNs, self-test library optimization, and radiation fault modeling in neural networks. Awards & Recognition: IEEE Fellow (2016–) Multiple best-paper awards at IEEE conferences (DDECS, DATE, etc.) Grants & Collaborations: Coordinator of EU projects (RESCUE, TUTORIAL) Partnerships with EDF, Marelli Europe, and SMAT Lead on National HPC/Quantum Computing Spoke 1 (2022–2025) Labs/Teams: Leads the CAD Group and collaborates with the French-Italian LIA LAFISI lab on hardware-software integration.
Mariano Scazzariello is a Lecturer at KTH Royal Institute of Technology, Sweden, affiliated with the School of Electrical Engineering and Computer Science and the Department of Network and Systems Engineering. He teaches the course 'Network Systems with Edge or Cloud Datacenters (IK2227)'. His research focuses on advanced networking topics including machine learning in networks, high-speed packet processing, network emulation, and software-defined networking innovations. His work spans contributions to network emulation tools like Kathará and Megalos, stateful packet processing at terabit scales, and leveraging large language models (LLMs) for network configuration and vulnerability detection. Recent research emphasizes low-latency protocols (e.g., SRv6/DetNet integration) and GPU-centric networking on commodity hardware. Mariano’s publications (2020–2025) highlight expertise in network function virtualization, ASIC-based switching, and optimizing network configurations through AI-driven approaches. He has pioneered frameworks for evaluating routing protocols and virtualizing large network scenarios at scale.
Dr. Akhilesh Jaiswal serves as Assistant Professor of Electrical and Computer Engineering at the University of Wisconsin-Madison, where his research pioneers device-circuit co-design for next-generation computing systems. His work focuses on enabling extreme-edge intelligence through processing-in-pixel technology, in-memory computing architectures, and bio-inspired neuromorphic systems. His academic credentials include: PhD in Nano-electronics from Purdue University (2019) MS from the University of Minnesota (2014) Bachelor of Technology from Shri Guru Gobind Singhji Institute of Engineering and Technology (2011) Dr. Jaiswal's research program centers on revolutionizing edge computing through hardware innovations that integrate sensing and processing. His device-circuit co-design approach leverages alternate state variables to create energy-efficient systems for real-time applications, with particular emphasis on retina-inspired sensors and photonic memory architectures. This work bridges semiconductor physics with AI acceleration needs, targeting applications from autonomous systems to biomedical devices. Analysis of his 2023-2025 publications reveals dominant themes in photonic SRAM-based in-memory computing (40% of output), retina-inspired motion processing (30%), and secure hardware architectures (20%). His team consistently develops novel bitcell designs that enable XOR logic execution within memory arrays while maintaining compatibility with CMOS fabrication processes. Recent work shows increasing focus on biomedical applications of processing-in-pixel technology. His distinguished recognition includes: Three consecutive ISI Exploratory Research Awards (2020-2023) IEEE Brain Community Best Paper Award (2022) 27 issued US patents with multiple pending applications Nomination for USC Moore Inventor Fellowship (2022) Dr. Jaiswal actively mentors graduate researchers through ECE 790/890/990 courses while securing exploratory funding through ISI and Keston Foundation awards. His patent portfolio demonstrates exceptional translational impact, with industry game-changer classifications from USPTO. The 2022 VLSI-SoC nomination and multiple research highlights in major outlets validate his contributions to hardware security and neuromorphic vision sensors. His laboratory develops integrated hardware platforms combining magnetic tunnel junctions, photonic memory, and CMOS image sensors to create unified processing-in-sensor systems. Current projects include retina-inspired motion segmentation for event cameras and electro-optic frequency transducers for quantum computing interfaces, with strong industry collaboration through patent licensing.
Yang Zhou is an Associate Professor in the Department of Computer Science and Software Engineering at Auburn University, part of the Samuel Ginn College of Engineering. His research focuses on big data algorithms, machine learning, data mining, and distributed computing. He has contributed to advancements in federated learning frameworks, graph mining tools, and spatial machine learning for environmental applications like flood mapping. Education includes a Ph.D. in Computer Science from Georgia Tech (2021), M.E. in Computer Application Technology from Chongqing University (2016), and B.E. in Engineering from Jiangnan University (2014). His work emphasizes scalable algorithms for large-scale systems, with tools like DirDense for dense subgraph mining and FedASMU for federated learning optimization. Recent publications explore adversarial robustness, blockchain strategies in IoT, and curriculum-based learning for large language models. He advises on interdisciplinary projects at the intersection of AI and environmental science.
Geng Yuan is an Assistant Professor at the University of Georgia's School of Computing, specializing in AI systems, energy-efficient deep learning, and hardware-software co-design. His work bridges machine learning algorithms with emerging hardware technologies like superconducting circuits and ReRAM. He holds a Ph.D. in Computer Engineering from Northeastern University (2023) and a Master's in Electrical & Computer Engineering from Syracuse University (2016). Doctor of Philosophy (Ph.D.) in Computer Engineering, Northeastern University (2023) Master of Science (M.S.) in Electrical & Computer Engineering, Syracuse University (2016) Bachelor of Science (B.S.) in Electrical Engineering, Beijing University of Technology (2014) His research focuses on optimizing deep learning systems for edge computing and mobile platforms through techniques like model compression, sparse training, and hardware-aware neural architecture search. Recent projects include adapting large language models via hybrid-grained pruning and developing ultra-low-power AQFP circuits for binary networks. Geng Yuan's publications span top venues like NeurIPS, CVPR, ICML, ICLR, ISCA, and DAC, with notable awards including a Best Paper Award at ICLR Workshop 2021, Spotlight Papers at ICLR 2023 and NeurIPS 2021, and a Design Contest 1st Place at ISLPED 2020. Best Paper Award (ICLR Workshop'21) Spotlight Paper Award (ICLR'23, NeurIPS'21) Design Contest 1st Place (ISLPED'20) Best Paper Nomination (DATE'21, ISQED'18) He actively recruits Ph.D., Master's students, and interns to his research group, focusing on advancing AI systems through interdisciplinary approaches combining machine learning, computer architecture, and electronic design automation.
Gordon Wetzstein is an Associate Professor of Electrical Engineering and, by courtesy, Computer Science at Stanford University. He leads the Stanford Computational Imaging Lab and co-directs the Stanford Center for Image Systems Engineering (SCIEN). His research focuses on computational imaging, wearable computing, and neural rendering, blending computer graphics, vision, AI, and optics. Education: Ph.D., Computer Science, University of British Columbia (2011) Diploma, Media Systems Science, Bauhaus University (2006) Research Interests: His work spans computational displays , holography , non-line-of-sight imaging , and AI-driven optical systems . Key projects include Autofocals (gaze-contingent eyeglasses) and neural holography systems. He explores applications in AR/VR, medical imaging, and scientific visualization. Publications: Recent work includes advances in 3D holography, gaze-tracking systems, and AI-optics integration. His papers address challenges in display efficiency, light-field processing, and real-time imaging. Awards: Fellow of Optica NSF CAREER Award (2016) PECASE (2019) ACM SIGGRAPH Significant New Researcher Award (2018) Advising & Grants: He advises over 20 doctoral and postdoctoral students. His lab collaborates with industry (e.g., Raxium, Google) and has secured grants from NSF, DARPA, and private foundations. Labs & Teams: His lab develops cutting-edge systems like neural holography and non-line-of-sight imaging. The SCIEN center fosters interdisciplinary image systems research.
Zhonghai Lu is a Professor of Electronic Systems Design (specializing in Dependable and Autonomous Systems) at KTH Royal Institute of Technology, part of the Department of Electrical Engineering in the School of Electrical Engineering and Computer Science (EECS). He serves as Program Director for KTH's Embedded Systems master's program and Director of Studies at the Division of Electronics and Embedded Systems. His research focuses on Network-on-Chip (NoC), computer architecture, embedded systems, and Prognostics and Health Management (PHM) of power electronics. He leads a research group exploring in-network processing and embedded intelligence, transforming passive networks into active computational frameworks. Lu holds a BSc from Beijing Normal University (1989), MSc and PhD from KTH (2002, 2007), and an MBA in Innovation and Growth from the University of Turku (2012). He has authored over 240 scientific papers, including journal articles and peer-reviewed conferences, with notable recognitions such as Best Paper Awards at NOCS’2015 and EU HiPEAC, and a Featured Paper in IEEE Transactions on Computers (2020). He serves as Associate Editor for ACM Transactions on Architecture and Code Optimization (TACO) and has chaired major conferences like HiPEAC’2017 and NOCS’2018. His research group’s recent work includes integrating AI into hardware acceleration, fault-tolerant neural networks, and RUL estimation for power electronics using recurrent neural networks. Lu has secured grants from the Swedish Research Council and Intel Corporation and developed courses like IL2230 (Hardware Architectures for Deep Learning) and IL2233 (Embedded Intelligence), pioneering embedded AI education at KTH. Education: BSc (Beijing Normal University), MSc/PhD (KTH), MBA (University of Turku) Awards: Best Paper Awards (NOCS, EU HiPEAC), Swedish Research Council Grants, Intel Research Gifts Labs/Teams: Research Group on In-Network Processing and Embedded Intelligence
Naresh R. Shanbhag is the Jack Kilby Professor in the Department of Electrical and Computer Engineering and the Coordinated Science Laboratory at the University of Illinois at Urbana-Champaign. He serves as Director of the Systems on Nanoscale Information fabriCs (SONIC) Center and held the D.J. Gandhi Distinguished Visiting Professorship at IIT Mumbai from 2015-2020. Previously, he was a visiting faculty member at National Taiwan University (2007) and Stanford University (2014). Dr. Shanbhag received his doctorate from the University of Minnesota (1993) in Electrical Engineering. From 1993 to 1995, he worked at AT&T Bell Laboratories as the lead chip architect for AT&T's 51.84 Mb/s transceiver chips over twisted-pair wiring for Asynchronous Transfer Mode (ATM)-LAN and very high-speed digital subscriber line (VDSL) chip-sets. His research focuses on the design of energy-efficient machine learning, communications, and signal processing systems on resource-constrained embedded platforms. He explores fundamental trade-offs between energy efficiency, latency and accuracy of decision-making systems implemented in nanoscale technologies, with applications to computer vision, biomedicine, automatic target recognition, and imaging. His work spans four primary focus areas: Resource-efficient Machine Learning for the Edge, In-memory Computing (IMC), Energy-efficient High Data Rate Communications, and Shannon-inspired Statistical Error Compensation (SEC). Analysis of his recent publications reveals a strong emphasis on in-memory computing architectures (SRAM, MRAM, RRAM) for machine learning acceleration. His work consistently addresses energy-accuracy trade-offs, with increasing attention to security aspects of hardware implementations and applications to MIMO signal processing and edge AI systems. His research demonstrates a progression from theoretical foundations to practical silicon implementations. 2024 Semiconductor Research Corporation Innovation Award 2018 Semiconductor Industry Association/Semiconductor Research Corporation University Researcher Award 2018 IEEE International Symposium on Circuits and Systems Best Paper Award 2006 IEEE Fellow 1996 National Science Foundation CAREER Award Professor Shanbhag has mentored over 50 graduate students who now work at leading technology companies including Qualcomm, Amazon, Nvidia, Intel, and Apple. His research has been generously supported by the National Science Foundation, DARPA, AFRL, Semiconductor Research Corporation, Texas Instruments, Sandia National Laboratories, and industry partners including IBM, GlobalFoundries, and Intel Corporation. He led the Alternative Computational Models research theme (2006-2012) and was the founding Director of the SONIC Center (2013-2017), a 5-year multi-university center funded by DARPA and SRC. Currently, he leads research themes in the SRC and DARPA funded JUMP 2.0 Program's Center for Co-Design of Cognitive Systems and the Center for Ubiquitous Connectivity, and in the NSF IUCRC Center for Advanced Semiconductor Chips with Accelerated Performance (ASAP). As Director of the Systems on Nanoscale Information fabriCs (SONIC) Center, Professor Shanbhag leads a multidisciplinary team exploring novel computing paradigms for the nanoscale era. His group has benchmarked an extensive collection of in-memory computing and digital accelerator IC designs, maintaining a publicly available IMC benchmarking repository of metrics extracted from published IC prototypes. His research philosophy integrates concepts from information theory, statistical signal processing, detection and estimation, VLSI architectures, and digital and analog integrated circuits to develop energy-efficient systems from algorithms to silicon implementations.
Dr. Hiren Patel is a Professor in the Department of Electrical and Computer Engineering at the University of Waterloo. He holds a Doctorate in Computer Engineering from Virginia Tech and previously worked as a postdoctoral fellow at UC Berkeley under Edward A. Lee. His research focuses on real-time embedded systems, computer architecture, machine learning hardware, and cybersecurity. He teaches courses like ECE 150 (Programming), ECE 320/429 (Computer Architecture), and ECE 327 (Digital Systems). Research Interests: Cyber-physical systems and hybrid architectures Hardware/software co-design methodologies Predictable cache coherence protocols IoT and edge computing systems Security in embedded and real-time systems Recent work emphasizes cache coherence solutions for safety-critical systems and GPU acceleration strategies. His publications address challenges in multicore predictability, FPGA bandwidth optimization, and autonomous robotics orchestration. No specific awards are listed, though his extensive publication record indicates significant contributions to embedded systems research. He currently oversees graduate student applications focusing on his core research areas.
Anantha Chandrakasan is the Vannevar Bush Professor of Electrical Engineering and Computer Science at MIT, serving as Dean of the MIT School of Engineering and Chief Innovation and Strategy Officer. His research focuses on energy-efficient integrated circuits, medical devices, and AI hardware security. He leads the MIT Energy-Efficient Circuits and Systems Group, developing systems for biomedical applications, wireless communication, and quantum computing. He holds appointments at MIT's Microsystems Technology Laboratories and has contributed to collaborations like the MIT-Takeda Program in AI-driven healthcare and a partnership with GlobalFoundries for energy-efficient AI chips. His work spans implantable drug delivery systems, conformable ultrasound patches, and secure edge computing architectures. Chandrakasan's innovations include ultra-low-power circuits for IoT devices, cryptographic processors for post-quantum security, and AI accelerators for edge applications. He emphasizes interdisciplinary research bridging electrical engineering with biomedical and quantum fields, supported by leadership roles in MIT's strategic initiatives. His contributions to energy-efficient computing have led to advancements in wearable health monitors, batteryless sensors, and secure communication protocols for medical devices. Ongoing projects include THz integrated systems and AI-enhanced analog circuit design optimization.
Yanzhi Wang is a Professor in the Department of Electrical and Computer Engineering at Northeastern University , affiliated with the Institute for Experiential AI and the Institute for the Wireless Internet of Things . He holds a PhD from the University of Southern California (2014). His research focuses on real-time AI systems, deep neural network compression, neuromorphic computing, and non-von Neumann architectures. Notable projects include NSF-funded initiatives on age-inclusive urban design, superconducting computing (DISCoVER), and edge device optimization (PatDNN). He has received prestigious awards such as the Army Research Office Young Investigator Award and the Constantinos Mavroidis Translational Research Award. His work emphasizes algorithm-hardware co-design for energy efficiency, with grants from NSF, ARO, and industry partners like Google. Recent research trends reflect his focus on accelerating vision transformers, diffusion models, and large language models for edge computing. He has pioneered methods like AutoViT and Fastcar, addressing latency and resource constraints in mobile platforms. Collaborations span academia and industry, driving innovations in superconducting circuits and neuromorphic systems.
