Geoffrey Nelissen is an Assistant Professor in the Department of Mathematics and Computer Science at Eindhoven University of Technology. He holds additional roles as a Research Scientist and Investigador Auxiliar at INESC TEC (Portugal), contributing to interdisciplinary research in real-time systems. His work focuses on schedulability analysis, parallel task execution, and real-time communication protocols, with applications in embedded systems and multicore architectures. Research Interests: Real-Time Scheduling Response Time Analysis Multi-core and Parallel Systems Time-Sensitive Networking (TSN) Formal Verification Recent work emphasizes schedule abstraction frameworks, memory contention analysis, and deterministic communication protocols. His research has received recognition through multiple best paper awards including ICESS 2021 and RTAS 2022. He actively contributes to conferences like RTSS and ECRTS while teaching courses on Real-Time Systems and Operating Systems. Collaborations span European institutions with focus on embedded systems, autonomous driving, and safety-critical applications. Current projects explore holistic approaches to WCRT analysis and resilient real-time communication architectures.
Manolis G.H. Katevenis is a Professor at the Department of Computer Science, University of Crete, and Deputy Director and Head of the Computer Architecture and VLSI Systems (CARV) Laboratory at the Institute of Computer Science (ICS), Foundation for Research & Technology - Hellas (FORTH). He co-founded the European Research Center on Computer Architecture (EuReCCA) and is a founding partner of the European Network of Excellence on High-Performance and Embedded Architecture and Compilation (HiPEAC). PhD in Computer Science from University of California, Berkeley (1983) Co-founder of EuReCCA (2011) Contributed to RISC architecture (1980-1983), interconnection networks (1985-2011), and parallel computing (1993-2010) His research spans Scalable Multicore Systems , Interconnection Network Architecture , Packet Switch Design , Computer Architecture , and VLSI Systems . He has made foundational contributions to per-flow queueing, backpressure mechanisms, and wormhole IP over ATM, with applications in internet routers, data centers, and supercomputers. His publications focus on high-radix crossbar switches, flow control algorithms, and explicit interprocessor communication. Notable scientific awards include: ACM Doctoral Dissertation Award (1984) David J. Sakrison Memorial Prize (1983) IBM PhD Fellowship (1981-1983) Greek State Fellowship (1973-1978) He has supervised 40 graduate theses and participated in 22 R&D projects totaling €9M, including HiPEAC (coordinator of interconnection networks), SARC (FPGA prototype design), and ENCORE (cache-optimized remote DMA). His work has received over 2000 citations, with an h-index of 23.
Heiko Falk is a Professor and Head of the Institute of Embedded Systems at Technische Universität Hamburg (TUHH). His roles include serving as Workshop Chair for the 2024 Embedded Systems Week (ESWEEK), Scientific Coordinator for the B.Sc. and M.Sc. Computer Science programs, and Deputy Head of the Board of Examiners for Computer Science and Engineering. His research focuses on real-time systems, compiler optimizations, and worst-case execution time (WCET) analysis. Key areas include multi-core architectures, cache management, energy efficiency, and hardware/software co-design. Falk's work emphasizes practical compiler techniques for improving real-time performance, such as WCET-aware memory allocation, dynamic SPM optimization, and event-driven scheduling. His publications analyze shared cache interference, preemptive/non-preemptive scheduling, and DMA-aware optimizations. Recent work explores multi-objective trade-offs between WCET, energy consumption, and code size in embedded systems. No scientific awards are explicitly listed, but his contributions to WCET benchmarking (e.g., haRTStone project) and compiler frameworks demonstrate significant impact in the field. Advising and grants: No formal advisees are listed in the provided texts. Falk's work is supported through projects like teamplay, focusing on cyber-physical systems optimization. Labs/Teams: His group operates within TUHH's Institute of Embedded Systems, collaborating on projects addressing real-time system challenges in multi-core environments.
Associate Professor Peter Sutton is an academic at the University of Queensland (UQ), holding roles as Deputy Head of School (Teaching and Learning) and Associate Professor in the School of Electrical Engineering and Computer Science. His research focuses on Engineering Education, Embedded Systems, Reconfigurable Computing, and Electronic Design Automation. He has contributed to curriculum design, remote lab management during the pandemic, and hardware-software co-design for embedded systems. Sutton completed his undergraduate studies at UQ and earned advanced degrees at Carnegie Mellon University, with over three decades of experience in computer systems research and education. Education Bachelor of Science, University of Queensland Bachelor (Honours) of Engineering, University of Queensland Masters of Science (Coursework), Carnegie Mellon University Doctor of Philosophy, Carnegie Mellon University Research Interests Sutton’s work spans engineering pedagogy, embedded system design, and reconfigurable computing. Recent projects include adapting hands-on labs for remote learning during the pandemic and optimizing FPGA-based architectures for data compression and encryption. His contributions to cache optimization and multiprocessor systems highlight his expertise in hardware-software integration. Publications His 50+ publications cover topics like FPGA implementations of neural networks, code compression techniques for VLIW processors, and embedded system design tools. Notable contributions include frameworks for reconfigurable system-on-chip development and methods to enhance debugging practices in post-novice students. Labs & Teams He collaborates within UQ’s School of Electrical Engineering and Computer Science, contributing to research groups focused on embedded systems and engineering education innovation.
Gururaj Saileshwar is an Assistant Professor in the Department of Computer Science at the University of Toronto, within the Mathematical and Computational Sciences school. His research focuses on securing computing hardware and systems, with a focus on microarchitectural security (cache side-channels, Rowhammer attacks), system security (memory safety), and security for machine learning systems. Education: PhD in Computer Science from Georgia Institute of Technology (2019), advised by Prof. Moinuddin Qureshi. B.Tech and M.Tech from Indian Institute of Technology Bombay (India). Prior to UofT, he was with NVIDIA Research. Research interests include developing new attacks, defenses, and tools for automated security analysis. His work has received multiple awards including the IEEE Top Pick in Hardware and Embedded Security, HPCA Best Paper Award, and IEEE HOST Best PhD Dissertation Award. He teaches courses on secure computer systems and hardware security, including CSC427 (Computer Security) and a topics course on secure computer systems. His lab focuses on hardware-software co-design solutions for security and reliability challenges in modern computing systems. Labs/Teams: Leads the Secure Hardware Systems Lab at UofT, collaborating on Rowhammer mitigation, cache attack defenses, and machine learning security. Grants: Active funding from NSF, industry partnerships with NVIDIA, and other hardware security initiatives. Advising: Currently recruiting PhD students interested in hardware security, system security, and machine learning systems security.
Sandhya Dwarkadas is the Walter N. Munster Professor and Chair of the Department of Computer Science at the University of Virginia. Her research focuses on the intersection of computer hardware and software, particularly in parallel computing, computer architecture, and compiler/runtime-architecture interaction. She holds dual roles as department chair and active researcher, balancing leadership with contributions to energy-efficient and reconfigurable computing systems. Education: B.Tech. in Electrical Engineering, Indian Institute of Technology (1986) M.S. and Ph.D. in Electrical and Computer Engineering, Rice University (1989, 1993) Research interests emphasize parallel and distributed computing architectures, with a focus on energy efficiency, cache coherence, and security in multicore systems. Recent work explores mitigating side-channel attacks via innovations like TimeCache and RollingCache. Her publications span 30+ years, addressing both foundational and applied challenges in computer systems. Awards highlight her impact: ACM and IEEE Fellowships (2018/2017), University of Rochester’s Hajim Award (2020), and AAAS Fellowship (2024). She actively mentors students through courses like CS 6190 and leads interdisciplinary projects like TriForce. Labs/Teams: Her work is anchored in the University of Virginia’s Computer Science Department, collaborating across academia and industry to advance next-generation computing systems.
Dr. Alexandra Fedorova is a Professor in the Department of Electrical and Computer Engineering at the University of British Columbia (UBC), with an Associate Member role in the Computer Science department. She leads the Systopia systems research group, focusing on system software design, memory/storage management, and accelerator-centric computing. Her work emphasizes performance optimization, energy efficiency, and hardware-software co-design. She holds a PhD from Harvard University (2006), where she researched operating system scheduling under Margo Seltzer. Prior to UBC, she was an Associate Professor at Simon Fraser University (2006–2015). Fedorova is a recipient of the Alfred P. Sloan Research Fellowship and the Anita Borg Early Career Award. She consults for MongoDB's storage engine team and collaborates with industry on storage and performance challenges. Her research spans tools like Non-sequitur for program trace visualization, studies on storage-class memory (e.g., Optane), and frameworks for GPU acceleration. Recent efforts include Sunstone (spatial accelerator scheduling) and ExtMem (application-aware memory management). Her work bridges low-level systems with high-performance computing needs. Key contributions include optimizing NUMA systems, improving storage engine performance, and exploring processing-in-memory architectures. Fedorova’s projects often involve open-source collaboration, reflected in her GitHub repositories such as vividperf and perf-logging , which support performance analysis tools.
Alastair F. Donaldson is a Professor and Director of Research in the Department of Computing at Imperial College London, where he leads the FastPL research group. His academic career spans over a decade at Imperial, progressing from Lecturer (2011-2014) to Senior Lecturer (2014-2017), Reader (2017-2020), and Professor (2020-present). He has also held significant industry positions, including Founder and Director of GraphicsFuzz Ltd. (acquired by Google in 2018), Senior Software Engineer at Google (2018-2021), and Visiting Researcher at both Google and Microsoft Research Redmond. Donaldson earned his PhD from the University of Glasgow under Alice Miller, following a BSc (hons, First Class) in Computing Science and Mathematics. His postdoctoral work included an EPSRC Postdoctoral Research Fellowship at the University of Oxford and a Research Fellowship at Wolfson College Oxford. His research focuses on formal analysis, software testing and programming languages techniques for improving software reliability, with special emphasis on high-performance systems. Donaldson's work bridges theoretical foundations with practical applications, particularly in compiler testing, GPU programming verification, and metamorphic testing. His research has significantly influenced both academia and industry, as evidenced by the acquisition of his startup GraphicsFuzz by Google. Analysis of his recent publications reveals a strong focus on fuzz testing techniques applied across diverse domains including compilers, GPUs, cryptographic protocols, and large language models. His work consistently combines formal methods with practical testing approaches, addressing challenges in compiler correctness, memory models, and API verification across multiple platforms. 2017 BCS Roger Needham Award EPSRC Early Career Fellowship Best Paper Award, EuroSys 2024 Best Paper Award, MET 2021 Best Paper Award, IWOCL 2019 Best Paper Award, IISWC 2019 Best Paper Award, ICST 2016 ACM SIGSOFT Distinguished Paper Award, ISSTA 2023 ACM SIGSOFT Distinguished Paper Award, FSE 2017 ACM SIGPLAN Most Influential OOPSLA Paper Award, 2022 (for GPUVerify) As Director of Research in the Department of Computing, Donaldson oversees research strategy and development. His FastPL research group investigates novel techniques for programming, testing and reasoning about high performance systems. He has served on numerous program committees and held leadership roles including PLDI Steering Committee Chair (2022-2025) and PACM-PL Advisory Board member. His industry engagement includes testifying as an Expert Witness in the IBM UK Ltd v LzLabs GmbH & Ors case. The FastPL research group, which Donaldson leads, focuses on formal analysis, software testing and programming languages. The group has made significant contributions to compiler testing, GPU verification, and metamorphic testing techniques, with practical impact demonstrated by the acquisition of GraphicsFuzz. Current research directions include fuzzing for zero-knowledge proof circuits, randomized testing of decompilers, and systematic testing of large language models for code generation.
Ioannis Sourdis is a Full Professor at the Department of Computer Engineering, Chalmers University of Technology, Sweden. His research focuses on computer architecture, reconfigurable computing, network-on-chip (NoC) design, memory systems, and fault-tolerant embedded systems, with applications in biomedical informatics and hardware security. Current projects include EUMMSS (Efficient Uncore Mechanisms for Multicore Space Systems, funded by the Swedish National Space Board) and eProcessor (European Processor Ecosystem, funded by the European Commission). Past initiatives include the DeSyRe project (on-demand system reliability), ECOSCALE (exascale reconfigurable computing), and SHARCS (secure hardware-software architectures). His work spans NoC router design (e.g., FastTrackNoC, DDRNoC), memory compression (MemSZ, L2C), and biomedical security applications (heartbeat-based protocols). He has published extensively in venues like DATE, ICS, PACT, and IEEE Transactions on Networking. Key research areas: Chiplet-based systems , hybrid memory architectures , FPGA acceleration , and real-time stream aggregation .
Marco Donato is an Assistant Professor in both the Department of Electrical and Computer Engineering and the Department of Computer Science at Tufts University. He leads the TECS Lab (Testchip, Embedded Computing Systems) focused on hardware design for emerging applications. Prior to joining Tufts, he was a postdoctoral fellow at Harvard University's John A. Paulson School of Engineering and Applied Sciences. Dr. Donato received his academic training from prestigious institutions: Ph.D. in Electrical Sciences and Computer Engineering from Brown University (2016) M.Sc. in Electrical Engineering from Università di Roma La Sapienza, Rome, Italy (2010) B.Sc. in Electrical Engineering from Università di Roma La Sapienza, Rome, Italy (2008) Dr. Donato's research primarily focuses on designing reliable and energy-efficient hardware systems leveraging emerging technologies. His work centers on co-design methodologies for building specialized architectures for machine learning applications that utilize dense, fault-prone embedded non-volatile memories. He investigates noise modeling and reliability aspects of next-generation memory technologies, with particular emphasis on how these can be effectively integrated into system-on-chip (SoC) designs for edge computing and IoT applications. His research bridges the gap between circuit-level design and system-level architecture to create holistic solutions for hardware acceleration of machine learning workloads. Analysis of Dr. Donato's publication record reveals a strong focus on hardware acceleration for machine learning, particularly through innovative memory system designs. His work spans multiple domains including non-volatile memory technologies, energy-efficient circuit design, and flexible SoC architectures. A notable trend is his exploration of how emerging memory technologies can be leveraged to create more efficient implementations of deep neural networks, with particular attention to the trade-offs between reliability, density, and energy consumption. His research often involves full-stack approaches that consider everything from device physics to system architecture. Dr. Donato is actively involved in mentoring and has indicated he is "looking for Ph.D. students." His work has been supported by significant research grants that have enabled the fabrication of multiple test chips, as evidenced by his extensive publication record in top-tier venues including IEEE Journal of Solid-State Circuits, ISSCC, and MICRO. He leads the TECS Lab at Tufts University, which focuses on testchip development, embedded computing systems, and hardware acceleration. The lab appears to maintain connections with researchers at Harvard University and other institutions, reflecting Dr. Donato's collaborative approach to research. The lab's work emphasizes practical, real-world implementations of novel hardware concepts through actual silicon fabrication, which is relatively rare in academic settings.
Jovan Stojkovic is an incoming Assistant Professor at the Department of Computer Science at the University of Texas at Austin, set to join in Fall 2026. Prior to his appointment at UT Austin, he will spend a year at Meta working with the AI and Systems Co-design group. His research focuses on cloud computing and datacenters, with particular emphasis on cloud-native workloads and machine learning inference. Education: PhD in Computer Science from the University of Illinois at Urbana-Champaign, advised by Professor Josep Torrellas Undergraduate studies at the School of Electrical Engineering, University of Belgrade, Serbia, where he was recognized as the best student of the Computer Engineering and Information Theory Department every year from 2017-2020 Research Interests: Jovan's research focuses on cloud computing and datacenters , with two primary domains: Cloud-native workloads , such as microservices and serverless computing. He investigates how to co-design novel hardware platforms and software systems that deliver orders-of-magnitude improvements in performance, energy efficiency, and resource utilization for these emerging workloads. Machine Learning (ML) inference , particularly large language models (LLMs). His work addresses the challenges of ML inference through smart scheduling, workload placement, and system-level configuration tuning to reduce energy, power, and thermal overheads while maintaining performance and accuracy guarantees. Publication Trends: Jovan's publications demonstrate a strong focus on optimizing cloud infrastructure for emerging workloads. His research spans across serverless computing, microservices, and large language model inference. A clear trend emerges in his work: addressing the performance, energy efficiency, and resource utilization challenges of modern cloud workloads through innovative hardware-software co-design approaches. His most recent work shows increasing focus on LLM inference optimization, particularly in the areas of thermal management, power efficiency, and scheduling for many-adapter environments. Awards and Honors: HPCA Best Paper Award (2025) IEEE MICRO Top Picks Honorable Mention (2024) 6 patents with IBM and Microsoft on: Serverless systems, Processor overclocking in the cloud, and Energy-efficient LLM inference W. J. Poppelbaum Memorial Award (2025) for hardware and architecture innovation Mavis Future Faculty Fellowship (2024–2025) Invited to present at 11th Heidelberg Laureate Forum (2024) Kenichi Miura Award (2022) for excellence in High Performance Computing Multiple student travel grants to ISCA, MICRO, ASPLOS, and HPCA Advising and Grants: Jovan is actively seeking prospective PhD students for his research group at UT Austin. His research has been supported through collaborations with major tech companies including IBM, Microsoft, and Meta. His six patents with IBM and Microsoft demonstrate the practical impact of his research in serverless systems, processor overclocking, and energy-efficient LLM inference. His work on serverless computing (MXFaaS, EcoFaaS) and LLM inference optimization has received significant recognition in top-tier computer architecture conferences. Research Groups: During his PhD at UIUC, Jovan worked with Professor Josep Torrellas on cloud infrastructure research. He has collaborated extensively with researchers at IBM Research (particularly Hubertus Franke) and Microsoft (particularly Íñigo Goiri and Ricardo Bianchini). His upcoming position at UT Austin will establish his independent research group focused on cloud computing and datacenter systems. His year at Meta working with the AI and Systems Co-design group will further strengthen his expertise in AI infrastructure.
Brandon Lucia is a Full Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He leads the abstract research group focusing on the intersection of computer architecture, systems, and programming languages. His work bridges theoretical foundations with practical implementations in energy-constrained environments. Lucia's research centers on intermittent computing systems and edge computing in extreme environments. His work on energy-harvesting systems has established fundamental principles for batteryless computing, while his orbital edge computing research pioneers computational intelligence for nanosatellite constellations. These research thrusts address critical challenges in reliability, efficiency, and programmability for systems operating under severe power constraints. His publication record shows a clear evolution from foundational work on intermittent computing models to sophisticated applications in space computing and edge intelligence. Recent publications demonstrate increasing integration of dataflow architectures with energy-harvesting constraints, particularly in satellite constellations where computational resources must be managed across distributed, power-constrained platforms operating in extreme environments. NSF CAREER Award (2017) IEEE TCCA Young Computer Architect Award (2019) Sloan Foundation Fellowship (2021) ASPLOS Best Paper Awards (2018, 2020) OOPSLA Distinguished Paper and Artifact Awards (2015) Lucia actively mentors numerous PhD students including Brad Denby, Zhuo Cheng, and Emily Ruppel, many of whom contribute significantly to his research program. His abstract research group maintains strong industry connections while pursuing fundamental advances in computing systems. The group has developed multiple open-source tools including Legerdemain for program analysis and MultiCacheSim for cache coherence simulation. His laboratory work spans from theoretical foundations of intermittent computing to practical implementations in space systems. Current projects include computational nanosatellite constellations, energy-minimal dataflow architectures, and secure edge computing systems that operate reliably despite frequent power failures.
Juan Manuel Cebrian Gonzalez is an Assistant Professor at the Department of Computer Engineering and Technology, Faculty of Informatics, University of Murcia. His work focuses on computer architecture, parallel systems, and energy-efficient computing. Doctorate: University of Murcia (2011), thesis on fine-grain power and thermal management in multicore processors. Research interests: Designing architectural mechanisms for optimizing power consumption and thermal management in multicore systems, cache coherence in parallel architectures, and vectorization techniques for high-performance computing. His work also explores heterogeneous architectures, fault tolerance, and efficient memory systems. Recent article trends: Focus on cache management, speculative execution, lock-free constructs, and performance-energy trade-offs in edge and heterogeneous computing. Key methodologies include gem5 simulation, Arm SVE, and AVX-512 vectorization. Collaboration: Supervised by Dr. Juan Luis Aragón Alcaraz and Dr. Stefanos Kaxiras. Active in the Computer Architecture and Parallel Systems research group.
Pejman Lotfi-Kamran is an Associate Professor at the School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, where he also serves as the head of the school and director of Turin Cloud Services. His research focuses on computer architecture, systems, approximate computing, and cloud computing, with an emphasis on performance and energy efficiency for big-data applications. His educational background includes: Ph.D. in Computer Science, EPFL (2013) M.Sc. in Electrical and Computer Engineering, University of Tehran (2005) B.Sc. in Electrical and Computer Engineering, University of Tehran (2002) Lotfi-Kamran's research spans computer architecture innovations, including data and instruction prefetching, networks-on-chip, coherence protocols, and many-core processor design. He has pioneered work on scale-out processors, neural acceleration for GPUs, and approximate computing frameworks. His publications appear in top venues such as ISCA, HPCA, MICRO, and IEEE/ACM journals. His recent articles reflect a strong trend in improving system performance through intelligent prefetching, efficient NoC designs, and energy-aware architectures. Key themes include reducing frontend bottlenecks, optimizing cache behavior, and enhancing data delivery in large-scale systems. His work often combines cross-stack insights with hardware-software co-design for real-world impact. Scientific awards and recognitions include: 2017 CADS Best Paper Award 2016 Young Faculty Award from Iran's National Elites Foundation 2012-2013 Intel Ph.D. Fellowship 2012 and 2011 HiPEAC Paper Awards 2011 HPCA Best Student Paper Finalist Multiple academic honors from University of Tehran He has advised several graduate students including Paria Darbani, Ali Ansari, Mohammad Bakhshalipour, and Farid Samandi, many of whom have co-authored significant papers. His teaching spans institutions like Sharif University of Technology, Iran University of Science and Technology, and EPFL, covering advanced computer architecture and multiprocessor systems. He has led research projects such as AxBench and CloudSuite on Simics, and contributed to national initiatives like Iran’s National Grid. He is actively involved in tool development and continues to shape research in next-generation computing systems. He leads the Turin Cloud Services initiative at IPM and is deeply engaged in both theoretical and applied aspects of computer systems research, with ongoing work in neural acceleration, approximate computing, and scalable architectures.
Prof. Dr. Andreas Herkersdorf is a Full Professor and Chair of Integrated Systems at the Technical University of Munich (TUM) School of Computation, Information and Technology. His research focuses on application-specific multicore processors (MPSoC), FPGA-based prototyping, fault-tolerant systems, and energy-efficient architectures, with applications in IP packet processing, automotive systems, and visual computing. He has received multiple IBM innovation awards and serves on editorial boards including the DFG Review Board for computer architecture. Education: Dipl.-Ing. Electrical Engineering (TUM, 1987), Dr. techn. Electrical Engineering (ETH Zurich, 1991) Research: MPSoC architectures, autonomic computing, NoC resilience, FPGA acceleration, and self-optimizing systems. Awards: IBM Master Inventor (1998), IBM Outstanding Technical Achievement Award (2001), multiple IBM Innovation Achievement Awards (1996-2003) His recent publications emphasize hardware/software co-design, machine learning integration for runtime optimization, and network-on-chip innovations. He collaborates on projects involving 6G systems, smartNICs, and automotive communication protocols.
