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Gert Cauwenberghs is a Professor of Bioengineering at the University of California San Diego (UCSD), affiliated with the Jacobs School of Engineering. He co-directs the Institute for Neural Computation and holds a visiting professorship at MIT. His research focuses on neuromorphic engineering, energy-efficient neural interfaces, and wearable biosensors. Key contributions include silicon-based adaptive neural circuits, implantable neural recording systems, and in-ear biosensing devices. Education: M.Eng. in Applied Physics (University of Brussels, 1988), M.S. and Ph.D. in Electrical Engineering (Caltech, 1989–1994). Prior roles include Professorships at Johns Hopkins University and Visiting Professor at MIT. Research Interests: Biomedical integrated circuits, neuromorphic computing, brain-machine interfaces, and energy-efficient neural systems. His work bridges neuroengineering and clinical applications, emphasizing adaptive intelligence and low-power designs. Recent Work: Development of femtojoule-efficient neural chips, high-density neural interfaces, and closed-loop wearable systems. Projects include neurobench benchmarking frameworks and RRAM-based neuromorphic hardware. Awards: NSF Career Award (1997), ONR Young Investigator (1999), PECASE (2000), IEEE Distinguished Lecturer (2003–2004). Grants & Labs: Active in NIH and DoD-funded projects, co-directs the UCSD Institute for Neural Computation. Collaborates with industry on neural interface technologies. Labs/Teams: Cauwenberghs Lab at UCSD focuses on integrated neuroengineering systems, including neural recording systems and neuromorphic computing architectures.

• Neuromorphic Engineering
• Biomedical Integrated Circuits
• Neural Interfaces
• +7 more

Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.

• Very-Large-Scale Integration (VLSI)
• Hardware Accelerators for Artificial Intelligence
• Hardware Security
• +7 more

Suman Datta is a Professor at the Georgia Institute of Technology , holding the Joseph M. Pettit Chair in Advanced Computing and Georgia Research Alliance Eminent Scholar titles. He has a joint appointment with the School of Materials Science and Engineering. Education : B.Tech in Electrical Engineering from IIT Kanpur; Ph.D. in Electrical and Computer Engineering from the University of Cincinnati. Prior Appointments : Stinson Endowed Chair Professor of Nanotechnology at University of Notre Dame (2015–2022); Professor at Penn State (2007–2015); Intel Corporation (1999–2007) in Advanced Transistor Group. Research Interests : His work focuses on high-performance heterogeneous computing using advanced CMOS and beyond-CMOS semiconductors. Key areas include ferroelectric field-effect transistors (FeFETs) , cryogenic computing , in-memory computing , and brain-inspired computing . He explores materials like ferroelectric gate stacks , insulator-to-metal phase transition oxides , and high-mobility oxides for next-generation compute architectures. Recent Article Trends : His group’s publications emphasize BEOL-compatible oxide transistors , negative capacitance , radiation-resilient devices , and machine learning-aided modeling . Subfields include low-voltage memory , 3D Ising machines , dynamic logic at cryogenic temperatures , and monolithic integration of power delivery systems. Scientific Awards : IEEE Fellow (2013) for contributions to transistor technologies NAI Fellow (2016) for societal impact via patents Intel Achievement Award (2003) for high-k/metal gate CMOS Intel Logic Technology Quality Award (2002) for Tri-gate transistors SEMI Award (2012) for high-k dielectrics Penn State Outstanding/ Premier Research Awards (2012, 2015) Advising & Grants : He has mentored students like Wriddhi Chakraborty , Khandker Akif Aabrar , and Sourav Dutta . His research is funded by SRC , DARPA , and NSF , including leadership of the ASCENT and EXCEL centers. Labs & Collaborations : Datta directs the STAR Lab at Georgia Tech, which specializes in atomistic modeling , nanofabrication , and compact model development . The lab collaborates with industry giants like Intel , Micron , and IBM through the ASCENT center.

• Semiconductor Devices
• Nanotechnology
• VLSI Systems
• +7 more

Qing Cao is an Associate Professor of Materials Science and Engineering at the University of Illinois at Urbana-Champaign, with courtesy appointments in Chemistry and Electrical Engineering. He leads the Cao Research Group within the Grainger College of Engineering and serves as Deputy Editor of Science Advances. Dr. Cao received his B.S. in Chemistry from Nanjing University in 2004 and his Ph.D. in Materials Chemistry from the University of Illinois at Urbana-Champaign in 2009. After working for 9 years as a research scientist at IBM Thomas J. Watson Research Center, he returned to UIUC in 2018 as a faculty member. His research focuses on developing functional nanomaterials for unconventional electronic systems, high-performance logic devices, and low-cost energy harvesting. The Cao Research Group specifically works on: nanoelectronic devices based on novel nanomaterials; next-generation memory devices for neuromorphic and in-memory computing; monolithic 3D integration for high performance electronics; high-performance printable electronic materials; and bioelectronics for healthcare applications. His work bridges materials science, chemistry, electrical engineering, and device physics. Analysis of Dr. Cao's recent publications reveals a strong focus on electrochemical memory devices for neuromorphic computing, with significant work on carbon nanotube-based electronics and novel nanomaterials. His 2023 Nature Electronics paper on CMOS-compatible electrochemical synaptic transistors demonstrates his leadership in developing hardware solutions for deep learning acceleration. His research trajectory shows a progression from fundamental carbon nanotube device physics to more applied systems for computing and sensing applications. IBM Pat Goldberg Memorial Best Paper Award (2017) IBM Master Inventor Award (2016) MIT Technology Review TR35 (2016) Forbes '30 Under 30' (2012) and 'Most Influential All-Star Alumni' (2016) Atlantic Council Millennium Fellow (2017) US Frontiers of Engineering by National Academy of Engineering (2016, 2019) 17 IBM Invention Achievement Awards (2011-2018) Dr. Cao has secured significant research funding including NSF grants 1950182 and 2139185. His research group actively recruits graduate students and postdoctoral researchers to work on cutting-edge materials and device projects. His work has resulted in over thirty research papers and fifty patents and patent applications. He teaches graduate courses including MSE 403 (Synthesis of Materials), MSE 460 (Electronic Materials I), and MSE 488 (Optical Materials). The Cao Research Group operates within the University of Illinois' world-class facilities including the Frederick Seitz Materials Research Laboratory and Holonyak Micro and Nanotechnology Laboratory. His research has received support from NSF, DoD, DOE, and industry partners including TSMC. The group's recent $2 million project focuses on developing technology to help mobile devices learn and adapt to their surroundings.

• Nanomaterials
• Electronic Devices
• Optoelectronic Devices
• +5 more

Dr. Jing Li is an Associate Professor and Eduardo D. Glandt Faculty Fellow at the University of Pennsylvania , holding dual appointments in the Electrical and Systems Engineering and Computer and Information Science departments. As co-director of the CyberSavvy nationwide security research center and director of the Penn Computational Intelligence Lab (PennCIL) , she pioneers innovations in non-von Neumann computing paradigms. Her research spans post-CMOS technologies, in-memory computing, and hardware-software co-design for security and AI applications. PhD in Computer Engineering, Purdue University (2009) BSc in Electrical Engineering, Shanghai Jiaotong University (2004) Research Focus: Dr. Li's work addresses fundamental challenges in computer systems across the stack. Key areas include: In-Memory Computing: Liquid Silicon architecture combining RRAM with silicon CMOS through monolithic 3D integration Security Engineering: Transforming computer security from "Art" to formal "Engineering" discipline within CyberSavvy Virtualization: Cloud FPGA abstraction layers decoupling compilation from runtime resource management Graph Analytics: Degree-aware optimization techniques for massive-scale graph processing Deep Learning Systems: Roofline model extensions for FPGA-based CNN acceleration Scientific Impact: Awarded DARPA Young Faculty Award , NSF CAREER Award , and IBM CEO Milestone Award , her team has achieved world records in energy-efficient computing (ENIAD supercomputer). With 46 U.S. patents and over 80 publications, she leads ecosystem development for emerging computing architectures through initiatives like the open-source MEG simulation platform . Community Leadership: Dr. Li serves on program committees for flagship conferences ( ISCA , FPGA Symposium ), chairs the International Memory Workshop , and contributes to the MLsys conference's inaugural committee. She actively mentors through multiple PhD openings and industry collaborations.

• Computer Architecture
• Compiler Design
• Distributed Systems
• +7 more

Dr. Chih-Hung (James) Chen is a Professor in the Department of Electrical & Computer Engineering at McMaster University. His research focuses on noise-related issues in semiconductor devices, low-noise circuit design for medical and communication applications, and thermal noise characterization in nano-scale transistors. He holds senior member status in IEEE and is a licensed Professional Engineer in Ontario. Education: Ph.D., McMaster University, 2002 M.A.Sc., Simon Fraser University, 1997 B.Sc., National Central University, Taiwan, 1991 Research interests include biomedical technologies, microelectronics & VLSI, and digital/smart systems. He has collaborated with companies like Sony Corporation, United Microelectronics Corporation, and Focus Microwaves. His work is supported by grants from the Canada Foundation for Innovation (CFI), NSERC, and the Ontario Innovation Trust (OIT). Notable achievements include serving on the International Advisory Committee of the International Conference on Noise and Fluctuations (2015) and as an editor for the Journal of Low Power Electronics and Applications since 2022. Teaching includes courses like Analysis and Design of RF ICs for Communications and Electronic Devices and Circuits 2. His research lab focuses on advancing noise measurement techniques and designing ultra-low-power analog circuits for emerging applications.

• Biomedical Technologies
• Microelectronics & VLSI
• Digital & Smart Systems
• +5 more

Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.

• Nanotechnology
• Nanoelectronics
• Spintronics
• +5 more

Hua Chen is an Associate Researcher and PhD Supervisor at the School of Quantum Science and Engineering at Southern University of Science and Technology (SUSTech), with extensive experience in quantum computing circuit design and MEMS sensor interfaces. Previously, he served as an Associate Researcher at the Institute of Microelectronics, Chinese Academy of Sciences (2021-2022) and as an Assistant Researcher there from 2017-2021, building on his industry experience as an RF/Analog IC Design Engineer at Southwest Integrated Circuit Design Co., Ltd (2007-2010). Education: Ph.D. in Microelectronics and Solid-State Electronics, University of Chinese Academy of Sciences (2014-2017) M.Eng. in Electronic and Communication Engineering, University of Chinese Academy of Sciences (2011-2014) B.Eng. in Microelectronics, Chongqing University of Posts and Telecommunications (2003-2007) Dr. Chen's research focuses on interface circuit design for quantum computing and MEMS sensors, with particular expertise in high performance analog/RF/mixed-signal IC design. His recent work has shifted toward cryogenic circuit design for quantum bit control and readout systems, representing a strategic pivot toward China's national priority in quantum information technology. His publications reveal a consistent trajectory from MEMS gyroscopes and oscillators toward quantum computing hardware support circuits, demonstrating his ability to adapt expertise to emerging technological frontiers. Dr. Chen's research output shows a clear evolution from traditional MEMS sensor interfaces toward quantum cryogenic electronics, with his 15 most recent publications heavily concentrated in cryogenic circuit design for quantum applications. This represents a strategic shift aligning with China's substantial investment in quantum computing research, particularly in the development of control and readout electronics for scalable quantum systems. His significant honors include: Special talent of Shenzhen's Pengcheng Peacock Plan (January 2024) IEEE Senior Member (February 2022) Intellectual Property Specialist of Chinese Academy of Sciences (January 2020) Outstanding Employee (Top 10%) at Institute of Microelectronics CAS (2020) Multiple Graduate Student Scholarships from Institute of Microelectronics CAS (2015-2017) As a PhD Supervisor at SUSTech, Dr. Chen mentors graduate students in quantum circuit design while leading research funded through multiple sources including a Beijing Natural Science Foundation General Project (RMB 200,000) for RF MEMS disk oscillator drive circuits and a Youth Project (RMB 100,000) for MEMS gyroscope phase alignment. He has also participated in major national projects totaling over RMB 27 million, demonstrating his integration into China's strategic research initiatives. Dr. Chen leads a research group at the International Quantum Academy in Shenzhen focused on cryogenic CMOS integrated circuit design for quantum computing applications. His team develops specialized low-temperature measurement and control chips that address critical challenges in scaling quantum computing systems, with particular emphasis on MEMS-based quantum frequency references and cryogenic amplifiers that operate at temperatures near absolute zero.

• Quantum Computing
• MEMS Sensors
• Analog Circuit Design
• +5 more

Alyssa B. Apsel is a Professor of Electrical and Computer Engineering at Cornell University since 2002 and a Visiting Professor at Imperial College London. She became the IBM Professor of Engineering in 2023 and Director of Electrical and Computer Engineering at Cornell in 2018. Education: B.S., Electrical Engineering, Swarthmore College (1995) M.S., Electrical Engineering, California Institute of Technology (1996) Ph.D., Electrical Engineering, Johns Hopkins University (2002) Research Focus: She specializes in power-aware mixed-signal circuits for scaled CMOS and modern systems. Her group explores cost-effective designs addressing device scaling challenges (variation, noise, reduced analog performance) through analog/mixed-signal innovation, particularly in IoT radios and reconfigurable multi-standard wireless systems. Key areas: RF circuits, VLSI integration, biomedical telemetry, and low-power design. Publication Trends: Her 2016 work spans RF transceiver design, thermometer DAC calibration, biomedical ICs with UWB telemetry, and jitter-measurement circuits. These reflect her expertise in low-power wireless systems, analog/mixed-signal design, and biomedical electronics. Awards: IEEE Fellow (2020) IEEE CAS Distinguished Lecturer (2018-2019) ISLPED Design Contest Second Place (2010) Multiple Student Paper Awards (2000, 1995) Fellowships: Abel Wolman (1997), Caltech Institute (1995) Grants & Leadership: She founded EchoICs, which received a $275,000 NSF STTR Phase I Award (2024) for flexible spectrum radios. Her lab focuses on RF interfaces for implantable electronics and photonic integration.

• RF Mixed Signal Circuit Design
• Ultra-Low Power Radio
• Photonic Integration with VLSI
• +4 more

Professor John D. Cressler is a tenured faculty member at the Georgia Institute of Technology, holding a position within the School of Electrical and Computer Engineering in the College of Engineering. His research focuses on cutting-edge semiconductor technologies, particularly silicon-germanium heterojunction bipolar transistors (SiGe HBTs) for mixed-signal applications spanning RF, microwave, mm-wave, analog, and digital domains. His research interests center on atomic-scale bandgap engineering for next-generation semiconductor devices, with emphasis on SiGe HBT technology development, radiation-hardened circuits for space applications, cryogenic electronics, and device-circuit interactions. His team explores fundamental device theory, broadband noise analysis, profile optimization, 2-D/3-D simulation, compact modeling, and radiation effects. Current projects include Europa-surface mission electronics, D-band/sub-THz systems, and radiation-tolerant receiver designs. Analysis of his 15 most recent publications (2024-2025) reveals a dominant focus on radiation-hardened electronics for space applications (40% of works), millimeter-wave circuit design (30%), and SiGe HBT reliability optimization (30%). Key trends include Europa mission electronics development, D-band/sub-THz circuit innovation, and advanced radiation mitigation techniques using SiGe BiCMOS technology. Professor Cressler teaches multiple courses including ECE 3040 (Microelectronic Circuits), ECE 3450 (Semiconductor Devices), ECE 6444 (Silicon-Based Heterostructure Devices and Circuits), and the interdisciplinary IAC 2002 course on Science, Engineering and Religion. His research is supported by industrial collaborations and Georgia Tech facilities including the Georgia Electronic Design Center (GEDC), NanoTECH, and C-STAR.

• Silicon-Germanium Heterojunction Bipolar Transistors (SiGe HBT)
• Mixed-Signal Semiconductor Devices
• RF and Microwave Circuit Design
• +5 more

Matthias Bucher is a Professor at the Department of Electronics and Computer Engineering, Technical University of Crete. He specializes in analog/RF integrated circuits design, MOSFET compact modeling, and device characterization. His research focuses on nanoscale CMOS, wide-band semiconductor devices, and high-voltage MOSFETs. He leads the Electronics Laboratory and teaches courses such as Electronics II and CMOS Analog IC Design. Education: Ph.D. in Electrical Engineering, Swiss Federal Institute of Technology (EPFL), 1999 M.S. in Electrical Engineering, Swiss Federal Institute of Technology, 1993 Research Interests: Prof. Bucher’s work emphasizes charge-based compact models (e.g., EKV3), RF device modeling, and noise analysis in MOSFETs/JFETs. His contributions include open-source tools for Verilog-A modeling and parameter extraction methodologies for advanced CMOS technologies. Labs/Teams: He directs the Electronics Laboratory , focusing on nanoelectronics and high-reliability circuits. His team collaborates on semiconductor device modeling for aerospace and industrial applications. Grants/Awards: While not explicitly listed, his extensive publication record and leadership in open-source projects indicate sustained recognition in semiconductor research communities.

• Analog/RF Integrated Circuits Design
• MOSFET Compact Modeling
• Wide-band Device Characterization
• +3 more

Tathagata Srimani is an Assistant Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University (CMU), affiliated with the College of Engineering. He previously served as a Postdoctoral Scholar in Electrical Engineering at Stanford University. His academic journey includes a Ph.D. and S.M. in EECS from MIT (2022 and 2018 respectively) and a B.Tech. in E&ECE from IIT Kharagpur (2016). Research Focus: Srimani’s work centers on nanoelectronics and transformative NanoSystems. Key areas include: Carbon nanotube field-effect transistors (CNFETs) and their monolithic 3D integration with silicon Ultra-dense 3D integration of logic and memory to address the 'memory wall' in AI/ML Technology-architecture co-design frameworks for energy-efficient computing Key Achievements: Developed first silicon fab-compatible CNFET processes (TNANO ’18, Nature ’19) Enabled CNFET RISC-V microprocessor and monolithic 3D integration with Analog Devices/SkyWater Recipient of MIT Presidential Fellowship (2016) and Morris Joseph Levin Award (2018) Teaching & Outreach: Teaches semiconductor devices and hardware design, including hands-on 'Hacker Fab' courses. Leads the NEXUS Research Group exploring heterogeneous nanomaterials (e.g., magnetic and oxide semiconductors) and thermal/power management in 3D systems. Future Directions: Expanding into probabilistic computing hardware, co-design frameworks for application-specific systems, and scaling 3D NanoSystem technologies for industrial adoption.

• Nanotechnology
• Beyond-silicon CMOS technologies
• 3D Integration
• +7 more

Dr. Yiran Chen is the John Cocke Distinguished Professor at Duke University's Department of Electrical and Computer Engineering, leading the NSF AI Institute for Edge Computing (Athena) and the Duke Center for Computational Evolutionary Intelligence (DCEI). A global leader in neuromorphic computing, emerging memory systems, and edge AI, he holds prestigious roles including IEEE Fellow and Editor-in-Chief of IEEE Transactions on Circuits and Systems for AI. His research spans machine learning accelerators, security-hardened hardware, and co-design of EDA tools with LLMs. With over 700 publications and 96 patents, he has been awarded 15 paper awards and 17 nominations, including rare Technical Achievement Awards from IEEE societies. He advises over 60 PhD students and 4 postdocs, many of whom hold academic positions worldwide. His work bridges academia and industry, contributing to startups and venture capital through his board roles. Education: B.S. (Tsinghua, 1998) → M.S. (Tsinghua, 2001) → Ph.D. (Purdue, 2005). Career path: Assistant/Associate Professor at University of Pittsburgh (2010–2014) → Duke since 2014. Awards include the ACM SIGDA Outstanding New Faculty Award (2014), NSF CAREER Award (2013), and the Stansell Family Distinguished Research Award (2022). Research focuses on innovations in: (1) Non-volatile memory architectures for AI acceleration, (2) Hardware-software co-design for edge computing, (3) Security in neuromorphic systems, and (4) Large-scale ML for EDA. His group pioneered ReRAM-based accelerators like ReBNN and MARC, and introduced novel edge AI frameworks like Ecco and Prosperity. These works address scalability, energy efficiency, and real-time performance challenges. Key initiatives include the NSF IUCRC for Alternative Sustainable & Intelligent Computing (ASIC), advancing sustainable computing through novel materials and architectures. His leadership in standard-setting bodies like the IEEE Circuits and Systems Society ensures cutting-edge research translates into industry practices. Grants: Lead PIs for multiple NSF AI Institutes and industry partnerships. Labs: Directs the Athena Institute and DCEI, fostering collaboration between academia and industry. Current projects include quantum computing placement algorithms (QPlacer), federated learning frameworks (FedGPT), and neuro-symbolic architectures.

• Emerging memory and storage technologies
• Embedded systems
• Cyber-Physical Systems (CPS)
• +5 more

Carl-Mikael Zetterling is a Professor and Head of Department at Kungliga Tekniska Högskolan (KTH) in Stockholm, Sweden, affiliated with the School of Electrical Engineering and Computer Science (ICT) and the Electronics and Embedded Systems department. His research focuses on process technology and device design for high-temperature, high-power silicon carbide (SiC) electronics, expanding into SiC-based analog and integrated circuits. He has authored over 300 publications, including books on SiC process technology and plagiarism prevention. Dr. Zetterling has held leadership roles such as Vice Dean of the School of ICT (2013–2017) and teacher representative on KTH's faculty board. He has collaborated internationally at Stanford University, Kyoto University, and Kyoto Institute of Technology. His work addresses applications in extreme environments, including Venus exploration and fusion reactor monitoring, with a focus on radiation tolerance and thermal resilience. The 15 most recent publications highlight trends in wide bandgap semiconductors, gamma irradiation effects on SiC devices, and high-temperature integrated circuits. His articles span structural health monitoring with machine learning, novel SiC diode designs, and radiation-hardened electronics. Key contributions include advancements in self-aligned contacts, trench MOSFETs, and compact modeling for extreme conditions. While no formal awards are listed, his roles in technical program committees (TMS Electronic Materials Conference, IEEE SISC Conference) and editorial work demonstrate significant academic service. He teaches courses ranging from digital design to high-temperature electronics, overseeing degree projects in embedded systems, communication, and nanotechnology.

• Process Technology
• Device Design
• Silicon Carbide (SiC) Electronics
• +3 more

Guofu Niu is a Professor in the Department of Electrical and Computer Engineering at Auburn University, holding the Ed and Peggy Reynolds Family endowed chair. His research specializes in semiconductor device physics, compact modeling of SiGe heterojunction bipolar transistors (HBTs), FinFETs, and cryogenic electronics for RF and power applications. Key research areas include RF linearity characterization, avalanche effects, thermal noise, and low-temperature device performance. He has developed advanced models (e.g., Mextram) for circuit simulation tools, enhancing the accuracy of semiconductor design workflows. Publications focus on nano-scale device reliability, tunneling currents, and optimization of RF amplifiers, with applications in 5G technology and extreme-environment electronics. Collaborative projects span industry and academia to advance semiconductor modeling frameworks.

• Semiconductor Devices
• Compact Modeling
• RF Circuit Design
• +3 more