Find Academic Supervisors

• Architectures for fault-tolerant quantum computing
• Topological error correcting codes
• Magic states
• +5 more

Professor Earl T. Campbell is a Professor of Quantum Computation at the School of Mathematical and Physical Sciences, University of Sheffield, and serves as VP of Quantum Science at Riverlane. His research focuses on practical quantum technologies with capabilities beyond classical physics, particularly in fault-tolerant quantum computing. His educational background includes: Physics & Philosophy MSc (2001-2005, Bristol University) Quantum computing PhD (2005-2008, Oxford University) Professor Campbell's research centers on the central question 'What are the optimal blue-prints for large-scale, reliable quantum technologies?' His work spans architectures for fault-tolerant quantum computing, topological error correcting codes, magic states, gate synthesis, and Majorana fermions. His team designs protocols and software to operate future quantum computers reliably despite noise and decoherence, including development of error correction codes, magic state factories (which determine quantum computer processing speed), and algorithm compilation into machine-level commands. His recent publications demonstrate a strong focus on practical aspects of quantum error correction, with significant contributions to surface codes, homological product codes, and efficient decoding algorithms. His work bridges theoretical quantum information science with practical implementation challenges, aiming to reduce resource requirements for fault-tolerant quantum computing. His notable scientific achievements include: Royal Commission of Great Exhibition of 1851 fellowship (2008-2010) EPSRC early career Research Fellow (2015-present) Professor Campbell supervises PhD student Luke Heyfron and collaborates with postdoc Mark Howard. He has received significant grant funding including an EPSRC early career fellow project 'Towards fault-tolerant quantum computing with minimal resources' (EP/M024261/1, £675,867) and Royal Commission fellowship funding (~£100,000). He is an active member of the EPSRC Peer Review College and the Institute of Physics QQQ group Committee, and has organized the FTQT2016 workshop in Benasque, Spain.

Subramanian IyerView profile

Professor

• System Scaling Technology
• Advanced Packaging
• 3D Integration
• +2 more

Subramanian Iyer is a Distinguished Professor at the University of California, Los Angeles (UCLA), holding the Charles P. Reames Endowed Chair in Electrical Engineering with joint appointments in Electrical and Computer Engineering and Materials Science and Engineering. His laboratory focuses on cutting-edge semiconductor research. Primary research domains include: System Scaling Technology : Innovations in semiconductor miniaturization 3D Integration & Advanced Packaging : Techniques for vertical chip stacking and heterogeneous integration Memory Subsystems : Development of embedded DRAM and novel memory architectures Neuromorphic Computing : Hardware implementations of brain-inspired computing Publication analysis reveals three dominant themes across 35+ years of research: Semiconductor materials innovation (SiGe alloys, silicides, MBE growth) Memory technology evolution (embedded DRAM, eFUSE, low-latency designs) System integration advancements (3D packaging, TSV, heterogeneous integration) Significant honors include: IEEE Fellow (1995) and Daniel Noble Award (2012) National Academy of Inventors Fellow (2017) IBM Fellow (2010) with 30+ invention plateaus IMAPS Educator Award (2021) and Daniel C. Hughes Memorial Award (2020) He leads UCLA's NanoLab facility and has been featured in The New York Times and Wall Street Journal for pioneering chiplet technology. Current work focuses on megachip architectures and open-access semiconductor prototyping.

• Computer Science
• Networking Systems
• Software Engineering
• +5 more

Xin Wang is a Professor at Fudan University's School of Computer Science, specifically within the Department of Communication Science and Engineering and affiliated with the State Key Laboratory of ASIC and System in Shanghai, China. With 185 publications spanning two decades (2003-2025), Wang maintains an exceptionally active research profile, particularly evident in recent high-output years including 22 publications in 2019, 19 in 2021, and 13 in 2024. The research portfolio demonstrates deep collaboration networks, most notably with Yang Chen (45 co-authored papers), Yangfan Zhou, and Qingyuan Gong. Wang's research spans multiple critical areas in computer science, with significant contributions to networking systems (particularly CDN optimization, HTTP/3 implementation, and IPv6 infrastructure), software engineering (focusing on work rhythms, testing methodologies, and GUI analysis), mobile applications (including healthcare implementations and accessibility features), and security (especially account security and fraud detection in e-commerce). The interdisciplinary nature of the work is evident through applications in healthcare, e-commerce, campus safety, and IoT systems. Analysis of recent publications (2023-2025) reveals a strong trend toward practical system implementations addressing real-world challenges. The research demonstrates a consistent pattern of moving from theoretical foundations to deployable solutions, with particular emphasis on optimizing performance in networking systems, enhancing security in digital platforms, and improving user experience across diverse application domains. The work frequently incorporates machine learning techniques to solve complex system problems while maintaining practical applicability. While specific grant information isn't detailed in the publication records, the extensive collaboration network spanning multiple institutions in China and internationally suggests substantial research funding support. The consistent publication output across top venues including IEEE/ACM Transactions, INFOCOM, SIGCOMM, and ICSE indicates sustained research productivity and impact.

• Electronic Design Automation
• VLSI Design
• Computer Systems
• +7 more

Shinji Kimura is a Professor at Waseda University's Faculty of Science and Engineering, specializing in VLSI design and electronic systems. He holds a Doctor of Engineering from Kyoto University and has been with Waseda since 2002, previously serving as Associate Professor at Nara Institute of Science and Technology (1993–2002) and Assistant Professor at Kobe University (1985–1993). Kimura's research spans low-power circuit design , approximate computing , FPGA optimization , video coding (HEVC) , and hardware acceleration for AI . His work focuses on energy-efficient architectures for applications like neural networks, computer vision, and ultra-high-definition video processing. Recent publications emphasize hardware-efficient multipliers, neural network compression, and 3D-stacked memory systems. Awards include the LSI IP Design Award (2000, 1999) and the Information Processing Society of Japan Encouragement Award (1993). He leads projects on HEVC encoding/decoding, non-volatile memory optimization, and 3D integrated circuits, with VLSI implementations achieving real-time 8K video processing.

Sam PagliariniView profile

Professor

• Hardware Security
• Chip Design
• Electronic Design Automation (EDA)
• +7 more

Sam Pagliarini is a Professor in the Department of Electrical and Computer Engineering (ECE) at Carnegie Mellon University (CMU), where he leads research in hardware security and trustworthy integrated circuit design. Prior to joining CMU in 2024, he directed the Centre for Hardware Security at Tallinn University of Technology (2019–2023). He holds a Ph.D. in Electrical Engineering from Télécom Paris (France, 2013), an M.S. in Microelectronics from Universidade Federal do Rio Grande do Sul (Brazil, 2011), and a B.S. in Computer Engineering from the same institution (2008). His research focuses on securing hardware design pipelines, including EDA tools for secure chips, countermeasures against hardware trojans, and obfuscation techniques to protect intellectual property. He has pioneered work on reconfigurable-based obfuscation (ReBO), layout-effect-based security mechanisms, and post-quantum cryptographic accelerators. Recent efforts include collaborations on post-quantum cryptography vulnerabilities and silicon demonstrations of hardware trojan insertion methods. Prof. Pagliarini's work spans academia and industry, with contributions to both theoretical frameworks (e.g., SCARF framework for chip security) and applied solutions like the G-GPU ASIC accelerator generator. His research has addressed emerging threats in the IC supply chain and explored trade-offs between security, performance, and design complexity in post-silicon manufacturing.

• Computer Architecture
• Hardware Design
• Signal Processing
• +7 more

Prof. Dr.-Ing. Holger Blume serves as Vice President for Research and Transfer at Leibniz University Hannover while maintaining his academic position as Professor in the Architectures and Systems Section within the Faculty of Electrical Engineering and Computer Science. He holds multiple leadership positions including Chairperson of the Research Commission and Central Ethics Committee, Executive Board member of eNIFE (Leibniz Research Initiative for Neurosciences), and membership in both the Laboratory of Nano and Quantum Engineering and L3S Research Centre. His research interests span computer architecture, hardware design, signal processing, AI accelerators, hearing aid technology, and biomedical engineering. His work bridges theoretical computer science with practical applications in automotive systems, medical devices, and quantum engineering. Professor Blume's research demonstrates strong interdisciplinary connections between electrical engineering, computer science, and biomedical applications, with particular emphasis on hardware-oriented solutions for real-world problems. Analysis of his recent publications (2023-2025) reveals a strong focus on hardware acceleration for AI and signal processing applications, particularly in automotive radar/LiDAR systems and hearing aid technology. His work shows consistent innovation in RISC-V processor design, specialized hardware for mathematical functions, and biomedical applications of engineering principles. The research demonstrates a clear trajectory toward energy-efficient, specialized computing architectures for specific application domains. As Vice President for Research and Transfer, Professor Blume oversees significant research initiatives at Leibniz University Hannover, which hosts multiple Clusters of Excellence including PhoenixD (Photonics, Optics, and Engineering), QuantumFrontiers, and Hearing4all. The university participates in numerous collaborative research centers and junior research groups funded by DFG, BMBF, and EU programs. Professor Blume is actively involved in multiple research facilities including the Laboratory of Nano and Quantum Engineering and the L3S Research Centre. His work connects with Leibniz University's research focuses on optical technologies, quantum optics and gravitational physics, and biomedical research and technology. His leadership positions indicate strong involvement in shaping the research strategy and ethical framework of the university's scientific endeavors.

Vivienne BrandView profile

Professor

• Corporate Law
• Corporate Governance
• Whistleblowing
• +5 more

Vivienne Brand is Professor in Law at Flinders University's College of Business, Government and Law, where she leads the corporate law research program. She serves as General Editor of the Australian Journal of Corporate Law and Deputy Chair of the Law Council of Australia’s Corporations Committee, with expertise in corporate governance, whistleblowing systems, and social licence to operate frameworks. Her policy influence includes invited testimony before Federal parliamentary inquiries on whistleblowing reform and liquidator regulation. Her academic qualifications include: LLB (Honours) Graduate Diploma in Legal Practice (GDLP) Master of Laws (LLM) with Merit Master of Educational Studies (MEdSt) PhD Brand's research critically examines corporate ethics through empirical studies of director behavior, particularly regarding whistleblowing mechanisms and social licence to operate in Australian business contexts. She investigates how directors' duties evolve with societal expectations, regulatory changes, and emerging challenges like AI governance. Her work bridges legal theory with practical compliance frameworks, emphasizing the role of non-financial incentives in ethical corporate behavior. Recent publications (2020-2024) reveal three key trends: (1) Deepening analysis of whistleblowing regulation with focus on financial incentives and Regtech solutions; (2) Expansion into Middle East/North Africa trade law and sustainability governance; (3) Critical examination of AI's impact on director responsibilities and corporate accountability frameworks. Her scholarship consistently connects corporate law with UN Sustainable Development Goals through ethical business practices. Awarded national recognition for teaching excellence: Australian Citation for Outstanding Contribution to Student Learning Vice Chancellor's Award for Teaching Excellence (awarded twice) Brand actively supervises corporate law research and secured funding as Chief Investigator for the 2023-2024 project Innovations in health and aged care: promoting Arab-Australia knowledge transfer , addressing cross-cultural healthcare challenges. Her professional engagement includes non-executive directorships and leadership in the Society of Corporate Law Academics (serving as President until February 2024). She maintains active roles in Law Council of Australia committees, including the Whistleblowing Working Party and Foreign Bribery Divisions, while contributing to global policy discussions on corporate governance standards.

Tarik GrabaView profile

Lecturer

• Hardware Security
• Embedded Systems Design
• Integrated Circuit Reliability
• +3 more

Tarik Graba is a Lecturer at Télécom Paris and a member of the Secure and Safe Hardware (SSH) research team within the Information Processing and Communication Laboratory (LTCI) department. His work focuses on hardware security, embedded systems, and cryptographic implementation. Education: Not explicitly mentioned Current Affiliations: Télécom Paris (Faculty), LTCI, SSH Team His research explores designing secure and reliable integrated systems , with emphasis on managing complexity, power consumption, and flexibility in embedded environments. He contributes to side-channel analysis , lightweight cryptographic algorithms , and hardware-based security mechanisms . The 15 most recent publications highlight his work in lightweight cryptography , hardware security , and embedded system optimization , particularly focusing on RISC-V extensions , side-channel leakage , TRNG circuits , and secure cryptographic processors . Scientific Awards Academic Palms award, Télécom Paris (2021) Tarik Graba collaborates extensively in hardware security research and has advised multiple projects on physical security countermeasures and embedded cryptographic systems . He works with teams like the SSH Laboratory to develop secure hardware architectures.

Stephen A. EdwardsView profile

Associate Professor

• Embedded Systems
• Real-Time Systems
• Hardware Synthesis
• +5 more

Stephen A. Edwards is an Associate Professor at the Computer Science Department of Columbia University , where he explores automating software for embedded systems and real-time control . His work focuses on compiler techniques for languages like Esterel and domain-specific solutions for device drivers and communication protocols . Education : PhD in Electrical Engineering, University of California, Berkeley (1997) MS in Electrical Engineering, UC Berkeley (1994) BS in Electrical Engineering, California Institute of Technology (1992) Research Interests span hardware synthesis , functional programming , and synchronous languages . He develops domain-specific languages to bridge software and hardware, emphasizing determinism and timing precision in embedded systems. His group's work includes projects like the FHW compiler and the Sparse Synchronous Model . Article Trends show a focus on FPGA-based systems , garbage collection for accelerators, and parallel functional programming . These reflect his broader interests in hardware-software co-design and compiler optimization for real-time applications. Students : John Hui (2021-2024, Apple) Max Levatich (2020-) Richard Townsend (2013-2019, Tufts) Nalini Vasudevan (2007-2011, Google) Marcio Buss (2004-2008) Jia Zeng (2002-2008) Cristian Soviani (2002-2007, Synopsys) Consulting & Expert Services : He provides litigation support and expert witness services in patent cases involving software architecture and computer design , including ITC cases. Labs & Projects : Leads research on sparse synchronous systems and hardware synthesis , with initiatives like the GAPS CLOSURE Project and FHW Compiler for translating Haskell to System Verilog.

• Reconfigurable Computing
• Electronics Design Automation
• FPGA Design
• +6 more

Andrea Guerrieri serves as an Associate Professor at the School of Engineering, University of Applied Sciences and Arts Western Switzerland Valais (HES-SO Valais-Wallis), specializing in reconfigurable computing and electronics design automation. His research has established significant industry impact through tools like DynaRapid and Dynamatic, with technology adopted by major semiconductor companies including MIPS, Intel, and AMD-Xilinx. BSc HES-SO in Industrial Systems - System-on-Chip specialization BSC HES-SO in Computer and Communication Systems - Digital Design specialization MSc HES-SO in Engineering - Embedded Hardware and Firmware specialization Professor Guerrieri's research focuses on reconfigurable computing, electronics design automation (EDA), and security, with particular emphasis on FPGA design, high-level synthesis, and post-quantum cryptography implementations. His work bridges the gap between theoretical computer architecture and practical hardware implementations, with strong applications in space technology and embedded security systems. His recent publications demonstrate increasing focus on energy-efficient implementations for space applications and quantum-resistant cryptographic systems. Analysis of his 15 most recent publications reveals a clear research trajectory toward optimizing FPGA implementations for post-quantum cryptography and space applications. His work consistently addresses the performance bottlenecks in high-level synthesis while maintaining practical applicability for industry partners like NASA, CERN, and major semiconductor companies. The recent surge in best paper awards (three in 2024 alone) reflects growing recognition of his contributions to efficient FPGA compilation techniques and cryptographic implementations. Scientific Awards: Best Paper Award at FPL 2024 Best Paper Award at HPEC 2024 Best Paper Award at ISFPGA 2020 Outstanding Short Paper Award at IEEE HPEC 2024 Outstanding TPC Member Award at DAC 2024 IEEE Senior Member (2021) Multiple Best Paper nominations (FCCM 2022, FPL 2022, HiPEAC 2022) Professor Guerrieri actively participates in international research projects including the DyReCte project (2019-2021) on dynamically reconfigurable cryptoengines for nano-satellites. He currently chairs the Onboard Computing topic for the Swiss consortium CHEESE affiliated with NASA SSERVI and collaborates extensively with industry partners including AMD-Xilinx, NVIDIA, Arm, NASA, and CERN, as well as academic institutions like ETH Zurich and University of Geneva. His current research focuses on developing next-generation EDA tools and reconfigurable computing platforms for both terrestrial and space applications. His laboratory work centers around FPGA-based prototyping and validation, with specialized facilities for space applications testing. Professor Guerrieri leads a research team that includes Andres Upegui, Quentin Berthet, Laurent Gantel, and Gabriel Da Silva Marques, focusing on practical implementations of reconfigurable architectures for security and space applications.

Sneha D. GoenkaView profile

Assistant Professor

• Computational Genomics
• Computer Systems Architecture
• High-Performance Computing
• +5 more

Sneha D. Goenka is an Assistant Professor at Princeton University in the Department of Electrical and Computer Engineering, with associated faculty status in the Computer Science department. She earned her Ph.D. from Stanford University (2024) and dual B.Tech./M.Tech. degrees from IIT Bombay (2017). Her research bridges computer systems architecture and computational genomics to develop accelerated genomic pipelines. Education : Ph.D. (Electrical Engineering, Stanford 2024), Dual Degree (IIT Bombay 2017) Her work focuses on optimizing genomic data processing through hardware-software co-design, achieving speedups in clinical and evolutionary genomics. She led the development of the world's fastest genome diagnosis technique using nanopore sequencing and cloud computing. Recent publications highlight her expertise in GPU/FPGA acceleration (SegAlign, Darwin-WGA) and ultra-rapid variant detection pipelines. Her research has been published in top venues like Nature Biotechnology , New England Journal of Medicine , and SC/HPCA conferences . Scientific Awards : Stanford Centennial TA Award (2024) ACM Heidelberg Laureate Forum Young Researcher (2024) Forbes 30 Under 30 (Science) (2023) NVIDIA Graduate Fellow (2022) Cadence Women in Technology Scholar (2021) She advises students in her lab and has collaborated with institutions like Stanford Medicine, NVIDIA Research, and D.E. Shaw Research. She also contributed to the Pratham satellite project at IIT Bombay.

Patanjali SristiView profile

Assistant Professor

• Hardware Security
• Trustworthy Hardware
• AI and IoT Security
• +6 more

Patanjali Sristi is an Assistant Professor at Augusta University's School of Computer and Cyber Sciences, specifically within the Department of Cybersecurity Engineering. Located at 100 Grace Hopper Lane in Augusta, Georgia, Dr. Sristi joined the university in January 2025 after previously working as a Postdoctoral Researcher at the University of Florida with Dr. Swarup Bhunia. Their academic journey began with a B.Tech in Electrical and Electronics Engineering from Pondicherry University in 2011, followed by both MS and Ph.D. in Computer Engineering from the Indian Institute of Technology (IIT Madras). Dr. Sristi's educational background demonstrates a strong foundation in electrical engineering and computer science, with advanced specialization in hardware security. Their Ph.D. research at IIT Madras was supervised by Dr. Kamakoti Veezhinathan, focusing on critical aspects of hardware security that would form the basis of their future research career. Dr. Sristi's research program centers on addressing one fundamental question: "How can we design, measure and build efficient and affordable security assurances for a given hardware design in the context of an untrusted supply chain while respecting the design constraints at each level of abstraction?" This research vision spans three interconnected domains: AI for System Design: Developing data models and AI techniques for next-generation hardware systems AI for Hardware Security: Creating AI models for vulnerability detection, countermeasure evaluation, and mitigation of supply chain threats Cybersecurity for AI: Establishing metrics and algorithms for secure development, deployment, and operation of AI systems Dr. Sristi's scholarly output reveals a consistent focus on hardware security challenges within the modern distributed electronics supply chain. Their work demonstrates a progression from foundational research on hardware trojans and side-channel attacks toward comprehensive frameworks addressing the emerging "zero trust" paradigm in hardware security. A notable trend is the integration of AI/ML techniques with traditional hardware security approaches, reflecting the evolving nature of security threats and countermeasures. Their publications span prestigious venues including IEEE Transactions on VLSI Systems, IEEE Transactions on Computers, and various IEEE conferences, indicating strong recognition within the hardware security community. While specific awards aren't detailed in the available information, Dr. Sristi's research impact is evident through multiple US patents (including US Patent 11,899,827 and US Patent App. 17/392,376) and invitations to deliver talks at prominent organizations including Sony Finishing School, Northrop Grumman, and IEEE events. Their work on Netflix Privacy Analysis was featured in Wired, demonstrating real-world relevance and impact. Dr. Sristi actively engages with students through courses including CSCI 8940 (Dissertation Research), CSCI 8720 (Problems in Computer & Cyber), and CSCI 7900 (Research Colloquium). Their research program appears well-supported through collaborations with major institutions and industry partners, as evidenced by workshops conducted for the Indian Army in conjunction with Pravartak and IIT Madras. These partnerships suggest substantial research funding and collaborative opportunities that enhance the educational experience for students. Though specific lab information isn't provided in the available text, Dr. Sristi's research scope suggests involvement with hardware security laboratories equipped for VLSI design, testing, and security evaluation. Their work on IoT security, hardware trojans, and supply chain security would require facilities for physical device testing, side-channel analysis, and hardware emulation. The focus on "zero trust" implementation for hardware security indicates a research environment that bridges theoretical security models with practical implementation challenges.

Tiantai DengView profile

Lecturer

• FPGA-based Hardware Acceleration
• Sparse Processing Architecture for CNN and GEMM
• Number System and Approximation Computing
• +3 more

Dr. Tiantai Deng is a Lecturer in Electronics and Digital Systems at the School of Electrical and Electronic Engineering , University of Sheffield (since 2021). His industrial background includes a senior research engineer role at HiSilicon/Huawei , where he focused on hardware architecture design for CNN, GEMM, and image/video processing on FPGAs/ASICs. Education: BEng, MSc, PhD Research interests span FPGA-based hardware acceleration , sparse processing architecture for CNN/GEMM, number system design , approximation computing , and high-level design environments . His work integrates algorithm-hardware co-optimization for efficiency in AI and mathematical computing. Recent publications emphasize neurodynamic systems for opinion modeling, parallel processing elements for ODE/AI acceleration, and low-power FPGA implementations for clustering/modulation classification. Earlier work addressed combustion dynamics and image processing pipelines. Contact: t.deng@sheffield.ac.uk | Office: G108, Sir Frederick Mappin Building, Sheffield S1 3JD | ORCID 0000-0003-4507-5746

• Energy-Efficient Computing
• Hardware Acceleration
• Machine Learning
• +3 more

Dr. David Boland is a Senior Lecturer at the School of Electrical and Computer Engineering, University of Sydney. He holds an MEng and PhD from Imperial College London. His research focuses on energy-efficient hardware acceleration, particularly using FPGAs and application-specific integrated circuits (ASICs), to optimize computational efficiency in domains like machine learning and optical communications. He has contributed to projects involving custom hardware accelerators, federated learning for edge computing, and real-time signal processing. Education: MEng, Imperial College London, 2007 PhD, Imperial College London, 2012 Research Interests: Dr. Boland’s work emphasizes reducing computational overhead through customized hardware solutions. He explores techniques for minimizing unnecessary computations while maintaining accuracy, leveraging FPGA-based designs for parallelism and energy efficiency. Key areas include: Hardware acceleration for machine learning FPGA optimization for neural networks Energy-efficient algorithms for edge computing Online arithmetic and latency-accuracy trade-offs Grants & Collaborations: 2022: On-Board Federated Learning in Orbital Edge Computing (NSW Department of Industry) 2017: Fast Automated Anomaly Detection in Communication Networks (Defence Science & Technology Group) Affiliations: Member of the Net Zero Institute, collaborating on sustainable computing solutions.

• VLSI Design
• Wireless Communications (5G/6G)
• Massive MIMO
• +5 more

Mohsin Abbas is an Assistant Professor (Tenure Track) in the Computing Sciences department at Tampere University, Finland. His research focuses on high-throughput, low-latency, and energy-efficient VLSI architectures for baseband processing systems, particularly channel code decoders. He has held roles including Research Assistant Professor at HKUST, Postdoctoral Fellow at McGill University, and Lead Engineer at ASTRI. Education: PhD in Electronics and Computer Engineering (2017), HKUST, under Prof. Chi-Ying Tsui MSc in Computer Science and Engineering (2011), Hanyang University, South Korea BSc in Computer Engineering (2007), University of Engineering and Technology Taxila, Pakistan Research Interests: VLSI Design (ASIC/FPGA) Wireless Communications (5G/6G) Massive MIMO and Compute-In-Memory (CiM) Channel Coding and Hardware Architecture Low-Latency Decoding Algorithms (e.g., GRAND) Energy-Efficient Systems and Green Communication Teaching Experience: HKUST: Digital Circuits and Systems (ELEC 2200), VLSI Design Automation (EESM 5020) Labs/Teams: Integrated Systems for Information Processing (ISIP) Lab, McGill University (2019–2022) HKUST’s ECE Department and ISIP Lab collaborations