Sebastien Pillement

Sébastien Pillement is a Lecturer at Polytech'Nantes, the College of Engineering of the University of Nantes, and a member of the ASIC research team within the IETR UMR 6164 laboratory. His career spans over 13 years at the IUT of Lannion (University of Rennes 1) before joining the University of Nantes in 2012. He holds a PhD in Computer Science from the University of Montpellier II (1998) and a Habilitation à Diriger des Recherches (HDR) from the University of Rennes 1 (2010).

• Current Research Focus: Dynamically Reconfigurable Architectures (DRA), Hardware Security, Fault-Tolerant Embedded Systems, NoC (Network-on-Chip), Design Methodologies.
• Teaching Areas: Digital Circuits, Computer Architecture, Operating Systems, Real-Time Systems, and Algorithms for Embedded Computing.

His research explores flexible and efficient architectures for embedded systems, emphasizing real-time management, reliability, and security. Key article trends include RISC-V processors, neural network acceleration on MPSoC, formal verification of arithmetic circuits, and runtime FPGA scheduling. Collaborations span international institutions like the University of Toronto and CEA, as well as industrial partners such as STMicroelectronics and Thales.

PhD Students:

• Current: Laureline Dubucq (Security & AI), Mustafa Ibrahim (Ultra-Low Power AI), Téo Biton (Runtime Anomaly Detection), Mohamed Amine Zhiri (Adaptive NoC), Juliette Pottier (RISC-V Protection).
• Graduates: Quentin Dariol (Neural Network Timing), Alexis Duhamel (FPGA Scheduling), Safouane Noubir (Security in Multi-Core Systems), Hai Dang Vu (Probabilistic Timing Analysis), David Pallier (Sensor Clock Synchronization).

Projects:

• Current: ADAPTING (2023-2029), FITNESS (2023-2027), SEC-V (2022-2025), NOP (2021-2025).
• Past: SPARTE (2015-2018), ARDyT (2011-2015), FosFor (2008-2011).