Per Stenstrom

Per Stenstrom is a Professor at Chalmers University of Technology in Gothenburg, Sweden, renowned for foundational contributions to computer architecture and high-performance memory systems. His work bridges theoretical innovation with practical implementations in modern processor design.

His research spans data-centric computing paradigms, focusing on memory hierarchy optimization, microarchitectural parallelism, and memory consistency models. Key themes include compression techniques for memory systems, databound architecture solutions, and sustainable performance scaling under power constraints—addressing critical challenges in contemporary computing infrastructure.

Dr. Stenstrom serves as associate editor-in-chief of the Journal of Parallel and Distributed Computing (JPDC) for architecture, senior associate editor of ACM TACO, and topical editor of IEEE Transactions on Computers. He has chaired premier conferences including the IEEE/ACM Symposium on Computer Architecture and IEEE High-Performance Computer Architecture Symposium.

• ACM Fellow
• IEEE Fellow
• Member of the Royal Swedish Academy of Engineering Sciences
• Member of Academia Europaea
• Member of the Royal Spanish Academy of Engineering Science

With four textbooks, approximately 200 publications, and 20 patents, his scholarly output defines modern computer architecture education. His editorial leadership shapes publishing standards across top-tier venues, though no student advising or grant details appear in source materials. Current lecture offerings include memory hierarchy compression, databound architectures, and microarchitectural optimization for modern processors.