جست‌وجوی استاد و پژوهشگر

• Formal verification
• Model checking
• Binary decision diagrams
• +۷ مورد دیگر

Gianpiero Cabodi is an Associate Professor in the Department of Control and Computer Science (DAUIN) at the Polytechnic of Turin, where he is also a member of the University Internship Commission. He is actively involved in teaching and research within the College of Computer, Film and Mechatronics Engineering. Research Interests: His research spans formal verification, model checking, binary decision diagrams, SAT solvers, embedded system design, and cybersecurity. His work emphasizes formal methods for ensuring correctness and security in hardware and software systems, particularly in safety-critical and automotive applications. Recent Publications: His 2024 publications demonstrate a strong focus on optimizing formal verification techniques. He explores interpolation-based improvements in bounded model checking, hardware model checking algorithms, and the use of binary decision diagrams in interpretable machine learning—highlighting a convergence of formal methods with modern AI interpretability and hardware verification. Teaching and Leadership: He has served as a course instructor for advanced data structures in Python, systems programming, and algorithms. He has also directed several doctoral programs in Computer and Systems Engineering. His leadership extends to research projects such as REBECCA and OSMOSIS, and he has chaired international workshops including FMCAD and DIFTS. Research Projects: REBECCA (2023–2026): Scientific Head of Structure, focusing on reconfigurable platforms for secure AI. OSMOSIS (2008–2010): Scientific Responsible for EU-funded codesign of embedded systems. Multiple commercial research projects on embedded systems in automotive, RFID traceability, cybersecurity, and HMI design (2008–2025). Advising and Grants: While no formal students are listed, he has supervised numerous research projects, often as Scientific Manager or Responsible, funded by both EU programs and industry contracts. His work bridges academic research and industrial applications, particularly in automotive and embedded domains. Labs and Teams: He is a key member of the FM - Formal Methods (DAUIN) research group, which focuses on formal verification techniques for digital systems.

• Electronic design automation
• Embedded systems
• Energy efficient electronic systems
• +۱۶ مورد دیگر

Daniele Jahier Pagliari is an Associate Professor in the Department of Control and Computer Science (DAUIN) at Politecnico di Torino, where he is also a member of the Interdepartmental Center PEIC - Power Electronics Innovation Center. He is actively involved in teaching and research, focusing on embedded systems, electronic design automation, and machine learning for edge computing. He teaches courses such as Optimized Execution of Neural Networks at the Edge, Machine Learning for IoT, and Hardware/Software Codesign of Flexible Computing Systems for Edge AI across various engineering programs including Computer Science and Systems Engineering, Data Science, and Automotive Engineering. His research interests span electronic design automation, embedded systems, energy-efficient computing, low-power design, and machine learning. He is particularly engaged in applying machine learning techniques to improve the design and performance of digital and analog circuits, with a focus on edge AI applications. His work aligns with key scientific areas including computer architecture, cyber-physical systems, and scientific computing. The recent publications highlight a strong trend in optimizing deep learning models for resource-constrained environments, accelerating neural network inference on ultra-low-power devices, and integrating physics-based models with AI for battery state estimation. There is also significant focus on using machine learning to enhance electronic design automation, particularly for analog and mixed-signal circuits, reflecting a convergence of AI and hardware design. He leads and participates in several high-impact research projects, including EU-funded initiatives like HAL4SDV, ISOLDE, TRISTAN, and AMBEATion, as well as commercial projects such as MASAI and software platform development for production support. He serves as the Scientific Responsible or Director in multiple projects, demonstrating leadership in both academic and industrial research contexts. He supervises multiple PhD students in the Computer and Systems Engineering program, including Luca Benfenati, Mohamed Amine Hamdi, Beatrice Alessandra Motetti, Giovanni Pollo, and Matteo Risso, whose research topics include latency-optimized inference, compiler optimization for edge devices, and hardware-aware deep learning design. He is also involved in patent development, notably for an instrumentation method to dynamically modify circuit precision. He is a member of the College of Computer, Film and Mechatronics Engineering and contributes to various degree programs. His work supports UN Sustainable Development Goals related to good health, affordable and clean energy, industry innovation, and sustainable cities.

Kun Qinمشاهده پروفایل

پژوهشگر

• Hardware/Software Codesign
• RISC-V Architecture
• Open-Source Hardware
• +۳ مورد دیگر

Kun Qin is a Doctoral Candidate and Research Associate at the Technical University of Munich , affiliated with the IH02 Chair of Computer Architecture and Operating Systems (CAOS) and the I10 Chair of Computer Architecture and Parallel Systems (CAPS). His work focuses on Hardware/Software Codesign , RISC-V Architecture , and Quantum Computing . Current affiliation: Department of Computer Engineering, School of Computation, Information and Technology Research areas: FPGA/ASIC design, quantum-based systems, open-source hardware Teaching: Courses on HDL, Computer Architecture, and Operating Systems (WS23/24–WS24/25) Kun actively participates in academic service as Web Co-Chair for the ACM International Conference on Computing Frontiers (CF'24, CF'25). His research includes FPGA acceleration for RTL verification and quantum control processors. Key scientific achievement: Best Poster Award at SERESSA (2023) . Publications span topics like RISC-V verification frameworks, FPGA-based timing systems, and quantum control processors for superconducting qubits.

Tirado Franciscoمشاهده پروفایل

استاد

• Power Aware Computing
• Heterogeneous Computing
• Applications optimization
• +۴ مورد دیگر

Francisco Tirado is a Full Professor of Computer Architecture at Complutense University of Madrid since 1986. He has held leadership roles including Vice-Chancellor for Research (2012-2015), Dean of the Faculty of Physics (1994-2002), and Director of the Complutense Supercomputing Center (2002-2007). He is a founding member of the Spanish Society for Computer Science (SCIE) and Spanish Society for Computer Architecture (SARTECO). His research focuses on power-aware computing, heterogeneous systems, bioinformatics, and hardware design automation. He has authored over 242 publications and supervised 15 PhD theses. His professional service includes chairing 138 international conferences and serving on numerous committees for EUROMICRO, IEEE, and national research agencies. Education: No explicit details provided, but has been active at Complutense University since 1978. Affiliations: Member of COSCE Executive Board (2012), IEEE Senior Member (2005), and EUROMICRO Board (1991-2004). Research Interests: - Optimizing energy efficiency in high-performance computing systems - Design of heterogeneous architectures and accelerators - Bioinformatics applications through hardware/software co-design - Parallel programming models for emerging architectures - Automation tools for FPGA and embedded systems development Conference Contributions: Played multiple roles (General Chair, Program Chair) for major events like ParCo, HPCA, and EUROMICRO PDP conferences. Delivered 64 keynote/plenary lectures globally. Scientific Awards: Doctor 'Honoris Causa' from universities in Spain, Paraguay, and Peru 2013 National Computer Science Award IEEE Senior Membership Advising: Supervised 15 PhD students. Active in technology transfer contracts with industry. Labs/Teams: Founder and leader of the ArTeCS research group at Complutense University, specializing in computer architecture and high-performance computing innovations.

Simone Orcioniمشاهده پروفایل

دانشیار

• Sensor Systems
• Biomedical Engineering
• Signal Processing
• +۵ مورد دیگر

Prof. Simone Orcioni is an Associate Professor at the Department of Information Engineering, Università Politecnica delle Marche. His research focuses on sensor systems, biomedical engineering, nonlinear signal processing, and embedded systems. He leads projects in structural health monitoring, battery management, and telemedicine solutions. Orcioni's work integrates hardware design, algorithm development, and data analytics to address challenges in infrastructure maintenance, healthcare, and sustainable energy. Education: Not explicitly listed, but his role as an associate professor implies advanced academic credentials in electrical or biomedical engineering. Research interests include wearable sensors for healthcare monitoring, IoT-enabled environmental systems, and stochastic modeling of nonlinear processes. He collaborates on interdisciplinary projects involving robotics, circular economy, and smart infrastructure. His publications span journals and conferences in signal processing, biomedical engineering, and electronics. Notable areas include electrochemical impedance spectroscopy, sleep monitoring systems, and low-cost sensor networks. Orcioni's work emphasizes practical applications, such as non-invasive vital sign detection and sustainable battery recycling processes. Awards: None explicitly mentioned. Grants and collaborations are implied through his research projects but not detailed in the text. He contributes to academic governance via his teaching and administrative roles at the university. Labs/Teams: Affiliated with the Department of Information Engineering's research groups focused on embedded systems, biomedical instrumentation, and nonlinear signal analysis. Collaborates with industry partners on projects like smart EV charging systems and telemedicine platforms.

Theodore S. Norvellمشاهده پروفایل

دانشیار

• Formal Software Verification
• Concurrent Programming
• Algorithm Animation
• +۲ مورد دیگر

Theodore Norvell is Associate Professor in Electrical and Computer Engineering at Memorial University, specializing in formal verification of software/hardware systems and concurrent programming languages. Holds PhD from University of Toronto and leads research on program correctness and algorithm animation. Co-developed The Teaching Machine for educational visualization. Publications focus on hardware/software codesign, reconfigurable architectures, and automated verification techniques.

Tanguy Rissetمشاهده پروفایل

استاد

• Embedded Systems
• Compilation
• High Level Synthesis
• +۳ مورد دیگر

Tanguy Risset is Professor in the Telecommunication Department at Insa-Lyon, specializing in embedded systems, compilation, and software-defined radio. As head of Inria's Socrate project, he coordinates research on cognitive radio networks integrating signal processing, communications, and computer science. His research develops FPGA-based solutions for real-time audio processing and wireless systems, emphasizing compilation techniques for hardware acceleration. Recent publications focus on low-latency audio transmission, spatial sound implementation, and open-source toolchains for FPGA audio DSP.

Daniel Lohmannمشاهده پروفایل

استاد

• Operating Systems
• Embedded Systems
• Real-Time Systems
• +۴ مورد دیگر

Professor Daniel Lohmann leads the Systems Research and Architecture (SRA) group at Leibniz Universität Hannover since 2017, following his role as Associate Professor (Privatdozent) at Friedrich-Alexander-Universität Erlangen-Nürnberg (2009–2016). His work focuses on configurable system software, emphasizing embedded systems, real-time systems, and dependable architectures. Key projects include danceOS (dependability in embedded OS), Sloth (minimal-effort kernels), and AspectC++ (aspect-oriented C++ extension). His research is funded by DFG and addresses challenges in variability management, fault tolerance, and real-time scheduling. Research interests span operating systems design, software product lines, generative programming, and aspect-oriented development. Notable contributions include the CiAO OS family and the Sloth RTOS, leveraging aspect-oriented techniques for flexibility and efficiency. His work on configuration analysis (e.g., static variability in Linux) and fault mitigation (e.g., AN-Codes for soft errors) highlights his expertise in system reliability and optimization. Publications emphasize real-time systems, embedded software, and software engineering, with awards including the Best Paper Award at SPLC 2010 and an Outstanding Paper at RTAS 2017. He supervises theses on system software tailoring, fault tolerance, and industrial software ecosystems. His groups collaborate on invasive computing (SFB/TRR 89) and hardware-aware OS design.

• Computer architecture and parallel systems
• Power-aware computing
• Process and resource management in HPC systems
• +۵ مورد دیگر

Dr. Eishi Arima is a researcher at the Chair of Computer Architecture and Parallel Systems within the Department of Informatics at the Technical University of Munich (TUM). His work focuses on cutting-edge computer architecture and high-performance computing systems, with particular expertise in power-aware computing, resource management, and heterogeneous systems. He actively contributes to numerous international conferences and collaborative research projects addressing challenges in modern computing infrastructure. Dr. Arima's research spans multiple critical areas in computer architecture including memory and storage systems, performance modeling and optimization, hardware/software codesign, and processor microarchitectures. His work demonstrates particular strength in addressing energy efficiency challenges in high-performance computing environments, with numerous publications on power capping, resource partitioning, and sustainable computing approaches. His research bridges theoretical concepts with practical implementations, often incorporating machine learning techniques to optimize system performance under various constraints. Analysis of Dr. Arima's publication record reveals a strong focus on addressing the energy efficiency challenges in modern computing systems. His work consistently targets the intersection of hardware architecture and system-level resource management, with particular emphasis on heterogeneous computing platforms combining CPUs, GPUs, and emerging memory technologies. Over time, his research has evolved from traditional cache and memory system optimizations toward more holistic approaches incorporating machine learning for resource management in power-constrained environments. Recent publications demonstrate increasing attention to sustainability aspects of computing, reflecting broader industry trends toward greener computing solutions. Dr. Arima has served in various organizational capacities for major international conferences including as Program Committee member for SC, IPDPS, and Cluster conferences, and as Program Co-Chair for ACM CF'20. His journal review activities span multiple prestigious publications including IEEE TPDS and Elsevier FGCS. This extensive service demonstrates his recognition as a respected member of the international computer architecture research community. Dr. Arima has mentored numerous students through bachelor's theses, master's theses, and guided research projects. His students have produced research on topics including reinforcement learning for resource management, job scheduling optimization, memory system improvements, and power-aware computing techniques. Several student projects have resulted in publications at reputable conferences, indicating the high quality of research conducted under his supervision. His mentoring covers both theoretical aspects of computer architecture and practical implementation challenges in real-world systems. Dr. Arima is actively involved in multiple research projects including SEANERGYS (EuroHPC), PlasmaPEPS, OpenCUBE, DaREXA-F, ScalNEXT, PDexa, MUNIQC-ATOMS, BB-KI_Chips, QuaST, and Q-DESSI. These projects address various aspects of high-performance computing, from energy efficiency to quantum computing integration. His work contributes to the development of next-generation computing infrastructure that balances performance requirements with sustainability concerns.

Markus Weinhardtمشاهده پروفایل

استاد

• Reconfigurable Computing
• Compiler Development
• Image Processing
• +۳ مورد دیگر

Prof. Dr.-Ing. Markus Weinhardt is a Professor at the Faculty of Engineering and Computer Science at Osnabrück University of Applied Sciences. His research focuses on reconfigurable computing, compiler development, and image processing. He earned his Ph.D. from Karlsruhe Institute of Technology (2000) and held postdoctoral positions at Imperial College London (2000) and PACT XPP Technologies AG (2009). He leads the DFG-funded HiPReP project and organizes workshops like FSP 2016. Education: Ph.D. in Computer Science (Karlsruhe Institute of Technology), postdoctoral research at Imperial College London, and industry experience at PACT XPP Technologies AG. Research Interests: Reconfigurable architectures, FPGA-based acceleration, compiler optimization, and high-performance computing. Projects include HiPReP (high-performance reconfigurable processor) and HPVis (software optimization via FPGA coprocessors). Teaching: Courses on Hardware/Software Codesign, Programming, and Master’s projects in compiler design and hardware optimization. Key Contributions: Over 30 publications, including works on CHiPReP compilers, dynamic scheduling in reconfigurable arrays, and FPGA-accelerated algorithms.

Barry W. Johnsonمشاهده پروفایل

استاد

• Cybersecurity
• Safety Engineering
• Biometrics
• +۳ مورد دیگر

Barry W. Johnson is the L.A. Lacy Distinguished Professor of Electrical and Computer Engineering at the University of Virginia. He has been on faculty since 1984, promoted to Full Professor in 1994. His career includes roles as SEAS Senior Associate Dean (2006-2015), NSF Division Director (2015-2019), and co-founder/CEO of Privaris (2002-2006). He holds B.S., M.S., and Ph.D. in Electrical Engineering from UVA (1979-1983). Research focuses on ensuring safety/security of critical computer systems. Key areas include cybersecurity, safety engineering, biometrics, IoT security, and autonomous systems. Published over 150 articles, 8 book chapters, two books, and holds 40+ patents. Notable honors include IEEE Fellow (1996), National Academy of Inventors Fellow (2016), and NSF Distinguished Service Award (2019). Recent publications emphasize system safety analysis, fault tolerance, and secure transaction methods. His work combines theoretical advancements with practical applications in transportation systems, nuclear safety, and medical devices. Active in both academia and industry, Dr. Johnson's contributions bridge theoretical research and real-world safety-critical systems deployment.

Andreas Gerstlauerمشاهده پروفایل

استاد

• Embedded Systems
• Cyber-Physical Systems
• Internet of Things
• +۷ مورد دیگر

Andreas Gerstlauer is a Professor and holder of the Cullen Trust for Higher Education Endowed Professorship in Engineering #6 at The University of Texas at Austin. He serves as the Associate Chair for Academic Affairs in the Chandra Family Department of Electrical and Computer Engineering. His academic appointments include membership in the Architecture, Computer Systems, and Embedded Systems (ACSES) research area and the Integrated Circuits & Systems (ICS) research area. Dr. Gerstlauer received his Dipl.-Ing. (M.S.) degree in Electrical Engineering from the University of Stuttgart, Germany in 1997 and M.S. and Ph.D. degrees in Information and Computer Science from the University of California, Irvine in 1998 and 2004, respectively. Prior to joining UT Austin in 2008, he was an Assistant Researcher in the Center for Embedded Computer Systems (CECS) at UC Irvine. His research focuses on embedded systems, cyber-physical systems, and the Internet of Things, with particular emphasis on electronic system-level design methods, system modeling, design languages, and embedded hardware/software synthesis. His work spans from novel hardware/software fabrics and System-on-Chip architectures to system-level design automation methods and tools, with special emphasis on underlying system modeling foundations. His research group, the System-Level Architecture and Modeling (SLAM) Lab, investigates resource-constrained and application-specific embedded, high-performance, and edge computing systems. Dr. Gerstlauer's publication record shows a consistent trajectory in advancing system-level design methodologies, with recent work focusing on IoT applications, deep learning inference at the edge, power modeling using machine learning techniques, and advanced simulation frameworks for heterogeneous architectures. His research bridges the gap between theoretical design methodologies and practical implementation, with commercial applications used by organizations including JAXA and NEC Toshiba Space Systems. Humboldt Research Fellowship (2016-2017) Best Research Paper Award at DAC (2016) Best Paper Award at SAMOS (2015) Outstanding Paper Award at ECRTS (2023) IEEE HSTTC Top Pick in Hardware Security (2021) Best Paper Award at MLCAD (2021) Dr. Gerstlauer has successfully mentored numerous Ph.D. and Master's students who have gone on to prominent positions at companies including Google, NVIDIA, Apple, AMD, Facebook, Intel, and Samsung. His research has been supported by major funding agencies including NSF, DOE, SRC, Sandia National Labs, and industry partners such as AMD, ARM, Intel, Qualcomm, and Samsung. He has served in leadership roles for major conferences including General Co-Chair for ESWEEK 2020-2021 and Program Committee Chair for CODES+ISSS 2015-2016. The SLAM Lab, under his direction, currently pursues active research in neuromorphic computing system co-design, accelerator-rich heterogeneous system architectures, and predictive modeling for next-generation heterogeneous computer system design. The lab maintains strong industry partnerships and has produced multiple open-source software tools including QLA-RTS, DeepThings, LIPPo, and NoSSim that have been adopted by both academic and industrial researchers.

Mohamed Abdelfattahمشاهده پروفایل

استادیار

• deep learning systems
• automated machine learning
• hardware-software codesign
• +۷ مورد دیگر

Mohamed Abdelfattah is an Assistant Professor at Cornell Tech and the School of Electrical and Computer Engineering, Cornell University, specializing in machine-learning-centric computer systems for datacenters and mobile devices. Education: B.S., Electrical and Computer Engineering, German University in Cairo (2009) M.S., Electrical and Computer Engineering, University of Stuttgart (2011) Ph.D., Electrical and Computer Engineering, University of Toronto (2016) His research bridges computer architecture and machine learning with core focus areas: Deep learning systems optimization Hardware-aware automated machine learning Reconfigurable computing architectures FPGA-based acceleration He pioneers hardware-software co-design approaches to enhance ML efficiency across computing platforms. Awards: National Science Foundation Early CAREER Award (2024) Vanier Canada Graduate Scholarship Three best paper awards for embedded networks-on-chip for FPGAs His research is funded by the NSF CAREER grant, building on industrial collaborations from prior roles at Intel's Programmable Solutions Group and Samsung where he led hardware-aware ML research teams. His PhD work on FPGA architectures has been adopted by multiple semiconductor companies.

David Atienza Alonsoمشاهده پروفایل

استاد

• Embedded Systems Design
• Internet of Things (IoT)
• Edge Computing
• +۱۳ مورد دیگر

David Atienza Alonso is a Full Professor in the Department of Electrical and Electronics Engineering at the School of Engineering, École Polytechnique Fédérale de Lausanne (EPFL), Switzerland. He leads the Embedded Systems Laboratory (ESL) and serves as Associate Vice President for Centers and Platforms, overseeing major research infrastructure. His work spans embedded systems, IoT, edge AI, and sustainable computing. His research interests focus on system-level design for high-performance and low-power computing systems. Key areas include thermal-aware design of multi-processor systems-on-chip (MPSoC), energy-efficient embedded machine learning, wireless body sensor networks, and electronic design automation (EDA). His lab develops novel methodologies for hardware-software co-design, memory optimization, and edge computing architectures. The analysis of his recent publications reveals a strong trajectory in intelligent, energy-efficient computing systems. His work integrates machine learning with traditional EDA techniques for data center optimization, applies ultra-low power heterogeneous architectures to healthcare wearables, and advances thermal modeling for 3D ICs. Themes of sustainability, real-time processing, and edge intelligence are consistent across his research. Dr. Atienza has received numerous accolades, including: ERC Consolidator Grant (2016) DAC Under-40 Innovators Award (2018) IEEE TCCPS Mid-Career Award (2018) ACM SIGDA Outstanding New Faculty Award (2012) ICCAD 10-Year Most Influential Paper Award (2020) Best paper awards at top-tier conferences He has advised over 40 PhD students, many of whom have gone on to successful academic and industry careers. His research has been supported by major grants, including the ERC grant, and he has co-authored over 450 publications and 14 licensed patents. He plays a significant leadership role in the academic community, having served as Editor-in-Chief of IEEE Transactions on CAD, President of IEEE CEDA (2018–2019), and currently as Chair of the European Design Automation Association (EDAA). He is a Fellow of both IEEE and ACM. His laboratory, the Embedded Systems Laboratory (ESL), is a leading center for research in embedded and cyber-physical systems, fostering interdisciplinary collaboration and innovation in sustainable computing technologies.

Krzysztof Gajمشاهده پروفایل

استاد

• Cryptographic Hardware
• Post-Quantum Cryptography
• Lightweight Cryptography
• +۶ مورد دیگر

Krzysztof Gaj is a Professor and Associate Chair for Graduate Studies in the Department of Electrical and Computer Engineering at George Mason University. He co-directs the Cryptographic Engineering Research Group (CERG), a leading group in applied cryptography. He holds a PhD and MSc in Electrical Engineering from Warsaw University of Technology. Research Focus: Specializes in cryptographic hardware, post-quantum cryptography, lightweight cryptography, FPGA design, and hardware security. His work has influenced AES and SHA-3 standards, and he currently evaluates post-quantum and lightweight cryptographic algorithms for federal standards. Awards: Outstanding Faculty Award (ECE Department) NIST Diploma of Appreciation (SHA-3 Support) Outstanding Teaching Award (Volgenau School) Grants & Projects: Resurrecting SIKE - Commonwealth Cyber Initiative (2023-2024) Side-Channel Attack Countermeasures - NSF (2018-2024) PQC in Hardware - NIST (2018-2023) Teaches courses on FPGA design and cryptographic engineering. Actively involved in international research collaborations through CERG.