Jenna Wise DiVincenzo is an Assistant Professor at the Elmore Family School of Electrical and Computer Engineering at Purdue University. She specializes in research areas such as software verification, formal methods, and programming languages, with a focus on gradual verification techniques that combine static and dynamic analysis. Her work emphasizes usability and scalability in verification tools, and she has contributed to projects like Gradual C0 and gradual null-pointer analysis. Dr. DiVincenzo earned her PhD in Software Engineering from Carnegie Mellon University (2023) and a BS in Mathematics and Computer Science from Youngstown State University (2017). She has interned at IBM Research, MIT Lincoln Laboratory, and the Software Engineering Research and Empirical Studies Lab at YSU. Her awards include the Google PhD Fellowship, NSF GRFP Fellowship, and 2022 Rising Star in EECS. Her research projects span theoretical advancements in gradual verification, empirical studies on usability, and practical tool development. She advises PhD students (e.g., Craig Liu, Conrad Zimmerman) and collaborates on initiatives like gradual verification for Rust and educational tools to teach verification concepts. Her work also explores leveraging large language models for specification generation and enhancing verification tool soundness through formal proofs.
Paolo Ienne is a Professor at the Swiss Federal Institute of Technology in Lausanne (EPFL), where he leads the Processor Architecture Laboratory (LAP) within the School of Computer and Communication Sciences. His research focuses on advancing reconfigurable computing systems through innovative FPGA architectures and high-level synthesis methodologies. His primary research domains include reconfigurable computing, FPGA architecture design, dynamically scheduled dataflow circuits, and hardware acceleration techniques. Recent work emphasizes memory system optimization for FPGAs, formal verification of circuit transformations, and rapid C-to-hardware compilation flows. He has pioneered approaches for handling thousands of outstanding memory misses in FPGA accelerators and developed novel techniques for switch-block exploration without explicit pattern enumeration. Analysis of his 2023-2025 publications reveals a strong trend toward practical FPGA deployment challenges, with increasing focus on HBM integration, virtual memory systems for PCIe-attached devices, and formally verified circuit transformations. His work consistently targets real-world bottlenecks in high-level synthesis toolchains while maintaining theoretical rigor in dataflow architecture design. Professor Ienne's laboratory receives support from the Swiss National Science Foundation and industry partners including Huawei, enabling cutting-edge research in FPGA-based acceleration. His collaborative network spans major semiconductor companies and academic institutions worldwide, with frequent co-authorship on conference proceedings and journal publications in IEEE and ACM venues.
Sanjit A. Seshia is the Cadence Founders Chair Professor in the Department of Electrical Engineering and Computer Sciences at the University of California, Berkeley . He is affiliated with the Group in Logic and the Methodology of Science and participates in centers like the Industrial Cyber-Physical Systems Center , Berkeley AI Research , and the Simons Institute for the Theory of Computing . Research interests include formal methods for automated verification and synthesis of dependable systems, with applications to cyber-physical systems , AI-based autonomy , and computer security . His work spans SMT solving, model counting, syntax-guided synthesis, and algorithmic improvisation, with tools like UCLID5 , VerifAI , and Scenic for verifying autonomous systems and educational platforms like CPSGrader . Students and collaborators include notable researchers such as Dorsa Sadigh (Stanford), Daniel Fremont (UC Santa Cruz), and Hazem Torfah (Chalmers). He has co-founded startups like Decyphir and 20ⁿ Labs based on his research.
Professor Peter Y. K. Cheung is a Professor of Digital Systems at Imperial College London, holding dual affiliations within the Department of Electrical and Electronic Engineering and the Dyson School of Design Engineering. His work focuses on reconfigurable systems, FPGA architectures, and high-level synthesis tools. He co-founded one of the UK's leading FPGA research groups with Professor Wayne Luk, addressing challenges in variability mitigation, reliability, and application-specific FPGA deployments. His research spans Field-Programmable Gate Arrays (FPGAs) Reconfigurable computing Neural network acceleration Cryptographic protocols Embedded systems He has pioneered techniques such as logic shrinkage for FPGA-based neural networks and developed frameworks like LUTNet for efficient inference. His contributions also include fault-tolerant FPGA designs and methodologies for distributed computation protocols. Key collaborations include work with the Department of Computing on FPGA-based AI acceleration and cybersecurity applications. His recent work explores edge computing, secure decentralized systems, and pandemic modeling using adaptive control strategies. Notable projects include the DSCS protocol for secure distributed computation, acceleration of gravitational wave detection algorithms, and energy-efficient CNN implementations. His research bridges hardware-software co-design with real-world applications in healthcare, finance, and aerospace.
David Basin is a Full Professor at the Department of Computer Science, ETH Zurich, and heads the Information Security Group. He has held academic positions since 2003, including roles at the University of Freiburg (1997–2002) and the Max-Planck-Institut für Informatik (1992–1997). His research focuses on Information Security, including methods and tools for secure systems, formal verification, and cryptographic protocols. He is Editor-in-Chief of the ACM Transactions on Privacy and Security and Springer's Information Security and Cryptography book series. Basin founded the Zurich Information Security Center (ZISC) in 2003 and led it until 2011. Education: B.Sc. in Mathematics (Reed College, 1984), Ph.D. (Cornell University, 1989), and Habilitation (University of Saarbrücken, 1996). Research interests span formal methods for security protocol verification, privacy-preserving systems, and cryptographic implementations. He has contributed to foundational work on security protocols, including the Tamarin verification framework. His work addresses real-world systems like payment protocols (EMV), DNS security, and database isolation guarantees. Awards: ACM Fellow (2018) for contributions to Information Security and Formal Methods, IEEE Fellow. He has organized numerous conferences, including IEEE S&P, Euro S&P, and ACM CCS. Labs/Teams: Leads the Information Security Group at ETH Zurich and co-founded Anapaya Systems, a startup focused on network security solutions. His team develops tools like VeriMon (formally verified monitoring) and Tamarin for protocol analysis.
Alexander Summers is an Associate Professor at the Department of Computer Science , University of British Columbia . He joined UBC in March 2020 after serving as a Senior Researcher (Oberassistent) at ETH Zurich from 2014-2020. His research bridges Programming Languages , Formal Methods , and Software Engineering , with a focus on automated verification tools for heap-based and concurrent programs. MSc Joint Mathematics and Computer Science, Imperial College London (2004) PhD Computer Science, Imperial College London (2009) Postdoc, ETH Zurich (2009-2014) Summers leads the Prusti Project , developing deductive verification tools for Rust, and contributes to the Viper Project for intermediate verification languages. His work addresses challenges in: Memory safety and concurrency verification Ownership models and aliasing control Automated reasoning with SMT solvers Resource-oriented programming specifications Debugging verification condition quantifiers Formal validation of verification infrastructure His research has been recognized with a Amazon Research Award and ACM SIGPLAN Distinguished Paper Awards . He teaches courses like Advanced Software Engineering and Program Verifiers and Program Verification , and supervises graduate students in formal verification and Rust-related research.
Conrad Watt is an Assistant Professor at Nanyang Technological University (NTU), Singapore , specializing in WebAssembly, formal verification, and concurrency. He previously served as a Research Fellow at Peterhouse, University of Cambridge, and earned his PhD under Peter Sewell. Co-chair of the W3C WebAssembly Community Group Active in WebAssembly standards development, including concurrency specifications Developed mechanizations in theorem provers like Isabelle/HOL Collaborator with industry (wasmtime engine) and academic teams on verification tools Research Focus: Formal verification of low-level languages, concurrency models, and security mechanisms for WebAssembly. His work bridges theoretical rigor with practical applications, including WasmRef-Isabelle and threads projects. Recent Trends: 2025 publications explore separation logic automation and concurrency experiments, while 2024-2023 work emphasizes specification toolchains (SpecTec), verified interpreters, and memory-safe execution techniques. Scientific Awards ACM Doctoral Dissertation Award Honorable Mention EAPLS Best Dissertation Award Advising: Supervises PhD students Qiyuan Xu and Antanas Kalkauskas. Collaborates with researchers like Philippa Gardner and Jean Pichon-Pharabod.
Prof. Peter Müller is a Full Professor at the Department of Computer Science at ETH Zurich since 2008. Previously, he held positions as Assistant Professor at ETH Zurich (2003-2008), Researcher at Microsoft Research Redmond (2007-2008), and IT project manager at Deutsche Bank. He earned his Diploma in Computer Science from Technical University of Munich (1996) and his Dr. rer. nat. from University of Hagen (2001) with a dissertation on modular verification of object-oriented programs. His research focuses on enabling correct software development through programming languages, verification methods, and tools. Key areas include formal verification for Rust and Go programs (Prusti and Gobra projects), separation logic, security protocols, and distributed systems verification. Müller's work emphasizes practical verification techniques for real-world systems, including secure router implementations and smart contract verification. Recent research trends highlight advancements in hyperproperties, modular reasoning for iterators and closures in Rust, and formal validation of verification tools. His methodologies bridge theoretical foundations with industrial applications, addressing challenges in concurrency, memory safety, and security assurance. Notable contributions include the SCION internet architecture, the Prusti verifier for Rust, and formal verification frameworks for distributed systems. His work often integrates rigorous mathematical foundations with scalable software engineering practices.
Professor David Thomas holds the position of Professor in Computer Engineering at the University of Southampton's Electronics and Computer Science Department. His research focuses on the intersection of software and hardware, particularly leveraging FPGAs for novel digital architectures and event-driven computing. He has a notable academic trajectory, having previously served as a Lecturer and Senior Lecturer at Imperial College London before joining Southampton in 2021. Dr. Thomas is actively involved in supervising PhD students and contributes to interdisciplinary research projects funded by the EPSRC, such as the SONNETS initiative exploring scalable event-triggered systems. Education: BSc in Computer Science (Imperial College London), PhD in Digital Architectures (Imperial College London). Postdoctoral roles included Research Associate and Research Fellow at Imperial's Department of Computing. Research Interests: Event-driven computing, FPGA-based systems, high-level synthesis, and high-performance computing. His work emphasizes practical implementations of theoretical models, such as custom processors and application-specific accelerators. Current projects include optimizing random number generation for FPGAs and exploring meta-programming techniques for hardware design. Advising and Grants: Supervises multiple PhD students in areas like neuromorphic computing and algorithm optimization. Active in securing funding for distributed system architectures and FPGA-based solutions. Labs/Teams: Member of the Cyber Physical Systems research group. Collaborates with interdisciplinary teams on projects like POETS (Partially Ordered Event-Triggered Systems) for large-scale parallel computing.
Manos Kapritsos is an Associate Professor in the Department of Computer Science and Engineering at the University of Michigan's College of Engineering. He leads the GLaDOS research group focusing on reliability of distributed systems through formal verification and fault-tolerant replication techniques. His research spans: Formal verification of concurrent and distributed systems Fault-tolerant replication protocols beyond client-server models Automation of verification processes for complex systems Performance verification including latency properties Reliable cryptographic code implementation Analysis of his publications reveals strong emphasis on: developing automated verification tools (Armada, Vale, IronFleet), creating novel replication protocols (Aegean), verifying performance characteristics (Performal), and improving specification reliability (IronSpec). His work consistently bridges theoretical formal methods with practical systems implementation. Awards and honors include: Jay Lepreau Best Paper Award at OSDI 2025 Jon R. and Beverly S. Holt Award for Excellence in Teaching (2022) NSF CAREER Award (2021) Distinguished Paper Award at PLDI 2020 Google Faculty Award (2017) Distinguished Paper Award at USENIX Security 2017 Grant support includes NSF FMitF grants (2020, 2023), NSF Large grant (2021), DARPA grant (2020), and Google Faculty Award (2017). He advises PhD students through the GLaDOS group, focusing on distributed systems verification. He directs the GLaDOS lab at University of Michigan, developing verification frameworks and reliable distributed systems. Current projects include automated proof generation (Basilisk) and efficient communication protocols (Scrooge).
Sean Welleck is an Assistant Professor at Carnegie Mellon University's School of Computer Science, specifically within the Language Technologies Institute (LTI). He leads the L3 Lab and serves as an advisor for the AI for Math Fund. His academic journey includes a PhD from New York University under Kyunghyun Cho and postdoctoral positions at the Allen Institute for Artificial Intelligence and the University of Washington with Yejin Choi. Dr. Welleck's educational background shows a strong foundation in computer science. He earned his PhD in Computer Science from New York University, where he worked under the mentorship of Kyunghyun Cho and Zheng Zhang. Prior to this, he completed his MSE and BSE in Computer Science from the University of Pennsylvania, demonstrating a long-standing commitment to the field. Dr. Welleck's research focuses on bridging informal and formal reasoning with AI, with particular emphasis on developing learning, inference, and evaluation algorithms for large language models. His work spans multiple cutting-edge areas including mathematical reasoning , code generation , inference algorithms , and AI reasoning agents . A significant portion of his recent work involves combining AI with formal methods for mathematics, where he has developed frameworks like Llemma (an open-source language model for mathematical reasoning) and meta-generation (for inference-time algorithms). His research is characterized by a strong theoretical foundation coupled with practical applications that push the boundaries of what AI systems can achieve in formal reasoning domains. Analysis of Dr. Welleck's recent publications reveals a clear research trajectory focused on enhancing language models' capabilities in formal reasoning and mathematical problem-solving. His work demonstrates an evolution from foundational research in neural text generation to increasingly sophisticated approaches that integrate formal methods with deep learning. Key trends include the development of inference-time algorithms that improve model performance without additional training, frameworks for mathematical reasoning that connect informal and formal proofs, and novel evaluation methodologies for language models. His publications consistently appear in top-tier conferences including NeurIPS, ICLR, ICML, and ACL, reflecting the high impact of his contributions to the field. Dr. Welleck's scientific achievements have been recognized with several prestigious awards: NAACL 2025 Best Paper Award ICLR 2025 Oral Presentation (Top 2%) ICLR 2025 Spotlight Presentation (Top 5%) NeurIPS 2021 Outstanding Paper Award (Top 0.1%) for MAUVE NVIDIA AI Labs Pioneering Research Award (2017 and 2018) As an educator and mentor, Dr. Welleck actively guides the next generation of AI researchers. He currently advises multiple PhD students including Pranjal Aggarwal, Weihua Du, Andre He, and Seungone Kim (some co-advised with other faculty), along with MS students Riyaz Ahuja, Jiewen Hu, Qinyue Tan, and Thomas Zhu, and undergraduate Tate Rowney. At CMU, he teaches advanced courses such as Neural Code Generation and Advanced NLP, and has previously taught at New York University and the University of Washington. His commitment to education extends to creating resources like the Thesis Review Podcast and developing tutorials on neural theorem proving that have been presented at major conferences. Dr. Welleck leads the L3 Lab at CMU, which focuses on the intersection of language, learning, and logic. The lab brings together students and researchers to tackle challenging problems in AI reasoning, with particular emphasis on mathematical reasoning and code generation. Recent initiatives include the development of Llemma, an open-source language model specialized for mathematical reasoning, and work on inference-time algorithms that enable language models to improve their performance through additional computation during inference rather than through additional training.
Aidong Zhang is the Thomas M. Linville Professor of Computer Science at the University of Virginia, with joint appointments in Biomedical Engineering and the School of Data Science. Her research focuses on machine learning, interpretable AI, federated learning, and generative AI applications in healthcare and bioinformatics. She holds a Ph.D. in Computer Science from Purdue University. Dr. Zhang has been honored with prestigious awards including the ACM Fellow (2017), IEEE Fellow (2009), and the 2025 Distinguished Researcher Award from UVA. Her work bridges computational methods with biomedical challenges, emphasizing fairness, robustness, and explainability in AI systems. Key research areas include federated learning frameworks, concept-based models, and large language models for scientific hypothesis generation. Dr. Zhang leads a lab offering PhD positions in machine learning, bioinformatics, and health informatics. Notable grants include NSF projects on explainable AI platforms and hardware-software co-design for extreme-scale machine learning. Education: Ph.D., Computer Science, Purdue University Affiliations: School of Engineering and Applied Science, School of Data Science Grants: NSF-funded projects on federated learning, multimodal analysis, and biomedical AI Labs/Teams: Zhang's Research Group focusing on interpretable machine learning and healthcare applications
Mark Batty is a Professor in the School of Computing at the University of Kent, specializing in formal methods for concurrent systems. His work bridges hardware-software interfaces, focusing on memory models for C/C++, OpenCL, and architectures including x86, ARM, POWER, and GPUs. As a member of the Programming Languages and Systems Research Group, he develops mathematical specifications and verification tools for real-world concurrency challenges. His research centers on empirical testing of hardware/compiler behavior, formal modeling of system components, and verification of fine-grained concurrent algorithms. Key contributions address relaxed memory semantics, transactional memory, and compositional reasoning for concurrent data structures. His work combines theoretical rigor with practical tool development to ensure correctness in complex concurrent environments. Analysis of his 2015-2025 publications reveals consistent focus on memory consistency models, formal verification of weak memory concurrency, and compiler optimizations. Dominant themes include C/C++11 standards, GPU concurrency semantics, and mechanized verification techniques. His research demonstrates strong industry relevance through collaborations with hardware vendors and contributions to language standards. Mark Batty has received significant recognition: John C. Reynolds Doctoral Dissertation Award (2015) from ACM SIGPLAN CPHC and BCS Distinguished Dissertation Award (2015) Lloyds Register Foundation and Royal Academy of Engineering Research Fellowship (2016) He actively leads major research initiatives and mentors next-generation researchers: Current Funding: EPSRC Standard Grant 'Verifiably Correct transactional memory' (2018), VeTTS Grant 'Specification and verification of C++ data structure libraries' (2018), EPSRC First Grant 'Compositional, dependency-aware C++ concurrency' (2018) PhD Recruitment: Actively seeking candidates for UKRI-funded studentship in Verified Trustworthy Software Systems Batty drives community engagement through Kent Concurrency Workshop (2016) and South of England Programming Language Seminars, fostering national collaboration in programming languages research. His leadership in organizing Royal Society discussions underscores his influence in trustworthy systems verification.
Dr. David Cock is a Senior Lecturer and Senior Researcher at ETH Zürich's Department of Computer Science, affiliated with the Systems Group. He holds a PhD from UNSW (2014) and a B.Sc. (hons) from UNSW (2004). His research focuses on formal verification, trustworthy systems, and hardware-software co-design, with notable contributions to projects like Enzian (a CPU/FPGA platform) and seL4 (formally verified kernel). He teaches Advanced Operating Systems and Informal Methods courses. Key achievements include the ACM Software System Award (2022) for seL4 and leadership in projects addressing hardware complexity and security. Research interests include formal methods for hardware modeling (Sockeye project), runtime verification, and mitigating timing channels. His work bridges theoretical foundations with practical systems, emphasizing secure and reliable computing platforms. Projects like Trustworthy BMC aim to enhance baseboard management systems' assurance. Collaborations span academia and industry, with open-source contributions to hardware designs and formal tools. Publications span formal verification, hardware modeling, and secure systems, with recent focus on heterogeneous computing and declarative hardware specifications. Teaching emphasizes practical formal techniques and OS design, leveraging real-world hardware (e.g., Barrelfish). His lab, the Systems Group, explores cutting-edge challenges in systems software and architecture.
Shuvendu K. Lahiri is a researcher at Microsoft Research, focusing on formal verification, program synthesis, and software testing. His work bridges artificial intelligence with formal methods, particularly in blockchain security and automated code generation. 2025 : Published LLM-Vectorizer (verified loop vectorizer) and neural synthesis for SMT-assisted proof-oriented programming 2024 : Explored LLM-based test-driven code generation and natural precondition inference 2023 : Developed resource management specifications and contributed to test generation with pre-trained models 2022 : Advanced Solidity type systems and merge conflict resolution using language models His research combines large language models with formal verification tools to improve software correctness. He actively contributes to conferences like ICSE, PLDI, and ISSTA as author and committee member.
