Stephen W. Keckler is an Adjunct Professor at the Department of Computer Science , The University of Texas at Austin , and serves as Vice President of Architecture Research at NVIDIA . He is an ACM Fellow , IEEE Fellow , and Sloan Foundation Research Fellow . Education: BS in Electrical Engineering, Stanford University (1990) SM in Computer Science, Massachusetts Institute of Technology (1992) PhD in Computer Science, MIT (1998) Research Interests focus on computer architecture for deep learning , GPU computing , and energy-efficient systems . His work explores memory compression , network-on-chip designs , and heterogeneous computing . Publication Trends highlight advancements in deep learning accelerators , GPU memory systems , and energy-efficient architectures . Notable themes include sparsity exploitation , multi-chip modules , and fault-tolerant GPU pipelines . Scientific Recognition : ACM Fellow IEEE Fellow Sloan Foundation Research Fellow Best Paper Awards at ASPLOS 2009 and ISPASS 2011 Laboratory Affiliations : Computer Architecture and Technology Laboratory (CART) TRIPS Project (Tera-Op Reliable Intelligently adaptive Processing System) NVIDIA Research
Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.
Ayse Coskun is a Professor in the Electrical and Computer Engineering Department at Boston University's College of Engineering. She serves as Director of the Center for Information and Systems Engineering (CISE) and as interim Associate Dean for Research and Faculty Development. Her research focuses on the intersection of computer systems, energy efficiency, and AI. Dr. Coskun received her PhD from the University of California, San Diego in 2009. Prior to joining academia, she worked at Sun Microsystems (now Oracle). Her research spans energy-efficient computing, cloud computing, high performance computing, computer architecture, and embedded systems, with recent work focusing on AI's impact on data center energy demands. Her publication record shows consistent innovation across multiple domains, with recent work emphasizing AI applications for improving cloud security (through frameworks like DeltaSherlock and Praxi) and transforming data centers into grid-responsive assets (Emerald AI project). Her research bridges theoretical advances with practical applications, resulting in tools adopted by industry partners including IBM. IBM Faculty Award (2020) Ernest S. Kuh Early Career Award (2017) NSF CAREER Award (2012-2017) Multiple best paper and artifact awards at top conferences As an educator, Dr. Coskun teaches courses including EC327 Introduction to Software Engineering, EC535 Introduction to Embedded Systems, and EC713 Advanced Computing Systems and Architecture. She has advised numerous PhD students including Mert Toslali, Anthony Byrne, and Burak Aksar. Her lab maintains strong industry partnerships with IBM, Intel, AMD, and Oracle, and collaborates with academic institutions worldwide including Brown University, MIT, EPFL, and CEA-Tech in France. Dr. Coskun leads the Coskun Lab, which secured a $500K grant from Sandia National Labs for AI-based analytics in high performance computing systems, demonstrating the practical impact of her research on critical computing infrastructure.
Aviral Shrivastava is a Professor at the School of Computing and Augmented Intelligence, Arizona State University, leading the Make Programming Simple Lab. He holds a Ph.D. and M.S. from the University of California-Irvine (2006, 2002) and a Bachelor’s from IIT Delhi (1999). His research focuses on making programming simple for embedded and cyber-physical systems, with a particular interest in manycore and accelerated computing, software for CPS, and resilient/fault-tolerant computing. He has co-authored over 120 publications in top venues like DAC, ESWEEK, and ACM TECS, with more than 3000 citations and 5 granted patents. His work has been recognized with multiple awards, including the 2010 NSF CAREER award and best paper nominations. Research Areas: Embedded and Cyber-Physical Systems Compiler Design for Modern Architectures Resilient and Fault-Tolerant Computing Scientific Awards: 2010 NSF CAREER award DAC 2017 Best Paper Award Candidate VLSI 2016 Best Student Paper Award LCTES 2010 Second Highest Ranked Paper ASPDAC 2008 Best Paper Candidate Advising & Grants: He has mentored 9 Ph.D. and over 20 Masters students. His research has been funded by NSF, DOE, NIST, SFAZ, and industry partners, totaling $3.5M. He teaches courses on computer organization, architecture, and embedded systems, with student evaluations averaging over 4/5. He also serves as General Chair of Embedded Systems Week (ESWEEK) and holds editorial roles in IEEE ESL, ACM TCPS, and ACM TECS.
Dr. Ava Hedayatipour is an Assistant Professor of Electrical Engineering at California State University at Long Beach (CSULB), where she joined in Fall 2020. She holds a Ph.D. from the University of Tennessee, Knoxville (2020), and degrees from Iran University of Science and Technology (B.S., 2012) and Shahid Rajaee Teacher Training University (M.S., 2015). Her research focuses on analog/mixed-signal circuit design, bio-implantable devices, low-power systems, and hardware security. Notable contributions include a first-of-its-kind integrated secure multimodal sensor and a flexible paper electrode for remote electrochemical experiments. Education: Ph.D., Electrical Engineering, University of Tennessee, Knoxville, 2020 M.S., Electrical Engineering, Shahid Rajaee Teacher Training University, Iran, 2015 B.S., Electrical Engineering, Iran University of Science and Technology, 2012 Research Interests: Analog and mixed-signal circuit design Biomedical devices and lab-on-chip applications Low-power, low-noise microelectronics Hardware security for IoT and biomedical sensors Flexible electrodes for wearable systems Awards: University of Tennessee Fellowship Award (2019) Outstanding Teaching Assistant Award (2018) BEST PAPER AWARD at IEEE DCAS 2025 2nd Place Winner at IEEE BIOCAS 2023 Innovation Challenge Advising & Grants: Lead CSULB LEAP program project on medical imaging braces Funded NSF project on chaotic analog security (2018–present) Collaborated with industry partners like Applied Medical and Synaptics Labs & Teams: Next Generation Wearable Lab at CSULB Focus on sensor design, hardware security, and biomedical applications
Patrick H. Madden is an Associate Professor and Director of the MS Information Systems program at the School of Computing, Binghamton University. His research focuses on combinatorial optimization, VLSI physical design automation, and algorithmic solutions for NP-Hard problems. He is also involved in interdisciplinary work in cryptography and biology-related optimization. Education: BS and MS from New Mexico Institute of Mining and Technology PhD from University of California, Los Angeles (UCLA) Professional Roles: Chair of ACM/SIGDA (Design Automation Special Interest Group) Chair of Design Automation Conference (DAC) Sponsors Committee Advisor to Binghamton ACM Student Chapter Coach for ICPC Programming Contest Teams Member of Watson School Graduation Committee Research Contributions: Leads the Optimality Research Group, developing optimization algorithms for VLSI CAD and medical software applications. Notable contributions include the Feng Shui placement tool and medical reference apps for iOS/Android platforms. Awards: SUNY Chancellor's Award for Excellence in Professional Service (2015) Grants & Collaborations: Collaborates with Prof. Monte McCollum (Cinema Department) on hybrid cinema projects and Dr. Joshua Steinberg (Physician) on medical software. Active in ACM committees and EDA conferences (DAC, ICCAD, ISPD). Labs/Teams: Directs the Optimality Research Group and oversees medical software collaborations through CS441/580 projects.
David Zhigang Pan is a Professor in the Department of Electrical & Computer Engineering at The University of Texas at Austin. He also holds the Silicon Laboratories Endowed Chair. Prior to joining UT Austin, he was a Research Staff Member at IBM T. J. Watson Research Center from 2000 to 2003. His academic journey began with a B.S. from Peking University, followed by M.S. and Ph.D. degrees from UCLA. Research Areas: Electronic Design Automation (EDA), Machine Learning Hardware, FPGA Prototyping, Optical Computing, Hardware Security, and CAD for Emerging Technologies Academic Timeline: Assistant Professor (2003-2008), Associate Professor (2008-2013), Full Professor (2013-present) His research focuses on design automation for mixed-signal circuits , GPU-accelerated EDA tools , and hardware-software co-design for AI . Recent work explores FFT-based optical neural networks and deobfuscation techniques for integrated circuits , reflecting his interdisciplinary approach at the intersection of machine learning , computer architecture , and semiconductor manufacturing . Key publication trends reveal expertise in: VLSI design , lithography optimization , and deep learning applications for EDA tools. His work has been recognized with multiple Best Paper Awards at top conferences including DAC , ASP-DAC , and HOST . Awards: IEEE Fellow (2014), SPIE Fellow (2017), ACM SRC Graduate Category Honors for students Patents: 8 U.S. Patents in electronic design and hardware optimization Prof. Pan has mentored 40 PhDs and postdocs who now hold key positions in academia and industry. He leads research initiatives involving GPU acceleration frameworks and optical computing architectures . His lab focuses on vertical integration of architecture, CAD tools, and fabrication technologies for next-generation hardware solutions.
Jeff Zhang is an Assistant Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University. He joined ASU in January 2023 after completing a postdoctoral fellowship at Harvard University. His research spans deep learning, computer architecture, embedded systems, and EDA, with particular emphasis on energy-efficient and fault-tolerant design for AI/ML systems and hardware accelerators. Education: Ph.D., New York University M.Eng., B.Eng., Hunan University Dr. Zhang's research bridges theoretical machine learning with practical hardware implementation, developing novel architectures that optimize performance, power consumption, and reliability. He has pioneered approaches for hardware acceleration of large language models, efficient sparse matrix operations, and novel memory technologies for AI workloads. His work has received multiple awards including IEEE Top Picks in Test and Reliability (2023) and IEEE Micro Best Paper Award (2022). His recent publications demonstrate a strong trend toward heterogeneous computing, with significant work in chiplet-based AI accelerators, photonic computing for AI, and 2.5D/3D integration techniques. The research spans from high-level compiler frameworks to circuit-level innovations, with a consistent theme of co-designing algorithms and hardware for optimal AI performance. His work on the SODA toolchain has been particularly influential in bridging Python to silicon. Scientific Awards: IEEE Top Picks in Test and Reliability, IEEE ITC, 2023 Best Paper Award, IEEE Micro, 2022 Best Paper Award Candidate, IEEE DATE, 2022 Best Presentation Award Nomination, ACM SIGDA DATE PhD Forum, 2020 Best Paper Award Nomination, IEEE VLSI Test Symposium, 2018 Ernst Weber Ph.D. Fellowship, New York University, 2015, 2016 Dr. Zhang actively mentors a diverse group of graduate and undergraduate students, with several alumni now working at leading technology companies including Apple, TSMC, and Ansys. His research is supported by prestigious grants from NSF, Sandia National Labs, and industry partners. He serves on technical program committees of numerous top conferences and has organized special sessions on emerging topics like Gen AI for Chip Design and LLM-Aided Design. Dr. Zhang leads a vibrant research group that collaborates extensively with industry partners and national laboratories. Current projects focus on next-generation AI hardware, including chiplet-based systems, photonic accelerators, and novel memory technologies for large language models. His group has developed several open-source tools and frameworks, including the SODA toolchain for bridging Python to silicon.
Kyprianos Papadimitriou is a Researcher at the Microprocessor and Hardware Laboratory within the School of Electrical and Computer Engineering at the Technical University of Crete . He holds a PhD in Electronic and Computer Engineering (2012) and has been involved in teaching laboratory courses such as Logic Design , Computer Architecture , and VLSI/ASIC Circuit Design . Research Areas : His work spans Reconfigurable Systems , Hardware Design , Computer Architecture , RFID Systems , and Real-Time Systems . He has developed innovative approaches in FPGA-based dynamic reconfiguration, MPSoC security, and 3D stereo vision for surveillance. Key Trends : Runtime reconfiguration for FPGAs Security frameworks for NoC-based MPSoCs Low-cost embedded vision systems Optimization of reconfiguration overhead Hardware task scheduling methodologies Genetic algorithm implementations on FPGAs Scientific Contributions : 1 USA patent (2005) Co-author of VLSI-SoC 2013 paper nominated for 1st Prize Active member of scientific committees (FPL, ReConFig) Peer reviewer for IEEE, Elsevier, and Springer journals Session chair at IEEE CNS and HPCC conferences Grants & Projects : Participated in competitive European and national programs, serving as scientific manager, coordinator, and technical coordinator. Developed spin-off company (2003-2005) to commercialize master's thesis research. Laboratory & Teaching : Affiliated with the Microprocessor and Hardware Laboratory , focusing on practical training in digital systems, processor-based systems, and VLSI design.
Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.
Mark R. Greenstreet is a Professor in the Department of Computer Science at the University of British Columbia (UBC). He holds a BSc from Caltech (1981), MA (1988), and PhD (1993) in Computer Science from Princeton University. His primary research focuses on formal verification of analog and mixed-signal (AMS) circuits, VLSI design, and hybrid systems. Notable contributions include the STARI signaling technique, tools like Coho for reachability analysis, and PReach for parallel model checking. He has advised numerous graduate students and collaborators, including Brad Bingham, Chao Yan, and Yan Peng. His work has been recognized with a Best Paper Award at the ASYNC Symposium. Supported by NSERC, Intel, and Oracle, his research bridges theoretical foundations and practical challenges in circuit design and verification. He teaches courses on formal methods, computer architecture, and automata theory at UBC.
Dr. Jason D. Bakos is a Professor in the Department of Computer Science and Engineering at the University of South Carolina's Molinaroli College of Engineering and Computing. His research focuses on high-performance domain-specific architectures, including reconfigurable computing, embedded systems, and machine learning acceleration. He has held academic positions since 2005, progressing from Assistant to Associate Professor before becoming a full Professor in 2017. Education : Ph.D., Computer Science, University of Pittsburgh (2005) B.S., Computer Science, Youngstown State University (1999) Research Interests : Dr. Bakos specializes in computer architecture at multiple levels (circuit, micro-architectural, and system) with a focus on VLSI design, reconfigurable computing, high-performance computing, and applications in embedded systems. His recent work includes FPGA acceleration of machine learning algorithms, structural health monitoring systems, and real-time signal processing. Awards : 2018 Teaching Award in Computer Science and Engineering 2009 NSF CAREER Award Multiple design competition awards for innovative chip and circuit designs Grants & Funding : He leads and co-leads projects funded by NSF, Savannah River National Laboratory, and industry partners like Texas Instruments. Recent grants focus on edge computing for real-time machine learning, FPGA-based accelerators, and corrosion analysis of nuclear materials. Labs & Teams : His research group collaborates on projects involving embedded systems, FPGA design, and interdisciplinary applications in structural engineering and bioinformatics. He advises a dynamic team of graduate students and post-doctoral researchers.
Tsun-Ming Tseng is a Professor and principal investigator at the Chair of Electronic Design Automation at the Technical University of Munich (TUM). He leads the Emerging Technology Group and oversees multiple DFG/BMBF-funded research projects in the areas of microfluidic large-scale integration, optical network-on-chip design, and novel microfabrication techniques. Dr. Tseng's research focuses on design automation for emerging technologies, with particular expertise in three main areas: microfluidic large-scale integration, optical network-on-chip systems, and novel microfabrication processes. His work bridges the gap between electronic design automation and cutting-edge applications in bioengineering, photonics, and advanced manufacturing. His research group develops sophisticated algorithms and tools for optimizing design, reliability, and performance in these emerging domains. Analysis of Dr. Tseng's recent publications reveals a strong focus on practical implementation challenges in emerging technologies. His work spans both theoretical algorithm development and practical system implementation, with particular emphasis on reliability, performance optimization, and manufacturing considerations. The research shows increasing integration between different technology domains, particularly the convergence of microfluidics, optical networking, and electronic design automation. Dr. Tseng has been awarded multiple significant research grants including: "DE-TW-CloudWRONoC" (BMBF-NSTC project, PI, 2025-2028, EUR 797.7K) "DE-TW-PI3D" (BMBF-NSTC project, PI, 2024-2027, EUR 391.6K) "Physical Design for Microfluidic Large-Scale Integration" (DFG research grant, PI, 2024-2026, EUR 331.9K) Multiple other DFG and industrial projects totaling over EUR 3 million in funding He has successfully supervised numerous doctoral researchers and postdoctoral fellows, with current group members including Jiahui Peng, Debraj Kundu, Liaoyuan Cheng, and several others. Dr. Tseng leads the Emerging Technology Group at TUM, which focuses on developing design automation methodologies for next-generation technologies. The group maintains strong collaborations with international institutions, including partnerships with researchers in Taiwan and Hong Kong. The team operates state-of-the-art facilities for research in microfluidics, optical networking, and advanced microfabrication techniques.
Mark C. Johnson is a Senior Lecturer at the Elmore Family School of Electrical and Computer Engineering at Purdue University, West Lafayette. He serves as Director of Instructional Laboratories and Associate Director for Design - Semiconductor Degree Program , overseeing laboratory infrastructure, CAD software administration, and curriculum development for courses like ECE337, ECE437, and ECE364. Education: Ph.D. in Electrical Engineering (1998), Purdue University M.S. in Electrical Engineering (1991), Wichita State University B.S. in Electrical Engineering (1983), Purdue University - Calumet His research focuses on electrical and computer engineering laboratory curriculum innovation , digital systems design , and CAD for VLSI . Over 15 recent publications highlight his work in SoC prototyping , low-power circuit design , and educational technology , spanning projects like FPGA filter optimization, dual-core processor experiments, and active learning strategies. Leadership Roles: Proceedings Chair (2003), MSE Program Chair (2005), MSE General Chair (2007), MSE Steering Committee Member, MSE & European Workshop on Microelectronics Education Chair, ECE Instructional Innovation Group (2004-2012) Secretary/Webmaster, ASEE Illinois/Indiana Section (2002-2011) He directs the ECE437 Computer Architecture Prototyping Lab and System on Chip Extension Technologies (SoCET) team , and co-advises the STARS semiconductor readiness program. Outside academia, he is an organist at Faith Presbyterian Church and composes keyboard music.
Professor Serdar Özoğuz is a full faculty member at the Department of Electronics and Communication Engineering , Istanbul Technical University . Holding a Ph.D. from ITU (2000) and a M.Sc. from ITU (1993) , he has taught courses like Active Network Synthesis , Basics of Electrical Circuits , and Scientific Research Ethics since 2014. His research focuses on Active RC filters Nonlinear electronic circuits Analog integrated circuit design Network synthesis . His recent publications emphasize machine learning applications in RF/microwave design , quantum computing for CAD tools , and emerging memory devices . The department's Devreler ve Sistemler Laboratuvarı Çok Geniş Ölçekli Tümdevre (VLSI) Tasarımı Laboratuvarı likely support his work. Despite no explicit awards listed, his 15+ recent articles in high-impact journals underscore his technical contributions.
