Luciano Lavagno is a Full Professor at the Department of Electronics and Telecommunications, Polytechnic University of Turin, with over two decades of academic and research contributions. His work bridges hardware acceleration, low-power electronics, and intelligent system design. Research Focus: Hardware-accelerated machine learning, high-level synthesis (HLS) for FPGA/ASIC, heterogeneous CPU/GPU/FPGA platforms Key Projects: SPACE (predictable acceleration), REBECCA (secure AI acceleration), HPC-National Center (quantum computing), and oral history preservation via "Ti racconto una storia" initiative His recent publications analyze CNN inference optimization, subgraph isomorphism, and superword-level parallelism exploitation. Lavagno supervises multiple PhD students working on FPGA acceleration, neural network hardware, and embedded systems. As Principal Investigator for national and EU-funded projects (PRIN, JTI-ECSEL, PNRR), he drives advancements in sustainable computing infrastructure. His patented technologies include MIx&Latch timing methodology, capacitive sensing innovations, and 5G acceleration frameworks.
Kimia Zamiri Azar serves as an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Central Florida, focusing on hardware security and verification methodologies. Her research bridges theoretical formal methods with practical security implementations in semiconductor design and testing. Her educational background includes: Ph.D. in Electrical and Computer Engineering, George Mason University (2021) Postdoctoral Research, University of Florida Dr. Azar's research spans hardware security with emphasis on system-level verification, VLSI design-for-trust, and advanced IC testing. She pioneers techniques in logic locking, secure heterogeneous integration, and IC supply chain security, developing frameworks for authenticated encryption in Systems-in-Package and runtime security monitoring. Her work integrates formal verification with innovative testing methodologies to address hardware trust challenges across the semiconductor lifecycle. Analysis of her recent publications reveals two dominant trends: (1) Application of large language models (LLMs) to hardware design tasks including high-level synthesis code generation and RTL optimization, and (2) Advancement of secure heterogeneous integration techniques for System-in-Package architectures with focus on counterfeit prevention and split-test security protocols. These directions address critical gaps in hardware trustworthiness amid increasingly complex semiconductor supply chains. Her scientific contributions have earned significant recognition: Best Paper Award at ICCAD 2019 Best Paper Award at ISVLSI 2020 Best Paper Award at ICCAD 2020 Best Paper Award at IEEE DCAS 2020 Best Paper Award at HOST 2022 Best Paper Award at DATE 2023 Dr. Azar secures substantial research funding from premier agencies including NSF, SRC, DARPA, AFRL, DoD (NG), and Microsemi. Her grants support projects spanning hardware security validation frameworks, secure heterogeneous integration, and AI-augmented verification methodologies. She actively mentors students in her research group, guiding publications in top venues like IEEE D&T, IEEE TC, and DAC while fostering industry-academic collaborations. Her work directly impacts semiconductor security standards through patented innovations and open-source verification tools. As an active IEEE and ACM member, she contributes to community advancement through conference organization (HOST, DATE), journal editorial roles, and workshop leadership on hardware security standards. Her research group collaborates with semiconductor industry leaders to translate theoretical security frameworks into practical design-for-trust methodologies for next-generation integrated circuits.
Dr. Jason D. Bakos is a Professor in the Department of Computer Science and Engineering at the University of South Carolina's Molinaroli College of Engineering and Computing. His research focuses on high-performance domain-specific architectures, including reconfigurable computing, embedded systems, and machine learning acceleration. He has held academic positions since 2005, progressing from Assistant to Associate Professor before becoming a full Professor in 2017. Education : Ph.D., Computer Science, University of Pittsburgh (2005) B.S., Computer Science, Youngstown State University (1999) Research Interests : Dr. Bakos specializes in computer architecture at multiple levels (circuit, micro-architectural, and system) with a focus on VLSI design, reconfigurable computing, high-performance computing, and applications in embedded systems. His recent work includes FPGA acceleration of machine learning algorithms, structural health monitoring systems, and real-time signal processing. Awards : 2018 Teaching Award in Computer Science and Engineering 2009 NSF CAREER Award Multiple design competition awards for innovative chip and circuit designs Grants & Funding : He leads and co-leads projects funded by NSF, Savannah River National Laboratory, and industry partners like Texas Instruments. Recent grants focus on edge computing for real-time machine learning, FPGA-based accelerators, and corrosion analysis of nuclear materials. Labs & Teams : His research group collaborates on projects involving embedded systems, FPGA design, and interdisciplinary applications in structural engineering and bioinformatics. He advises a dynamic team of graduate students and post-doctoral researchers.
Maurizio Martina is a Full Professor at the Department of Electronics and Telecommunications (DET) of Politecnico di Torino. He is a member of the Interdepartmental Center PEIC - Power Electronics Innovation Center and serves as an Associate Editor for the IEEE Transactions on Circuits and Systems I (2018-2023). His research focuses include: Digital circuits and signal processing Machine learning hardware architectures RISC-V extensions and post-quantum cryptography VLSI design for edge computing and IoT Recent publications emphasize cryptographic hardware implementations (CHIMERA, Keccak co-processors), RISC-V integration methodologies, and privacy-preserving neural network frameworks. His work spans VLSI architectures for video processing, bio-inspired electronics, and error correcting codes, with applications in cybersecurity, robotics, and biomedical systems. Scientific Recognition : Premio Nazionale Innovazione (2013) Premio dei Premi (2014) He supervises 12 PhD students across cycles 35-40 in Electrical, Electronics and Communications Engineering, including: Valeria Piscopo (2024-in progress) Alessandra Dolmeta (2022-in progress) Luigi Giuffrida (2022-in progress) Walid Walid (2019-2023) As part of the VLSILAB Group , his research explores hardware accelerators for machine learning, post-quantum cryptography on RISC-V, and bio-inspired embedded systems. Teaching activities include courses on Integrated Systems Architecture and Hardware & Wireless Security at Politecnico di Torino and Università di Pavia.
Tsun-Ming Tseng is a Professor and principal investigator at the Chair of Electronic Design Automation at the Technical University of Munich (TUM). He leads the Emerging Technology Group and oversees multiple DFG/BMBF-funded research projects in the areas of microfluidic large-scale integration, optical network-on-chip design, and novel microfabrication techniques. Dr. Tseng's research focuses on design automation for emerging technologies, with particular expertise in three main areas: microfluidic large-scale integration, optical network-on-chip systems, and novel microfabrication processes. His work bridges the gap between electronic design automation and cutting-edge applications in bioengineering, photonics, and advanced manufacturing. His research group develops sophisticated algorithms and tools for optimizing design, reliability, and performance in these emerging domains. Analysis of Dr. Tseng's recent publications reveals a strong focus on practical implementation challenges in emerging technologies. His work spans both theoretical algorithm development and practical system implementation, with particular emphasis on reliability, performance optimization, and manufacturing considerations. The research shows increasing integration between different technology domains, particularly the convergence of microfluidics, optical networking, and electronic design automation. Dr. Tseng has been awarded multiple significant research grants including: "DE-TW-CloudWRONoC" (BMBF-NSTC project, PI, 2025-2028, EUR 797.7K) "DE-TW-PI3D" (BMBF-NSTC project, PI, 2024-2027, EUR 391.6K) "Physical Design for Microfluidic Large-Scale Integration" (DFG research grant, PI, 2024-2026, EUR 331.9K) Multiple other DFG and industrial projects totaling over EUR 3 million in funding He has successfully supervised numerous doctoral researchers and postdoctoral fellows, with current group members including Jiahui Peng, Debraj Kundu, Liaoyuan Cheng, and several others. Dr. Tseng leads the Emerging Technology Group at TUM, which focuses on developing design automation methodologies for next-generation technologies. The group maintains strong collaborations with international institutions, including partnerships with researchers in Taiwan and Hong Kong. The team operates state-of-the-art facilities for research in microfluidics, optical networking, and advanced microfabrication techniques.
Zhidan Zheng is a researcher at the Technical University of Munich (TUM), working within the Chair of Electronic Design Automation led by Prof. Ulf Schlichtmann. His office is located in room 0509.05.911 at Arcisstr. 21, 80333 Munich, with direct contact available via email zhidan.zheng@tum.de and phone +49 (89) 289 - 23692. Zheng holds a Master of Science degree as indicated by his academic title M.Sc. and has been actively contributing to the field of optical interconnects and network-on-chip design. Zheng's research focuses on wavelength-routed optical networks-on-chip, with particular expertise in network topology optimization, fault tolerance mechanisms, waveguide routing algorithms, and bandwidth allocation strategies. His work addresses critical challenges in photonic integrated circuit design, including thermal variation effects, crosstalk mitigation, and lifetime extension for communication-intensive systems. Zheng has developed several innovative methodologies including ToPro+ for topology projection, LightR for fault-tolerant architectures, and WROXIM for network-level simulation. Analysis of Zheng's publication trends from 2021-2025 reveals a consistent focus on practical implementation challenges of optical networks-on-chip. His research has evolved from foundational topology design (Light, 2021) to increasingly sophisticated solutions addressing reliability (LightR, 2023) and comprehensive system integration (ToPro+, 2025). The work demonstrates strong collaboration with researchers including Mengchu Li, Tsun-Ming Tseng, and Ulf Schlichtmann across multiple high-impact venues including DAC, DATE, ICCAD, and ASP-DAC. Zheng actively contributes to the Electronic Design Automation research group at TUM, participating in projects related to analog EDA, emerging technologies, and optical networks. His research is situated within TUM's broader initiatives in photonic integration and high-performance computing architectures, working closely with Prof. Schlichtmann's team on funded projects in the optical NoC domain.
Giovanni De Micheli is a Professor of Electrical Engineering and Computer Science at EPF Lausanne, Switzerland. He also serves as Director of the Integrated Systems Centre and the Institute of Electrical Engineering at EPFL, and chairs the Scientific Committee of CSEM in Neuchatel. Previously, he held academic roles at Stanford University for 18 years, including Full Professor, Associate Professor, and Assistant Professor in the Department of Electrical Engineering. His research spans synthesis of digital circuits, hardware/software co-design, low-power design, and Networks on Chip (NoC) technology. 2003: IEEE Emanuel Piore Award 2000: Golden Jubilee Medal of the IEEE CAS Society 2000: ACM Fellow 1994: IEEE Fellow 1990: IEEE/CS Distinguished Service Award 1988: NSF Presidential Young Investigator Award His seminal contributions include pioneering C-based synthesis and Boolean matching algorithms for digital circuits, foundational work in dynamic power management using stochastic control, and the development of Network-on-Chip (NoC) technology. His publications, such as "Networks on Chips: A New SoC Paradigm" and "Dynamic Power Management for Portable Systems" , have shaped modern SoC design practices. With over 400 technical articles, 9 books, and an H-index of 56, his work remains highly influential.
Anuj Pathania serves as an Assistant Professor in the Parallel Computing Systems (PCS) group within the Informatics Institute at the University of Amsterdam's Faculty of Science. His research pioneers sustainable computing systems operating under severe power, thermal, and reliability constraints, with significant contributions to energy-efficient hardware design and embedded systems. Education: PhD in Computer Science (2018), Karlsruhe Institute of Technology MSc in Computer Science (2012), National University of Singapore B.Tech in Computer Science (2009), Maharaja Agrasen Institute of Technology Pathania's research centers on low-power design and sustainable systems for constrained environments, with particular expertise in thermal management of 3D-stacked architectures and energy-efficient machine learning inference . His work bridges electronic design automation with real-world reliability challenges, developing novel power budgeting techniques like T-TSP that incorporate transient temperature effects ignored by conventional methods. Current projects include EU-funded initiatives on energy labeling for digital services, addressing ecological impacts through technological, behavioral, and legal frameworks. His publication trajectory reveals a strategic evolution toward zero-waste computing , with recent work (2023-2025) focusing on hardware-software co-design for edge AI, energy modeling across computing continua, and parameter-efficient neural adaptation. Key themes include thermal-aware scheduling for S-NUCA many-cores, cooperative processor utilization in heterogeneous systems, and sustainability metrics for digital services. Scientific Recognition: Best Paper Award Nomination at IEEE Computer Society Annual Symposium on VLSI 2023 for 3D-TTP power budgeting technique Pathania actively mentors 4 PhD students (Ehsan Aghapour, Saeedeh Baneshi, Sudam Wasala, Yixian Shen) and has successfully supervised 5 Master's theses (including Cum Laude defenses by Joris op ten Berg and Jurre Wolff). His research is supported by major grants including Energy Labels for Ecologically Sustainable Digital Services (2023-2024) and Towards Zero-Waste Computing (2021-2025), developing simulation frameworks like HotSniper and CoMeT for thermal analysis. The PCS group maintains strong industry collaborations with ARM and NVIDIA, particularly through tools like ARM-CO-UP for heterogeneous processor utilization.
Giovanna Turvani is an Associate Professor at the Department of Electronics and Telecommunications (DET) at Politecnico di Torino, with affiliations in both the College of Electronic, Telecommunications and Physics Engineering and the College of Computer, Film, and Mechatronics Engineering. Scientific Branch: IINF-01/A - Electronics ERC Sectors: PE7_4, PE7_11, PE6_1, PE6_14, PE7_3 SDG Goals: Quality Education, Gender Equality, Affordable Energy, Industry Innovation Her research focuses on advanced electronics and quantum technologies, including: Logic-in-memory computing Quantum computing architectures Microwave imaging for medical and agricultural applications CAD tools for emerging nanotechnologies Embedded systems for bee health monitoring IoT solutions for bio-waste valorization Publications show strong expertise in quantum computing, nanocomputing, and microwave imaging, with recent trends emphasizing quantum optimization frameworks, in-memory architectures, and IoT-based agricultural technologies. She supervises PhD students in areas like quantum machine learning algorithms, predictive on-board systems, and quantum hardware design. Collaborations span multiple disciplines, including medical device development and agricultural electronics. Patents include innovations in microwave imaging, racetrack memory logic functions, and in-memory computing devices.
Professor Forrest Brewer is a faculty member in the Department of Electrical and Computer Engineering at the University of California, Santa Barbara (UCSB), affiliated with the College of Engineering. His research spans VLSI design, computer-aided design tools, and low-power computing, with a focus on unconventional engineering solutions. Education: PhD in Computer Science, University of Illinois BS in Physics (with honors), California Institute of Technology His work includes CMOS pulse-gate asynchronous logic for high-performance systems, sigma-delta modulation for signal processing, and formal verification strategies for asynchronous circuits. Applications range from radiation-hardened communication links for the Large Hadron Collider (LHC) to spiking neural networks for low-power computing in LIDAR/RADAR systems. Affiliations: California Nanosystems Institute Allosphere Steering Committee (Media Technology) With over 100 publications and 40 years of systems design experience, Brewer has contributed to defense programs, founded UCSB's Computer Engineering program, and served as Intel Faculty Fellow (1997). His lab, the Systems Synthesis Lab, explores collective dynamics and high-resolution, low-latency computation.
Stefan Hougardy is a Professor at the Research Institute for Discrete Mathematics, part of the Mathematisch-Naturwissenschaftliche Fakultät at the University of Bonn. He is actively engaged in research and teaching, with a focus on discrete mathematics and combinatorial optimization. He contributes to academic governance through roles in examination boards, teaching mentoring, and faculty committees. Stefan Hougardy's research lies at the intersection of theoretical computer science and practical optimization. His primary interests include approximation algorithms, the Traveling Salesman Problem (TSP), Steiner trees, graph theory, and VLSI design automation. He develops efficient algorithms for NP-hard problems and analyzes their theoretical performance guarantees. His work often bridges theory and application, particularly in electronic design automation and mathematical programming. His recent publications demonstrate a strong focus on the complexity and approximation of combinatorial optimization problems. Key themes include the analysis of local search heuristics like k-opt for TSP, edge elimination techniques, fast matching algorithms, and optimal legalization in chip design. His work combines rigorous theoretical analysis with practical implementation and computational experiments. MPC 'Outstanding Paper of the Year' Award 2024 Stefan Hougardy supervises graduate students and leads seminars on discrete mathematics and optimization. He is involved in the Bonn International Graduate School of Mathematics and the Hausdorff Center for Mathematics, contributing to doctoral education and mentoring. While specific grant details are not listed, his sustained research output and leadership roles suggest active funding support. He also contributes to curriculum development and academic quality assurance through various institutional committees. He is affiliated with the Research Institute for Discrete Mathematics at the University of Bonn, a leading center for combinatorial optimization and algorithmic research. The institute is closely linked with the Hausdorff Center for Mathematics, fostering collaboration in discrete and applied mathematics.
Dr Graeme Bragg is a Senior Teaching Fellow at the University of Southampton within the Department of Electronics and Computer Science . His work spans teaching, research, and technical development with a focus on event-driven computing, bioinformatics, and computational modeling. He actively supervises PhD students and collaborates on interdisciplinary projects. Research Interests: Parallel computing, event-driven systems, genotype imputation, Petri net simulations, subglacial hydrology modeling Teaching: Specializes in hardware description languages and computational methods for engineering students Technical Expertise: RISC-V architecture, FPGA acceleration, bespoke compute fabric development His recent publications demonstrate expertise in applying event-driven computing to diverse problems including: 2025: Automated marking systems for SystemVerilog labs 2025: Seasonal dynamics in subglacial hydrology 2023: Genotype imputation using custom hardware 2022: Optimization algorithms and graph analysis Current research explores: Custom RISC-V FPGA clusters for bioinformatics Event-triggered systems for scientific simulations Parallel computing solutions for molecular modeling Contact: gmb@ecs.soton.ac.uk | +44 23 8059 2784
Alberto Macii is a Full Professor in the Department of Control and Computer Science (DAUIN) at Polytechnic University of Turin. He is also a member of the Interdepartmental Center IAM@PoliTo - Integrated Additive Manufacturing and serves on two colleges: College of Computer, Film and Mechatronics Engineering and College of Mechanical, Aerospace and Automotive Engineering. His research interests include: Digital circuits and systems Electronic systems, modeling, and simulation Energy-efficient circuits and systems Energy management and battery systems Embedded systems and cyber-physical systems Low energy building technologies His work aligns with several Sustainable Development Goals including affordable and clean energy (Goal 7), industry innovation and infrastructure (Goal 9), and sustainable cities and communities (Goal 11). His publication record shows a consistent focus on energy efficiency in electronic systems spanning over two decades, with particular emphasis on battery modeling and power management. Recent work has expanded into environmental applications with transformer neural networks for flood forecasting, demonstrating the evolution of his research into new application domains while maintaining core expertise in energy optimization. His scientific awards include: Best paper award ACM/IEEE Great Lakes Symposium on VLSI (2008) IEEE Fellow (2007-) Senior Member IEEE He has served as Editor-in-Chief for the Journal of Embedded Computing (2005) and as Program Chair for EUC2005: Embedded & Ubiquitous Computing. Professor Macii has advised PhD students including Alberto Bocca (2019-2023) whose thesis focused on compact modeling techniques for energy analysis and optimization of complex systems. He has led numerous research projects including CANP (2018-2020), R3-PowerUP (2017-2021), SERENA (2017-2020), AMable (2017-2021), and STAMP (2016-2019), demonstrating sustained research leadership across multiple funding mechanisms. He is active in the EDA - Electronic Design Automation research group and LAB 4 research laboratory at DAUIN, with research spanning VLSI-CAD, Smart City technologies, and Industry 4.0 applications. His work bridges theoretical computer engineering with practical applications in energy conservation across multiple domains.
Andrea Costamagna is a researcher affiliated with the École Polytechnique Fédérale de Lausanne (EPFL), working within the School of Computer and Communication Sciences and the Department of Communication Systems. His research focuses on logic synthesis, digital circuit design, and the intersection of machine learning with hardware implementation. His work includes optimizing digital circuits using techniques like resynthesis, resubstitution, and decomposition, with applications in FPGA design and low-power systems. Recent publications explore symmetry-based synthesis, glitch-aware power minimization, and the use of resistive switching devices in machine learning hardware. His research also extends to quantum physics modeling with deep learning.
Sule Ozev is a Professor in the School of Electrical, Computer and Energy Engineering at Arizona State University (ASU). She holds a Ph.D. in Computer Science and Engineering from the University of California, San Diego (2002), and has been a faculty member since 2008. Her research focuses on analog and mixed-signal circuit testing, fault-tolerant systems, and RF circuit reliability. She has published over 100 papers and holds a U.S. patent. Notable awards include the NSF CAREER Award (2006) and the ASU Joseph Palais Distinguished Faculty Scholar Award (2023-2024). Her education includes: Ph.D., Computer Science and Engineering, UC San Diego (2002) M.S., Computer Science and Engineering, UC San Diego (1998) B.S., Electrical Engineering, Bogazici University, Turkey (1995) Research Interests: Self-test and calibration techniques for analog/RF circuits, fault simulation, and reliability enhancement. Recent work includes BIST solutions for power management units, MEMS sensor calibration, and IoT security. Publications span RF impedance measurement, low-power systems, and marine sensor applications. Awards also include best paper recognitions at IEEE VLSI Test Symposium (2022) and European Test Symposium (2019). Grants include NSF-funded projects on adaptive test strategies and collaborative research on sensor networks. Service roles include associate editor for IEEE Transactions on VLSI Systems and program chairs for major conferences.
