جست‌وجوی استاد و پژوهشگر

Tushar Krishnaمشاهده پروفایل

دانشیار

• Computer Architecture
• Interconnection Networks
• Networks-on-Chip
• +۴ مورد دیگر

Tushar Krishna is an Associate Professor in the School of Electrical and Computer Engineering at Georgia Institute of Technology, with a courtesy appointment in the School of Computer Science. He earned his PhD in Electrical Engineering and Computer Science from MIT in 2014, an MSE in Electrical Engineering from Princeton University in 2009, and a B.Tech in Electrical Engineering from IIT Delhi in 2007. His research spans computer architecture, interconnection networks, networks-on-chip (NoC), and AI/ML accelerator systems, with a focus on optimizing data movement in modern computing platforms. His work is funded by NSF, DARPA, IARPA, SRC, Department of Energy, Intel, Google, Meta, Qualcomm, and TSMC. His papers have been cited over 17,000 times, with three receiving IEEE Micro's Top Picks recognition, one earning an honorable mention, and four winning best paper awards. Dr. Krishna leads the Synergy Lab at Georgia Tech and has developed several influential tools including ASTRA-sim for distributed AI/ML training, MAESTRO and SCALE-sim for accelerator design space exploration, and Garnet2.0 for NoC simulation. His recent work focuses on large language model acceleration, distributed training systems, and neuro-symbolic AI architectures. He has received numerous teaching and research awards including induction into the HPCA Hall of Fame (2022), the Class of 1940 Teaching Effectiveness Award (2018), and the Roger P. Webb Outstanding Mid-career Faculty Award (2024). HPCA Hall of Fame Inductee (2022) Roger P. Webb Outstanding Mid-career Faculty Award (2024) Richard M. Bass/Eta Kappa Nu Outstanding Junior Teacher Award (2023) Roger P. Webb Outstanding Junior Faculty Award (2021) Class of 1940 Course Survey Teaching Effectiveness Award (2018) Dr. Krishna currently serves as Associate Director for the Center for Research into Novel Computing Hierarchies (CRNCH) and co-chair of the Chakra Execution Traces and Benchmarks Working Group. He has held the ON Semiconductor (Endowed) Junior Professorship at Georgia Tech (2019-2021) and has been a visiting professor at MIT EECS, Harvard University CS, and a researcher at Intel's VSSAD group.

Bahar Asgariمشاهده پروفایل

استادیار

• Computer Architecture
• Domain-Specific Architecture Design
• Near Memory Processing
• +۳ مورد دیگر

Bahar Asgari is an Assistant Professor in the Department of Computer Science at the University of Maryland, College Park. She holds appointments in CS, UMIACS, and ECE, and directs the Computer Architecture and Systems Lab (CASL). Her research focuses on domain-specific architecture design, near memory processing, and reconfigurable computing. Before joining UMD, she worked at Google, contributing to system optimization and memory utilization strategies. Education: Ph.D., Georgia Institute of Technology, 2021. Research Interests: Developing energy-efficient architectures for sparse problems, scientific computing acceleration, FPGA optimizations, and reconfigurable hardware systems. Her work addresses challenges in memory efficiency, parallelization, and hardware-software co-design across domains like machine learning and IoT. Key Awards: 2024 UMD Excellence in Teaching Award 2023 DOE Early Career Award Advising & Grants: Supervises 9 graduate students and leads projects sponsored by NSF, DOE, and industry partnerships. Her lab explores systolic arrays, near-data processing, and fault-tolerant computing. Labs/Teams: Directs CASL, which builds next-generation computing systems through hardware innovation and algorithm-architecture co-design.

Brandon Reagenمشاهده پروفایل

استادیار

• Computer Architecture
• Hardware Acceleration
• Machine Learning
• +۳ مورد دیگر

Brandon Reagen is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University's Tandon School of Engineering, with affiliations in Computer Science, the Center for Advanced Technology in Telecommunications (CATT), and the NYU Center for Cybersecurity (CCS). He holds a PhD in Computer Science from Harvard (2018) and undergraduate degrees in Computer Systems Engineering and Applied Mathematics from the University of Massachusetts, Amherst (2012). His research focuses on computer architecture, hardware acceleration for deep learning and privacy-preserving computation, and VLSI design. He pioneered efficient deep learning accelerator designs through unsafe optimizations and contributed to benchmarking frameworks like Aladdin and MachSuite. His work spans privacy-preserving machine learning, secure computing systems, and hardware-software co-design for cryptographic protocols. Key achievements include the NSF CAREER Award (2024) and Siebel Scholar recognition (2018). His research centers on advancing secure computing through innovations like zero-knowledge proof accelerators (e.g., zkSpeed), fully homomorphic encryption frameworks (Orion), and entropy-guided privacy techniques for large language models. He leads interdisciplinary efforts at CATT and CCS to bridge hardware design and cybersecurity challenges. Reagen's contributions include over 50 publications in top-tier conferences (e.g., ISCA, ASPLOS, MLSys) and industry collaborations at Facebook AI. His work emphasizes practical solutions for encrypted computation efficiency, privacy-preserving inference, and scalable secure systems.

Azad J Naeemiمشاهده پروفایل

استاد

• Nanotechnology
• Nanoelectronics
• Spintronics
• +۵ مورد دیگر

Azad J Naeemi is a Professor holding the Dean's Professorship in the School of Electrical and Computer Engineering at the Georgia Institute of Technology. He serves as Editor-in-Chief of the IEEE Journal on Exploratory Computational Devices and Circuits and Associate Director for Computation of the NSF-supported National Nanotechnology Coordinated Infrastructure (NNCI). His educational background includes a B.S. in Electrical Engineering from Sharif University (1994) and M.S./Ph.D. in Electrical and Computer Engineering from Georgia Tech (2001/2003). Prior to academia, he worked as a design engineer in Tehran (1994-1999) and as a research engineer at Georgia Tech's Microelectronics Research Center (2004-2008). Professor Naeemi's research spans nanotechnology with focus on emerging nanoelectronic devices, spintronics, ferroelectric devices, and design technology co-optimization for CMOS/beyond-CMOS technologies. His work bridges materials, devices, circuits, and systems, particularly investigating integrated circuits based on nanoscale devices and interconnects. Educational research includes experiential learning environments for engineering education. Recent publications (2024-2025) demonstrate strong emphasis on spin-orbit torque MRAM, ternary content addressable memories, ferroelectric/antiferroelectric devices, and plasmonic circuits. Key trends include energy-efficient hardware accelerators, neuromorphic computing applications, and compact modeling for advanced technology nodes. His scientific honors include: IEEE Solid-State Circuits Society James Meindl Innovators Award (2022) IEEE Electron Devices Society Paul Rappaport Award (2008) NSF CAREER Award (2013) SRC Inventor Recognition Award (2010) Multiple Georgia Tech teaching awards Professor Naeemi leads research supported by NSF (including NNCI infrastructure) and SRC. His editorial role with IEEE JXCDC positions him at the forefront of exploratory computational devices. He previously served as General Co-Chair for the IEEE International Interconnect Technology Conference (2013). His work connects with Georgia Tech's Microelectronics Research Center and national nanotechnology initiatives through the NNCI network, focusing on computational infrastructure for nanoscale device characterization and design.

Muhammad Rashedمشاهده پروفایل

استادیار

• Electronic Design Automation (EDA)
• In-Memory Computing
• Artificial Intelligence Acceleration
• +۵ مورد دیگر

Dr. Muhammad Rashed is an Assistant Professor in the Department of Computer Science and Engineering at the University of Texas at Arlington, within the College of Engineering. He holds a Ph.D. in Computer Engineering from the University of Central Florida (2024) and a B.S. in Electrical and Electronics Engineering from Bangladesh University of Engineering and Technology (2015). Ph.D. : Computer Engineering, University of Central Florida, 2024 B.S. : Electrical and Electronics Engineering, Bangladesh University of Engineering and Technology, 2015 His research focuses on electronic design automation (EDA), in-memory computing, AI acceleration, and sustainable computing. He explores novel computing paradigms to overcome the limitations of traditional architectures, particularly in data-intensive applications such as AI and scientific computing. His work emphasizes hardware-software co-design and leveraging emerging non-volatile memories for energy-efficient processing. The 15 most recent publications highlight a consistent focus on in-memory computing, particularly in path-based and flow-based architectures, logic synthesis, and AI acceleration. Key themes include optimization, fault tolerance, verification, and the use of advanced data structures like sentential decision diagrams. His work is published in top-tier venues such as DAC, ICCAD, ASP-DAC, and IEEE/ACM journals. Scientific Awards: UTA CARES Grant for OER Creation Research Experiences for Undergraduates (REU) Grant Alireza Seyedi Doctoral Research Innovation Endowed Scholarship David T. & Jane M. Donaldson Memorial Scholarship IEEE/ACM William J. McCalla ICCAD Best Paper Award Nomination Best Research Video Award, Design Automation Conference (DAC) Dr. Rashed advises several graduate and undergraduate students in the NextGen Computing Lab and is involved in research grants including the UTA CARES Grant and REU funding. He actively contributes to academic service through roles such as conference TPC member, journal reviewer (e.g., IEEE TCAD, ACM TODAES), and committee participation in the department and college. His lab, the NextGen Computing Lab, is dedicated to building scalable, energy-efficient computing systems for next-generation AI and scientific workloads, aligning with national initiatives in advanced computing.

Austin Rovinskiمشاهده پروفایل

استادیار

• Computer Architecture
• VLSI
• Electronic Design Automation (EDA)
• +۵ مورد دیگر

Austin Rovinski is an Assistant Professor in the Department of Electrical and Computer Engineering at New York University’s Tandon School of Engineering. He specializes in chip design, electronic design automation (EDA), and open-source hardware methodologies. His research focuses on VLSI design, domain-specific accelerators, and chiplet-based systems. Prior to NYU, he held a postdoctoral position at Cornell University and earned all his degrees (Ph.D., M.S., and B.S.) from the University of Michigan. Education: Ph.D., Electrical Engineering, University of Michigan - Ann Arbor Master’s, Electrical Engineering, University of Michigan - Ann Arbor Bachelor’s, Electrical Engineering, University of Michigan - Ann Arbor Research Focus: Developing open-source EDA frameworks like OpenROAD Optoelectronic interconnect systems for 2.5D packaging Agile hardware design methodologies Reconfigurable sparse matrix accelerators RISC-V-based manycore processors (e.g., Celerity project) Key Contributions: Austin led the development of the OpenROAD RTL-to-GDS flow and contributed to the Sirius and Celerity projects. His work emphasizes reproducibility, democratizing chip design through open-source tools. Awards: IEEE Micro Top Picks (2015) Michigan EECS Outstanding Research Award (2016) NSF Graduate Research Fellowship Honorable Mention (2017, 2018) Advising & Grants: Actively mentors graduate students in chip design and EDA. His research is supported by NYU’s Tandon School of Engineering and collaborations with industry partners. Labs & Teams: Core contributor to the OpenROAD project, part of NYU’s hardware design and EDA initiatives, and collaborator on the Celerity manycore processor project.

David Blaauwمشاهده پروفایل

استاد

• Ultra-Low Power Circuits
• IoT and Sensor Networks
• RF Communication
• +۷ مورد دیگر

David Blaauw is the Kensall D. Wise Collegiate Professor of Electrical Engineering and Computer Science (EECS) at the University of Michigan. His research focuses on ultra-low-power analog/mixed-signal circuits, mm-scale sensors, neural networks, and biomedical applications. He leads the Blaauw Lab, which has pioneered innovations like the Michigan Micro Mote (M^3) and neural recording probes. His work emphasizes real-world deployability, with applications in environmental monitoring (e.g., monarch butterflies), medical devices, and robotics. Education: B.S. in Physics and Computer Science, Duke University (1986) Ph.D. in Computer Science, University of Illinois Urbana-Champaign (1991) Research Interests: Blaauw’s lab explores ultra-low-power computing, mm-scale systems, RF communication, in-memory computing, and genomics acceleration. Key projects include: Millimeter-scale computers (e.g., 0.04mm³ temperature sensors) Wireless neural interfaces for brain-machine communication Energy-efficient accelerators for edge AI and genomics Micro-robotics with sensing/actuation/computation Awards: IEEE Fellow 2016 SIA-SRC Faculty Award Motorola Innovation Award Best Paper Awards at ISSCC, ISCA, and RFIC Advising & Impact: Over 600 publications, 65 patents, and 4 startup companies spun from his lab. Current research includes genome sequencing accelerators (GenAx) and neural recording dust for brain mapping. He directs the Michigan Integrated Circuits Lab and chairs major conferences like ISSCC and DAC. Labs/Teams: Blaauw Lab (University of Michigan) Michigan Integrated Circuits Lab (MICAL)

• Digital Hardware Design
• Reliability Engineering
• Reconfigurable Devices
• +۳ مورد دیگر

Eleonora Vacca is a PhD student and Research Fellow in the Department of Automatic Control and Computer Science (DAUIN) at the Polytechnic University of Turin. She holds a B.S. in Electronic Engineering from the University of Palermo (2018) and an M.S. in Electronic Engineering-Embedded Systems from Politecnico di Torino (2021). Her research focuses on digital hardware design, reliability engineering, reconfigurable devices, and AI applications in aerospace and safety-critical systems. She is a member of the Aerospace and Safety Computing Lab and the CAD - Electronic CAD & Reliability Group (DAUIN). Her work addresses challenges such as radiation effects mitigation in space missions, fault-tolerant AI accelerators, and real-time anomaly detection in satellite telemetry. She has contributed to projects like the RAMSES CubeSat-1 Development (2025-2026), funded by commercial contracts. In 2024, she won the Best Student Paper Award at the NEWCAS Conference for her research on radiation effects in space missions. Vacca collaborates on teaching, including assisting in the course 'Electronic Calculators' for Computer Engineering students. Her recent publications explore AI resilience in RISC-V ecosystems, radiation environment analysis for space missions, and gesture recognition systems for smart cities. She actively contributes to conferences such as the ACM International Conference on Computing Frontiers and the IEEE International Smart Cities Conference.

Emre Salmanمشاهده پروفایل

استاد

• Integrated Circuits (ICs)
• VLSI Systems
• Energy-Efficient Computing
• +۵ مورد دیگر

Emre Salman is a Professor in the Department of Electrical and Computer Engineering at Stony Brook University (SUNY), where he directs the Nanoscale Circuits and Systems (NanoCAS) Lab. His research focuses on nanoscale IC design, energy-efficient computing, and biomedical electronics, with notable contributions to 3D integrated circuits and wireless energy harvesting for IoT and healthcare applications. Education : PhD in Electrical Engineering, University of Rochester (2009) MSc in Electrical and Computer Engineering, University of Rochester (2006) BSc in Microelectronics Engineering, Sabanci University, Turkey (2004) Research Interests : Salman’s work spans energy-efficient integrated circuits, secure IoT systems, and implantable medical devices. He pioneers techniques like charge-recycling logic and thermal-aware design for post-Moore computing. His group develops monolithic 3D ICs to address power/thermal challenges in AI accelerators and biomedical implants. Articles Trends : Recent publications highlight advancements in triboelectric energy harvesters for knee implants, thermal covert channel mitigation in 3D processors, and energy-efficient DNN accelerators. He emphasizes sustainability and security in emerging technologies like ReRAM-based computing and AC circuits for wireless IoT. Awards : 2023-2024 IEEE Distinguished Lecturer 2018 IEEE Region 1 Technological Innovation Award 2013 NSF CAREER Award Advising & Grants : Salman has directed multiple NSF, NIH, and industry-funded projects. He advises students on topics like hardware security and biomedical electronics, with a focus on translating research into commercializable technologies. Labs & Teams : The NanoCAS Lab collaborates with Brookhaven National Lab and industry partners (e.g., AMD, Samsung) to bridge academic research with real-world applications in energy-efficient computing and secure 3D ICs.

• Reliable and Fault-Tolerant Computing
• RISC-V Architecture
• FPGA-Based Systems
• +۱۲ مورد دیگر

Sarah Azimi is a fixed-term researcher at the Department of Control and Computer Science (DAUIN) within the College of Computer, Film and Mechatronics Engineering at Politecnico di Torino. She actively contributes to research and teaching in the domains of reliable computing, reconfigurable systems, and AI applications for space and smart city security. Research Interests: Reliability and fault tolerance in safety-critical and space systems RISC-V and FPGA-based architectures High-performance computing (HPC) and reconfigurable computing AI resilience and real-time gesture recognition for public safety Radiation effects and hardening techniques for aerospace applications Publication Trends: Her recent publications focus on RISC-V reliability, radiation effects in space missions, AI resilience in reconfigurable platforms, and smart city security through gesture recognition. Her work spans both journal and conference venues, emphasizing practical and mission-tailored solutions in embedded and aerospace computing. Scientific Awards: No awards explicitly mentioned in the provided text. Advising and Grants: Sarah Azimi supervises multiple PhD students including Federico Buccellato, Aobo Cui, and Giorgio Cora. She leads the competitive research project Safe Smart City: Detecting Violence and Requests for Help in Real Time Through Video Surveillance Devices (2024). She is also a member of the RAMSES CubeSat-1 Development project (2025–2026) and led the commercial research project on the Rempro fault-tolerant processor (2022–2023). Labs and Teams: She is a key member of the CAD - Electronic CAD & Reliability Group (DAUIN) at Politecnico di Torino, contributing to cutting-edge research in electronic design automation and system reliability for aerospace and terrestrial applications.

• FPGA Design
• VLSI Systems
• Logic Synthesis
• +۷ مورد دیگر

Pierre-Emmanuel Gaillardon is a Professor in the Department of Electrical & Computer Engineering and Adjunct Professor in the School of Computing at the University of Utah. He holds a joint appointment since July 2024, having previously served as Assistant Professor (2016–2019) and Adjunct Assistant Professor in Computing (2016–2019). His research focuses on FPGA design, VLSI systems, nanoelectronics, and hardware security. He leads projects in emerging devices like TIGFETs, compute-in-memory architectures, and radiation-hardened FPGA fabrics. Teaching includes courses on Digital VLSI Design, Embedded Systems Design, and thesis supervision. He has secured grants from NSF, DARPA, and industry partners totaling over $10M, addressing topics like FPGA redaction, neuromorphic systems, and environmental sensors. Notable awards include the NSF CAREER Award (2018) and IEEE Senior Member elevation (2016). He actively serves on IEEE committees for nanoelectronics and EDA tools, contributing to standards like OpenFPGA.

David Atienzaمشاهده پروفایل

استاد

• Embedded Systems
• Low-Power Computing
• Edge AI
• +۳ مورد دیگر

David Atienza is a Professor in the Department of Electrical Engineering at the School of Engineering, Swiss Federal Institute of Technology in Lausanne (EPFL), renowned for pioneering embedded systems education and research in ultra-low power computing. His innovative teaching methods, including using Nintendo DS consoles and smartphones to teach embedded systems, earned him the 2015 EPFL Teaching Award in Electrical Engineering. His research focuses on Embedded Systems , Edge AI , and Wearable Healthcare , with breakthroughs in energy-efficient hardware-software co-design for biomedical applications. Key contributions include open-source platforms like X-HEEP and HEEPocrates for ultra-low power edge computing, and frameworks like SzCORE for seizure detection benchmarking. His work bridges computer architecture with real-world healthcare challenges, emphasizing privacy-preserving algorithms and sustainable computing. Recent publications (2023-2025) reveal a dominant trend toward biomedical edge AI and sustainable computing , with 70% of articles targeting healthcare wearables (seizure detection, cough monitoring) and 30% addressing energy efficiency in data centers and edge devices. His research consistently integrates open-hardware principles (RISC-V) with novel algorithm-hardware co-design. Awards include: 2015 EPFL Teaching Award in Electrical Engineering section While specific advising details are unreported, his extensive publication record and leadership in multi-partner projects like Sustainable Textile Electronics (STELEC) indicate active graduate supervision and significant research funding. His group develops open-source hardware frameworks used globally in academia and industry. He leads the Embedded Systems Laboratory at EPFL, driving projects in ultra-low power RISC-V architectures, biomedical wearables, and sustainable computing. Current initiatives include carbon-aware data center frameworks and multi-modal health monitoring systems deployable on commercial wearables.

Charles E. Leisersonمشاهده پروفایل

استاد

• Parallel Computing
• Performance Engineering
• Algorithms
• +۶ مورد دیگر

Charles E. Leiserson is a Professor of Computer Science and Engineering at MIT, holding the Edwin Sibley Webster Professorship in Electrical Engineering and Computer Science. He leads the Supertech Research Group and is Faculty Director of the MIT-Air Force AI Accelerator. His work focuses on parallel computing, performance engineering, and algorithms. Leiserson is renowned for co-authoring the foundational textbook Introduction to Algorithms , widely used in computer science education globally. He has pioneered technologies like the Cilk multithreaded programming language and contributed to supercomputing architectures such as the Connection Machine CM-5. His research bridges theoretical computer science with practical applications, emphasizing cache-oblivious algorithms and compiler optimizations. Leiserson has received multiple awards for his academic contributions and educational impact, including the ACM-IEEE Ken Kennedy Award and Margaret MacVicar Fellow distinction at MIT. Education: B.S., Yale University, 1975 Ph.D., Carnegie Mellon University, 1981 Research Interests: Leiserson’s work addresses performance engineering challenges in post-Moore’s Law computing. His group develops algorithms, software systems, and hardware strategies for scalable parallelism. Key areas include parallel programming frameworks (e.g., OpenCilk), cache-aware algorithms, and compiler optimizations. He emphasizes making parallel computing accessible to mainstream programmers through tools like Cilk and educational initiatives such as MIT’s Software Performance Engineering course. Projects & Leadership: Leiserson leads the Supertech Research Group and contributed to the Cilk Arts Inc. venture, acquired by Intel. He chairs the MIT Undergraduate Practice Opportunities Program (UPOP) and teaches courses on algorithms and discrete mathematics. His leadership workshops for faculty have educated hundreds worldwide on team management in academia. Awards & Recognition: 2014 ACM-IEEE Ken Kennedy Award IEEE Taylor L. Booth Education Award ACM Paris Kanellakis Theory and Practice Award Member of the National Academy of Engineering Labs & Teams: Active in MIT’s CSAIL, Leiserson collaborates through the Supertech Group and Theory of Computation communities. His current projects include Tapir compiler infrastructure, graph neural network applications for anti-money laundering, and deterministic parallel scheduling algorithms.

Xin Fuمشاهده پروفایل

استاد

• Computer Architecture
• Machine Learning
• Energy-Efficient Computing
• +۲ مورد دیگر

Dr. Xin Fu is a Professor in Electrical and Computer Engineering at the University of Houston's Cullen College of Engineering, holding a PhD from the University of Florida. His research spans computer architecture, energy-efficient systems, machine learning acceleration, and hardware reliability, with applications in edge computing and quantum systems. Awarded the NSF CAREER Award and named Miller Scholar, he leads innovations in heterogeneous computing architectures. Research focuses on optimizing hardware-software co-design for AI workloads, with current projects in federated learning optimization, quantum computing reliability, and neural network acceleration. Recent publications demonstrate cross-cutting work in mobile AI deployment, adversarial defense mechanisms, and quantum error correction. Honors include: NSF Faculty Early CAREER Award (2014) Four-time recipient of competitive NSF research grants Miller Scholar recognition for teaching and research excellence

Darshika G. Pereraمشاهده پروفایل

استادیار

• Computer Engineering
• FPGA-Based Hardware Acceleration
• Neuromorphic Computing
• +۵ مورد دیگر

Darshika G. Perera is an Assistant Professor in the Department of Electrical and Computer Engineering at the University of Colorado Colorado Springs (UCCS). Her research focuses on FPGA-based hardware acceleration, neuromorphic computing, and embedded systems optimization with applications in machine learning, cryptography, and battery management systems. She holds a PhD and has extensive experience in designing reconfigurable architectures for compute-intensive tasks. Her work bridges theoretical algorithms with practical hardware implementations, emphasizing efficiency and real-time performance. Key research areas include FPGA design methodologies, neuromorphic hardware for AI applications, and embedded systems security. She has published widely on topics such as hardware-software co-design for edge computing, optimization algorithms for genomics, and blockchain applications in healthcare IoT. Her contributions also span data mining hardware accelerators and dynamic reconfiguration techniques for cryptographic systems. Dr. Perera’s work is characterized by interdisciplinary collaborations, combining principles from electrical engineering, computer science, and applied mathematics. She is committed to advancing next-generation edge-computing platforms through innovative architectures and methodologies.