Florian Brandner is an Associate Professor at Télécom Paris , Institut Polytechnique de Paris, and a member of the AuTonomous Critical Embedded Systems (ACES) team within the Information Processing and Communication Laboratory (LTCI) . His research focuses on compiler backend optimization for embedded processors , especially VLIW architectures , in the context of real-time systems . He specializes in worst-case execution time (WCET) optimization , code generation techniques, register allocation, and dynamic binary translation. His work addresses challenges in identifying code paths critical for WCET and ensuring predictable behavior in embedded environments. Academic Appointments: Associate Professor (HDR) at Télécom Paris (2025–present); previous roles at COMPSYS team, ENS Lyon; Microsoft Research; Technical University of Denmark. Research Grants: Involved in projects like Designing Formally Verified Predictable Architectures (CEA 2023–2026), Collaborative Action on Timing Interferences (ANR 2022–2026), and Time-Predictable Cache Management (CEA 2016–2019). Scientific Awards: Outstanding Paper at ECRTS'25, Best Paper at RTNS'22, RTNS'20, SoftCOM'17, and RTNS'15. Patents: Co-inventor of Time-Division Multiplexing Methods (US Patent US20210397488A1, French Patent FR3087982B1). Recent Publications highlight advancements in formal verification for memory controllers (Real-Time Systems 2023), causality modeling in timing anomalies (STTT 2022), and context-sensitive cache analysis (Real-Time Systems 2022). His work spans real-time systems theory, practical compiler design, and hardware-software co-verification.







