Luciano Lavagno is a prominent academic in computer science and engineering, specializing in asynchronous circuit design, logic synthesis, and embedded systems. He has collaborated extensively with researchers like Alberto Sangiovanni-Vincentelli, Joaquim Cortadella, and Alex Yakovlev. Key contributions: Hazard-free asynchronous circuits, STG manipulation, FPGA synthesis frameworks Research focus: Formal verification, design methodologies, hardware-software co-design His publications from 1991–2025 demonstrate sustained innovation in asynchronous control logic, embedded system validation, and machine learning hardware acceleration. Notable works include SIS (sequential synthesis) and Petrify (asynchronous controller tool). While his 2018 DiracDeltaNet work extended into neural network optimization, his core expertise remains rooted in formal methods for circuit design.