Hadi Esmaeilzadeh is an Associate Professor at the University of California, San Diego in the Department of Computer Science and Engineering . He previously served as an Assistant Professor at Georgia Tech (2013-2017) and holds the Halicioğlu Chair in Computer Architecture . As founder/director of the Alternative Computing Technologies (ACT) Laboratory and associate director of UCSD's Center for Machine Integrated Computing and Security (MICS) , his research drives cross-stack solutions for next-generation computer systems. Early tenure recipient at UCSD Coined the term "dark silicon" in computer architecture Developed Tabla/DnnWeaver open-source frameworks Research Interests span: Approximate Computing Neural Acceleration FPGA/ASIC Hardware Design Machine Learning Systems Dark Silicon Challenges Security/Privacy in Accelerated Systems Scientific Recognition : 4 CACM Research Highlights 4 IEEE Micro Top Picks Distinguished Paper Award (HPCA 2016) Inducted to ISCA Hall of Fame (2018) Teaching : Developed courses on accelerator design (CSE 240D) and alternative computing (CS 8803 ACT) Advocates for hands-on FPGA-based learning in Processor Design with FPGAs courses
Prof. Baker Mohammad serves as Professor and Director of the System on Chip Lab in the Department of Computer and Information Engineering at Khalifa University. With over 15 years of industrial experience at Intel and Qualcomm designing microprocessors and DSP chips, he bridges academic research with real-world engineering challenges in high-performance computing and low-power systems. His educational background includes: Ph.D. in Electrical and Computer Engineering, University of Texas at Austin (2008) M.S. in Electrical and Computer Engineering, Arizona State University B.S. in Electrical Engineering, University of New Mexico Dr. Mohammad's research spans cutting-edge domains where VLSI design converges with AI acceleration and emerging memory technologies . His work pioneers Memristor applications in environmental sensing (radiation, vacuum, glucose) and neuromorphic computing, while advancing energy harvesting systems for wearable electronics. The integration of in-memory computing with security primitives represents a paradigm shift in hardware design, moving beyond traditional CMOS limitations. His publication trajectory reveals accelerating focus on self-powered neuromorphic systems and RRAM-based architectures, with recent work (2021-2023) emphasizing hardware-software co-design for edge AI. Over 75% of his recent publications involve cross-disciplinary collaborations spanning materials science, chemistry, and biomedical engineering. Notable scientific recognition includes: IEEE TVLSI Best Paper Award 2016 IEEE MWSCAS Myrill B. Reed Best Paper Award Qualcomm Qstar Award for Performance Leadership KUSTAR IP Excellence Award Multiple SRC Techon Best Session Papers As a dedicated mentor, he has supervised over 15 graduate students while securing competitive funding from Khalifa University, ADEK, Qualcomm, Tii, and UAE space agencies. His grant portfolio demonstrates exceptional translational impact, converting fundamental research in memristive devices into drone flight computers and medical sensors. Current projects integrate academic rigor with industrial deployment timelines. The System on Chip Lab operates as a multidisciplinary hub where semiconductor physicists collaborate with AI researchers to develop RISC-V-based secure processors and piezoelectric nanogenerator systems. Recent expansions include partnerships with Tii for aerospace applications and medical device startups for glucose monitoring technology.
Professor Wayne Luk is a Professor of Computer Engineering at the Department of Computing, Faculty of Engineering, Imperial College London. He leads the Programming Languages and Systems Section and the Custom Computing Research Group, and directs the EPSRC Centre for Doctoral Training in High-performance Embedded and Distributed Systems and the Centre for Advanced Financial Engineering. He previously served as a Visiting Professor at Stanford University from 2006 to 2009. His research spans FPGA acceleration, quantum computing, deep learning optimization, and algorithm-hardware co-design, with affiliations to the CRUK Convergence Science Centre and the Engineering Secure Software Systems group. His research interests include computational modeling for particle physics, causal discovery in agent-based systems, and high-throughput digital electronics. Notable contributions include FPGA-accelerated algorithms for neural networks, quantum circuit simulation, and Bayesian optimization frameworks. His work emphasizes practical applications of reconfigurable hardware in fields like medical imaging, high-energy physics, and financial systems. Professor Luk is a Fellow of the Royal Academy of Engineering, IEEE, and BCS. His publications focus on advancing hardware-aware machine learning, FPGA-based acceleration techniques, and scalable design methodologies. His research bridges theoretical computer science with applied engineering, addressing challenges in real-time systems, embedded computing, and next-generation computing architectures. His academic leadership includes directing interdisciplinary centers and training programs, fostering collaboration across computing, engineering, and physics. Current projects explore quantum computing tools, causal inference systems, and high-performance graph neural networks for particle physics applications.
Wolfgang Kunz is a Full Professor (C4, W3) and Chair of Electronic Design Automation at the Technische Universität Kaiserslautern since 2001. His academic career spans multiple prestigious institutions, including Goethe-University Frankfurt/Main and the University of Massachusetts, Amherst. He has held leadership roles such as Dean (2005-2007) and Vice-Dean (2007-2009) at TU Kaiserslautern. Habilitation (Dr. rer. nat. habil.), Computer Science, University of Potsdam (1996) Doctoral degree (Dr.-Ing.), Electrical Engineering, University of Hannover (1992) Dipl.-Ing. degree, Karlsruhe Institute of Technology (1989) His research focuses on hardware verification, security, and optimization, particularly in embedded systems and processors. His work on formal verification methods has been commercialized by companies like Synopsys, Mentor Graphics, and Siemens EDA. His 2016-2021 publications address critical security issues such as Spectre/Meltdown and introduce innovative verification frameworks adopted by industry leaders like Infineon and OneSpin Solutions. Scientific awards include the IEEE Fellow (2006), German IT Society Award (2005), and TU Kaiserslautern Distinguished Teaching Award (2016). He has served on editorial boards of major journals and coordinated the Erasmus Mundus European Master Program in Embedded Computing Systems since 2010. Key students: Jörg Bormann, Raik Brinkmann, Tobias Ludwig Collaborations: Siemens EDA, Infineon, AbsInt, Intel SCAP Spin-offs: LUBIS EDA, OneSpin Solutions
Nam Sung Kim is the W. J. "Jerry" Sanders III-Advanced Micro Devices Inc. Endowed Chair and holds a Professorship in Electrical and Computer Engineering at the University of Illinois. He is also affiliated with the Siebel School of Computing and Data Science, Coordinated Science Lab, and National Center for Supercomputing Applications (NCSA). His research focuses on computer architecture, memory systems, chiplet integration, and hardware security. Key areas include energy-efficient computing, processing-in-memory (PIM), and mitigating hardware vulnerabilities like rowhammer attacks. Kim has received prestigious awards including IEEE Fellow (2016), MICRO Hall of Fame (2018), NAI Fellow (2023), and NSF CAREER Award (2015). His work spans publications in top venues like ASPLOS and IEEE journals, addressing topics such as CXL-based memory systems, DRAM module optimization, and GPU architecture improvements. Collaborations emphasize interdisciplinary research in hardware-software co-design and emerging technologies. His labs and teams at Coordinated Science Lab and NCSA drive innovations in scalable computing, near-memory processing, and cloud infrastructure for AI workloads. Ongoing projects include developing resilient memory hierarchies and accelerating large-scale machine learning models through novel architecture designs.
Tosiron Adegbija is an Associate Professor in the Department of Electrical and Computer Engineering at the University of Arizona, where he serves as Director of Graduate Studies and Thomas R. Brown Endowed Fellow. He is a member of the Graduate Faculty and actively contributes to research and teaching in computer architecture and embedded systems. Education: PhD in Electrical and Computer Engineering, University of Florida, 2015 MS in Electrical and Computer Engineering, University of Florida, 2011 BS in Electrical Engineering, University of Ilorin, Nigeria, 2005 His research centers on energy-efficient computing with a focus on bio-inspired computer architecture , including spiking neural network (SNN) accelerators and in-memory computing. He also explores domain-specific architectures , adaptable memory systems , and microprocessor optimizations for IoT . His work leverages novel memory technologies like STT-RAM to enhance performance and reduce energy consumption in embedded and resource-constrained systems. Recent publications highlight trends in hybrid SNN acceleration, domain-specific accelerator generation, and system-level design space exploration. His research is increasingly focused on neuromorphic computing, automated hardware design, and ultra-efficient architectures using emerging materials like antiferromagnetic tunnel junctions. Scientific Awards: National Science Foundation (NSF) CAREER Award (2019) Elected IEEE Senior Member (2020) Best Paper Award at IEEE ISVLSI (2014) Teaching Award, University of Arizona (2018) ACM GLSVLSI Travel Award (2015) He advises numerous graduate and undergraduate students, many of whom have pursued careers at institutions like Pacific Northwest National Labs, Micron Technology, and Amazon. He has secured significant funding, including a $1.9M NSF FuSE2 grant for energy-efficient computing. His lab collaborates with UA Physics, CMU, and UNL. He has also developed educational tools for Chipyard and RISC-V, supporting hands-on learning in computer architecture. Labs and Research Teams: Leads a research group focused on bio-inspired and domain-specific computing, fostering innovation in energy-efficient hardware. The lab emphasizes hardware/software co-design, neuromorphic engineering, and real-world deployment in IoT and biomedical applications.
Mirjana Stojilovic is a Researcher at École Polytechnique Fédérale de Lausanne (EPFL) in the School of Computer and Communication Sciences (IC), specifically within the Institute of Computer Engineering (IINFCOM) and the Parallel Systems Architecture Laboratory (PARSA). She also serves as a Lecturer in the SSC - Teaching department at EPFL. Her office is located at INJ 235, Station 14, 1015 Lausanne, Switzerland. Mirjana Stojilović received her Dipl. Ing. and Ph.D. degrees from the School of Electrical Engineering, University of Belgrade, in 2006 and 2013, respectively. Her academic journey includes collaborating with the Processor Architecture Laboratory at EPFL as a Guest Researcher from 2010 to 2013, working at the University of Applied Sciences Western Switzerland as a senior researcher from 2013 to 2016, and joining the Parallel Systems Architecture Lab at EPFL in October 2016. Dr. Stojilovic's research spans field-programmable technology, electronic design automation (EDA), and electrical-level attacks and countermeasures for reconfigurable hardware. Her work bridges the gap between hardware design and security, with a particular focus on vulnerability analysis and protection mechanisms for FPGA-based systems in cloud environments. She has made significant contributions to understanding side-channel attacks, fault injection techniques, and secure multi-tenancy solutions for shared hardware resources. Her extensive publication record reveals a clear research trajectory from traditional FPGA design and EDA topics toward increasingly security-focused investigations. Recent work demonstrates deep expertise in power analysis attacks, hardware trojans, and countermeasures for cloud-based FPGA systems, reflecting the growing importance of hardware security in distributed computing environments. Scientific Awards and Recognitions: Best Paper Award at 2016 International Symposium on Electromagnetic Compatibility (EMC Europe 2016) Young Scientist Award at 33rd International Conference on Lightning Protection (ICLP2016) Young Author Best Paper Award at the 20th Telecommunication Forum in Belgrade (TELFOR 2012) EPFL School of Computer and Communication Sciences (IC) Teaching Award (2015) Nominated for Best Paper Award at the International Conference on Field-Programmable Technology (FPT) (2020) Dr. Stojilovic has advised numerous PhD students including Coulon Louis, Pirayadi Rouzbeh, and Shrivastava Shashwat, along with past EPFL PhD students Glamocanin Ognjen and Mahmoud Dina. She has supervised dozens of semester and diploma projects focusing on hardware security, FPGAs, design automation, side-channel attacks, and cloud computing. Her service to the academic community includes serving on program committees for FPGA, FCCM, FPL, and DATE conferences, reviewing for multiple IEEE and ACM journals, and acting as associate editor for IEEE ESL and ACM TRETS. As a member of the Parallel Systems Architecture Laboratory at EPFL, Dr. Stojilovic leads research projects investigating security aspects of reconfigurable hardware systems. Her team works at the intersection of computer architecture, electronic design automation, and hardware security, with particular emphasis on vulnerabilities and protections for shared FPGA resources in cloud environments.
David Jao is a Professor in the Department of Combinatorics and Optimization at the University of Waterloo. His research focuses on post-quantum cryptography, particularly leveraging isogenies of supersingular elliptic curves for secure cryptographic protocols. He is renowned for co-developing the Supersingular Isogeny Key Encapsulation (SIKE) protocol, a leading candidate for post-quantum cryptography standards. His work spans theoretical foundations and practical implementations, including optimizing isogeny-based systems for embedded devices and ARM processors. Research interests include isogeny-based cryptosystems, elliptic curve cryptography, zero-knowledge proofs, and cryptographic security against quantum attacks. He explores applications of expander graphs and Ramanujan graphs in cryptography, alongside algorithmic improvements for cryptographic protocols such as SIDH (Supersingular Isogeny Diffie-Hellman). Key contributions include advancements in key compression techniques for SIKE, side-channel attack mitigation, and formalizing security models for post-quantum key exchange. His publications analyze cryptographic hardness assumptions, such as the discrete logarithm problem in finite groups and the semidirect product structure in isogeny-based systems. Jao’s work bridges theoretical mathematics and applied cryptography, with a focus on ensuring practical security in next-generation cryptographic systems. His research addresses challenges in quantum-resistant authentication, key establishment, and digital signatures, often emphasizing efficiency and resistance to both classical and quantum attacks.
Jignesh M. Patel is a Professor in the Computer Science Department at Carnegie Mellon University , focusing on Data Management , System Efficiency (e.g., Scalable Data Platforms), and Human Efficiency (e.g., LLM-Based Query Interfaces). His work bridges Database Systems , Machine Learning , and Human-Computer Interaction . Co-founder of four startups: Paradise (1997), Locomatix (2007), Quickstep (2015), and DataChat (2017). Member of SIGMOD 2025 (AE) , CIDR 2024 (Co-Chair) , and other program committees. Research Interests include efficient data analysis algorithms , LLM-based data interaction , and systems security . His group develops platforms combining scalability and user productivity . Scientific Awards include Best Paper Awards at SIGMOD and VLDB, and Fellowships from AAAS, ACM, and IEEE. He also received Teaching Awards at CMU. Professional Activities feature co-founding startups , serving on program committees , and teaching courses like Database Systems and Advanced Database Systems at CMU.
Björn Brandenburg is a researcher at the Max Planck Institute for Software Systems (MPI-SWS) in Kaiserslautern, Germany. His work focuses on real-time systems, scheduling algorithms, and operating system design, with a particular emphasis on predictable resource allocation and performance guarantees in multiprocessor and cyber-physical environments. His research interests include real-time response-time analysis (e.g., PROSA ), locking protocols for multiprocessor systems, side-channel mitigation in cloud environments, and the verification of real-time scheduling policies. He has contributed to foundational studies on deadline failure probabilities, self-suspending tasks, and predictable real-time Linux implementations. Scientific awards include recognition for outstanding papers on TimerShield (2017) Offline Equivalence (2017) . His work intersects with practical systems like LITMUSRT and ROS 2, aiming to bridge theoretical guarantees with real-world applications in safety-critical and distributed real-time systems.
Kyle C. Hale is an Associate Professor at Oregon State University's School of Electrical Engineering and Computer Science (College of Engineering). He holds a Ph.D. and M.S. from Northwestern University (2016, 2013) and a B.S. in Computer Science from UT Austin (2010). Prior to joining Oregon State in 2024, he served as an Associate Professor at Illinois Tech in Chicago. His research spans operating systems, high-performance computing (HPC), virtualization, computer architecture, and system security. Current work focuses on specialized system software stacks for emerging computing paradigms like memory disaggregation and parallelism optimization. He leads the HExSA Lab and collaborates with the HiPCastor group. Scientific Awards: NSF CAREER Award (2023-2028) Illinois Tech College of Computing Excellence in Research (2023) Illinois Tech College of Computing Excellence in Teaching (2021) Illinois Tech Department of Computer Science Teacher of the Year (2020) EuroSys '22 Best Artifact Award Recent Research Trends: His publications emphasize compiler techniques for memory-disaggregated systems, optimizing parallel runtimes through hardware-software integration, virtualization at fine granularities, and accelerating machine learning workloads via system-level innovations. Keywords include HPC, virtualization, parallelism, and secure execution contexts. Teaching: Courses taught include Computer Architecture (CS/ECE 472), System Security (CSP 544), Operating Systems (CS 450), and advanced topics in serverless/edge computing. He actively recruits PhD students to the HExSA Lab.
Brandon Lucia is a Professor in the Department of Electrical and Computer Engineering at Carnegie Mellon University's College of Engineering. He holds the Kavčić-Moura Professorship and leads the Abstract research group. As CEO and co-founder of Efficient Computer Corp., he bridges academic research with commercial applications in energy-efficient computing. Dr. Lucia received his Ph.D. in Computer Science and Engineering from the University of Washington in 2013, following an MS from the same institution in 2010 and a BS in Computer Science from Tufts University in 2007. His research focuses on the intersection of computer architecture, computer systems, and programming languages, particularly in energy-constrained environments. His primary research interests include intermittent computing, energy harvesting computers, orbital edge computing, and parallel computing systems. Lucia's work addresses fundamental challenges in creating programmable, reliable computing devices that operate without batteries by harvesting energy from their environments, with applications in sensing, medical implants, and space systems. He also investigates software systems and architectures for making parallel computing correct, reliable, and efficient in the post-Moore's Law era. Lucia's publication record shows a clear trajectory toward orbital edge computing and nanosatellite systems, with recent work focusing on computational constellations, visual navigation for satellites, and energy-efficient processing in space. His research spans both theoretical foundations of intermittent computing and practical implementations in hardware and software. 2021 Sloan Research Fellowship 2018 NSF CAREER Award 2018 ASPLOS Best Paper Award IEEE MICRO Top Picks in Computer Architecture (2009, 2010, 2016) 2015 OOPSLA Best Paper Award 2019 IEEE TCCA Young Computer Architect Award 2022 Engineering Faculty Award As an advisor, Lucia has mentored numerous graduate students including Brad Denby, Zhuo Cheng, and Kyle McCleary, many of whom have become co-authors on his significant publications. His lab developed the world's first batteryless PocketQube nanosatellite (Tartan-Artibeus-1), which was deployed to low-Earth orbit aboard the SpaceX Transporter-3 Rocket. Lucia's research has received funding from sources including NSF, DARPA, Google, and VMware, supporting both fundamental research and practical implementations of energy-harvesting computing systems.
Mehmet Esat Belviranli is an Assistant Professor in the Computer Science Department at the Colorado School of Mines, where he directs the High Performance Systems and Software Lab (HyperSys). His research focuses on increasing resource utilization in heterogeneous architectures through runtime systems, scheduling algorithms, and performance modeling, with publications in top venues including MICRO, PPoPP, and SC. Education: Ph.D. in Computer Science, University of California, Riverside (2016) M.S. in Computer Science, Bilkent University (2009) B.S. in Computer Science, Bilkent University (2006) Belviranli's research spans heterogeneous architectures, runtime systems, performance modeling, parallel programming, autonomous computing, deep learning acceleration, cyber-physical systems, and edge-cloud platforms. His work develops analytical models and programming abstractions to address resource management, scheduling, and security challenges in diversely heterogeneous systems, with applications in edge computing, autonomous systems, and machine learning acceleration. Recent projects emphasize real-world constraints and security implications. His publication trends reveal increasing focus on edge-cloud resource management (e.g., HARNESS), security vulnerabilities in heterogeneous systems (e.g., MC3), and deep learning acceleration under resource constraints. Key themes include memory contention modeling, scheduling for cyber-physical systems, and concurrent DNN execution, reflecting a shift toward practical deployment in security-sensitive edge environments. Scientific Awards: U.S. Air Force Research Lab Summer Faculty Fellowship Award (2022) U.S. Air Force Research Lab Summer Faculty Fellowship Award (2021) Oak Ridge National Laboratory Significant Event Award (2019) Best Paper Finalist, IEEE HPEC 2018 Outstanding Paper Award, DATE 2024 Belviranli mentors Ph.D. students Ismet Dagli (MLCommons Rising Star 2024, CGO'24 SRC finalist) and Justin Davis (DATE'24 Outstanding Paper Award winner). He has secured $2M+ in funding from NSF, DoE, and SRC, including an NSF-SaTC grant on mobile security (2024), a DoE grant on superconductive systems (2023), and an NSF FuSe grant on graphene nanoribbons (2023), often leading multi-institutional teams from Rochester, Virginia, Arizona, and Minnesota. The HyperSys Lab develops ecosystems for high-performance heterogeneous systems, with recent projects including HARNESS for edge-cloud resource management and MC3 for mobile SoC security. The lab has received equipment donations from Google Coral.ai and Xilinx, and collaborates with national labs on security challenges and next-generation semiconductor technologies.
Jiang Hu is a Professor in the Department of Electrical and Computer Engineering at Texas A&M University, holding the Eric D. Rubin '06 Endowed Professorship. He also serves as Co-Director of Graduate Programs and is affiliated with the Computer Science & Engineering department. His research focuses on VLSI design automation, machine learning applications, and hardware security. He has held roles as editor for IEEE Transactions on CAD and ACM Transactions on Design Automation, and chaired the 2012 ACM International Symposium on Physical Design. Education: B.S. in Optical Engineering (Zhejiang University, 1990), M.S. in Physics (1997), and Ph.D. in Electrical Engineering (University of Minnesota, 2001). He worked at IBM Microelectronics before joining Texas A&M in 2002. Research interests include energy-efficient VLSI circuits, on-chip communication fabrics, analog layout automation, and AI-driven EDA. Recent work emphasizes machine learning for design closure, privacy-preserving frameworks, and systolic array-based architectures. Awards: IEEE Fellow (2016) Humboldt Research Fellowship (2012) Multiple best paper awards at DAC, ICCAD, and ASPDAC Advising and grants: Leads initiatives like the SLICE project, NSF workshops on ML-EDA infrastructure, and serves as Editor-in-Chief of ACM TODAES since 2024. His work bridges academic research and industry applications in EDA and semiconductor design. Labs/Teams: Active contributor to open-source tools like ALIGN for analog layout generation and collaborations on machine learning for EDA commons.
Franz Franchetti is the Kavčić-Moura Professor of Electrical & Computer Engineering at Carnegie Mellon University. He serves as Associate Dean for Research and Director of the Engineering Research Accelerator at CMU. Education: Ph.D. in Computational Mathematics (Vienna University of Technology, 2003) M.Sc. in Technical Mathematics (Vienna University of Technology, 2000) His research interests focus on automatic performance tuning and program generation for emerging parallel computing platforms , including multicore CPUs , GPUs , and 3DIC chip design . He leads the SPIRAL effort to automate highly optimized software libraries and explores domain-specific compiler transformations in HPC applications for smart grids and material sciences . Recent work extends SPIRAL to quantum computing . The scientific awards Franchetti has received include the Gordon Bell Prize (2006) , HPC Challenge Class II Award (2010) , and the CIT Dean's Early Career Fellowship (2013) . He and his students have won multiple Best Paper Awards at HPEC, DAC, and ISPA ACM TODAES Best Paper (2014) Student Research Competition wins (PACT 2024, CGO 2023) Franchetti has advised students like Richard Veras and Thom Popovici . He has secured significant grants from agencies such as DARPA, DOE, NSF, and industry partners (Intel, NVIDIA, Mercury). He co-founded SpiralGen, Inc. and holds leadership roles in organizations like ASciNA Western Pennsylvania and as Honorary Consul of Austria in Pittsburgh.
